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Large-Scale Photonic Integrated Circuits

Large-Scale Photonic Integrated Circuits
Large-Scale Photonic Integrated Circuits

Large-Scale Photonic Integrated Circuits

Radhakrishnan Nagarajan ,Senior Member,IEEE ,Charles H.Joyner ,Member,IEEE ,Richard P.Schneider,Jr.,Jeffrey S.Bostak ,Member,IEEE ,Timothy Butrie,Andrew G.Dentai ,Fellow,IEEE ,Vincent G.Dominic,Peter W.Evans,Masaki Kato,Mike Kauffman,Damien https://www.sodocs.net/doc/0410202525.html,mbert,Sheila K.Mathis,Atul Mathur,Richard https://www.sodocs.net/doc/0410202525.html,es,Matthew L.Mitchell,Mark J.Missey,Sanjeev Murthy,Alan C.Nilsson,Frank H.Peters,Stephen C.Pennypacker,Jacco L.Pleumeekers,Randal A.Salvatore ,Member,IEEE ,Rory K.Schlenker,

Robert B.Taylor,Huan-Shang Tsai,Michael F.Van Leeuwen,Jonas Webjorn,Mehrdad Ziari,Drew Perkins,Jagdeep Singh,Stephen G.Grubb,Michael S.Ref?e,David G.Mehuys ,Member,IEEE ,

Fred A.Kish ,Senior Member,IEEE ,and David F.Welch ,Senior Member,IEEE

Abstract—In this paper,100-Gb/s dense wavelength division multiplexed (DWDM)transmitter and receiver photonic in-tegrated circuits (PICs)are demonstrated.The transmitter is realized through the integration of over 50discrete functions onto a single monolithic InP chip.The resultant DWDM PICs are capable of simultaneously transmitting and receiving ten wave-lengths at 10Gb/s on a DWDM wavelength grid.Optical system performance results across a representative DWDM long-haul link are presented for a next-generation optical transport system using these large-scale PICs.The large-scale PIC enables signi?cant reductions in cost,packaging complexity,size,?ber coupling,and power consumption.

Index Terms—Integrated optoelectronics,optical ?ber commu-nication,optical receivers,optical transmitters.

I.I NTRODUCTION

T

HE EXPLOSIVE “Moore’s Law”growth of integrated electronics [1],along with the similarly explosive growth of the Internet,has contributed to growing demand for commu-nications networks offering greater bandwidth and ?exibility at lower cost.Monolithic InP-based photonic integrated circuits (PICs),if able to provide suf?cient functionality,performance,and cost reduction,offer compelling solutions for such net-works,while also providing the same inherent scalability that has bene?ted Si-based integrated electronics.However,since the early proposals for photonic integration [2]–[5],progress in InP PIC technology has been relatively slow.Today,large-scale PICs (LS-PICs)with high levels of integration

(50components/chip)remain con?ned to the laboratory.There are myriad reasons for this slow rate of maturity.Numerous technological barriers associated with InP semiconductor pro-cessing have been one of the strongest inhibitors—including dif?culty in achieving the requisite process uniformity and reproducibility—on a manufacturing scale—in such processes as epitaxy,lithography,dry etching,etc.Additionally,mono-lithically integrating numerous devices and functions,while at the same time minimizing process complexity,has proven challenging from a design standpoint,due to requirements associated with active/active and active/passive transitions,electrical and optical isolation,compromises in discrete device

Manuscript received July 23,2004;revised November 30,2004.

The authors are with In?nera Corporation,Sunnyvale,CA 94089USA (e-mail:fkish@in?https://www.sodocs.net/doc/0410202525.html,).

Digital Object Identi?er 10.1109/JSTQE.2004.841721

performance,etc.As a result,early versions of LS-PICs,even if successful in demonstrating useful functionality,have fallen short in demonstrating the levels of performance and manu-facturability necessary to achieve commercial viability.It is also interesting to note that “industry pull”may have played a role in this slow development path,particularly in the past 10years.Since all-optical wavelength division multiplexing (WDM)networks based on Erbium doped ?ber ampli?er (EDFA)technology rose to prominence in the 1990s,meeting the demands of telecommunications bandwidth while in effect circumventing the need for optical-electronic-optical (OEO)conversion,the motivation for commercial development of large scale photonic integration that would enable such ap-proaches was somewhat dampened.

In this paper,we report the design and operating characteristics of the ?rst commercially deployed monolithic large-scale PICs providingtransmitandreceivefunctions.TheseLS-PICswerede-velopedtobeconsistentwiththefunctionality,cost,andreliability requirements of a new telecommunications network architecture termeda“digitalopticalnetwork”whereinOEOregenerationand add–drop functionality can be drastically increased throughout the network due to the cost reduction enabled by the integration of ten transmitter channels and ten receiver channels onto pho-tonic integrated circuits.The transmitter (TX)PIC includes over 50discrete functions integrated monolithically on a single chip,spread over ten channels with an aggregate data capacity of 100Gb/s.The monolithic receiver (RX)PIC supports a similar aggre-gate data rate of 100Gb/s—the ?rst time a matched TX/RX pair operating at this data rate has been produced.The chips are man-ufactured on InP substrates,leveraging many of the advances in III-V semiconductor processes manufacturing that have arisen in the past decade.This level of integration is more than an order of magnitude greater than previously demonstrated in a commercial system,and thus represents a signi?cant milestone in PIC devel-opment.

II.P ROGRESSION OF P HOTONIC I NTEGRATED

C IRCUIT

D EVELOPMENT

Recent concurrent trends suggest that the timing may be right for commercial development of LS-PICs,both from the perspective of technological capability and market receptive-ness.Steady progress in the InP components ?eld in the last 10years has led to improved InP process capability,which has

1077-260X/$20.00?2005IEEE

contributed to not only signi ?cant progress in the performance and commercial availability of discrete devices,but also the commercial introduction of the ?rst InP-based PICs,with 2–4integrated functions.Such progress has helped to lay the groundwork for a LS-PIC technology meeting increasingly aggressive cost requirements,as will be further described in this paper.Additionally,it is increasingly clear that the economics of current WDM networks are optimal only for maximum capacity and reach,and do not scale well to new demands for greater ?exibility (e.g.,add –drop functionality).As a result,industry acceptance for complex LS-PICs as the enabling foundation technology in new OEO-based telecommunications schemes may prove stronger in the future.

Improvements in InP fabrication/process capability have progressed on multiple fronts,and have had profound impact on technological capability.InP substrate quality has improved consistently over the past 20years,and now conductive sub-strates are available to 4inch diameters with dislocation etch pit densities (EPD)of less that 500cm ,rivaling GaAs.Fe-doped semi-insulating substrates have also improved;boules grown using the vertical gradient freeze (VGF)technique and ex-hibiting EPDs of less than 5000cm have become recently available.Manufacturers are also now reporting availability of substrates up to 6in in diameter.Metalorganic vapor phase epitaxy (MOVPE)equipment has undergone an even more dramatic revolution.The current generation of manu-facturing-capable multiple wafer MOVPE reactors became available in the early 1990s,and with re ?nements since then,are now capable of consistently producing wavelength unifor-mities

of

nm or better,thickness uniformities of better

than 2%,and defect (particle)densities approaching 1cm ,on 3-and 4-in InP substrates.These levels of demonstrated performance,along with concurrent improvements in system reliability and increasing use of statistical process control methodologies,have been essential to enabling manufacture of progressively more complex photonic integrated circuits by ensuring a consistent materials baseline from which to build.Developments in the dry etching ?eld,in particular in the areas of improved sidewall roughness and cross-section targeting,have also contributed to overall improvement in InP process capability.Relevant etching techniques include reactive ion etching (RIE),and its more versatile variants:electron cyclotron resonance (ECR)and inductively coupled plasma (ICP)etching,which employ high-density plasmas to achieve high etch rates with good uniformity and reduced damage.Other areas in which improvement has made signi ?cant impact on overall InP process capability includes ?ne-line lithography and interconnect metallization.

Improved InP process capability has led directly to commer-cial impact with the growing deployment of the ?rst photonic integrated circuits in the optical transport network.The simplest photonic integrated devices are spot size converter (SSC)inte-grated lasers [6].Electroabsorption modulated lasers (EMLs),consisting of a continuous-wave (CW)DFB or DBR laser integrated with a passive transition element and an electroab-sorption modulator (EAM)to provide modulation bandwidths in excess of 10Gb/s,were introduced more than a decade ago [7],[8].The communication data rate possible using the EML exceeds that possible using commercially available directly modulated lasers (DMLs)for long-reach and intermediate reach telecommunications applications [including dense WDM (DWDM)applications].Commercial tunable lasers,to address sparing and emerging optical add/drop multiplexer (OADM)applications,have taken advantage of integration techniques in a variety of ways.The tunable sampled grating (SG)DBR laser represents one such approach [9],[10],employing a four-section DBR laser with integrated gain,phase,and two tunable grating sections.More recently,single channel DBR and SG-DBR lasers have been integrated with EAMs to provide a tunable 10Gb/s EML [11],[12]and a single-channel tunable SG-DBR laser with integrated SOA has also been developed [13].Both of these innovations have resulted in an increase in PIC complexity (in terms of functions/chip)by 2–4times.Another example of a commercially available PIC developed to address the tunable laser market is the wavelength selectable laser array [14].This device employs multiple laser (DFB)channels that are combined to a single output,so provide no increase in functionality despite a somewhat more complex integration scheme.All of these small-scale PICs meet the per-formance,cost and reliability requirements for deployment in the telecommunications network.However,their functionality remains limited with the relatively low level of integration

(5integrated functions/chip),and as such they cannot address more complex system needs,such as full-scale OEO conversion in a DWDM system.Higher levels of integration (up to 12in-dependently addressable channels)have been achieved in data communication using parallel optical arrays of GaAs-based vertical cavity surface emitting lasers operating at 10Gb/s [15],[16].However,such devices are currently limited to short-reach applications and cannot provide for sophisticated functions such as OEO conversion.

More complex PICs have been demonstrated in the laboratory,and while this work has not yet proven commercially viable,it has proven crucial in furthering the groundwork for commercial LS-PICs.Multiple wavelength EMLs [17],[18]include an array of DFBs integrated with a multimode interference (MMI)combiner into a single output channel,followed by an SOA and an EAM.Aside from the discrete wavelength steps between channels in the array,continuous wavelength tuning of the entire array is possible using a thermoelectric cooler (TEC).Arrayed waveguide grating(AWG)[also known asa phasedarray grating (PHASAR)]technology [19]enables more complex frequency-selective integration schemes,and such functionality may be indispensable to LS-PIC design.Demonstrations of AWG integration into transmitter and receiver PICs include multiplexed laser sources [20]–[22]and demultiplexing receiver PICs [23]–[26].In the latter demonstrations,the AWG is used to demultiplex from a multiwavelength input,into a multiple element array of photodetectors,for channel-level detection.Other uses of AWGs in more complex PIC ’s include a lossless 16-channel wavelength selector,making use of

two AWGs in series with an array of SOAs [27],a

2

2optical cross-connect using four AWGs in a single chip with Mach –Zehnder Interferometers (MZIs)[28],and a multichannel modulation circuit employing eight channels of SOAs and EAMs with a single AWG with 25-GHz spacing [29].

While crucial in establishing a technological foundation from which to build,these examples provide neither the requisite functionality nor the demonstrated performance and yield/man-ufacturability upon which to base commercial DWDM carrier network architectures.These failures have several origins.For one,much of the PIC research described in the literature is not closely coupled to a network systems development.As a result,critical functionality required for commercial network operation is missing.Moreover,academic R&D is by nature focused on early-stage demonstration,while largely neglecting manufac-turability and reliability concerns that are of principal impor-tance to enabling commercial network deployment of LS-PICs.That InP device and PIC development has made such signi ?-cant progress is a testament both to the amenability of this mate-rials system to various integration strategies,and to steady mat-uration of the underlying process technologies.However,until now the feasibility of producing PICs with a high level of in-tegration

(10components),and with performance and yield suf ?cient to meet the demands of commercial networks,has been generally regarded to be extraordinarily low —and corpo-rate spending toward such development has re ?ected this notion.Indeed,with the complexities presented by relatively immature InP process technologies,and given the high level of synergy required between PIC design and fabrication on the one hand,and system architectural design and construction on the other,the barrier to demonstrating a commercially relevant and viable large-scale PIC technology has been extraordinarily high.

III.P HOTONIC I NTEGRATED C IRCUIT A RCHITECTURE AND F ABRICATION

A.DWDM Transmitter PIC Architecture

In the “Digital Optical Network,”the transmitter (TX)LS-PIC is responsible for electrical to optical conversion,while the paired receiver (RX)PIC is used for complementary optical to electrical conversion.This architecture features a 100Gb/s

(10

channels

10Gb/s)LS-PIC DWDM transmitter,with each channel operating at an aggregate data rate of 10Gb/s (line rate of 11.1Gb/s with forward error correction (FEC)overhead)on a 200-GHz International Telecommunication Union (ITU)wavelength grid in the C-band.A schematic of the TX LS-PIC is shown in Fig.1.In simplest terms,the optical signals in each of the ten monolithic channels originate in an active section,and are multiplexed into a single output channel in a monolithically integrated passive region.The active train of each monolithically integrated channel includes a tunable EML —a tunable DFB laser integrated with an EAM operating at a data rate of 10Gb/s.The EMLs are individually controlled with DC bias on the DFBs,and 10Gb/s input on the EAMs.The wavelength is chirped across the monolithically integrated DFB array to yield ten distinct and highly controllable wavelengths that can each be ?ne-tuned to the ITU grid individually at the channel level.A photodiode is monolithically integrated into the back of each channel,to provide optical power monitoring (OPM)of the DFB over the lifetime of the chip.Control of the output power pro ?le across all channels is enabled with a monolithically integrated variable optical attenuator (VOA),essentially an absorber in the active train light path of

each

Fig.1.Schematic of the architecture of the ten-channel LS-PIC transmitter chip.The transmitter PIC incorporates over 50functions monolithically integrated on a single chip.

channel.Multiplexing the ten wavelengths into a single output channel is accomplished with an AWG router monolithically integrated in the passive section of the chip.The single output channel is terminated in a spot size converter for optimized ?ber coupling.AWGs are ideally suited for LS-PICs,given their integrability in InP,high channel count and low insertion loss characteristics.This chip represents the ?rst realization of the combined functionality —10Gb/s modulated source integrated with continuous tunability,AWG frequency selective multiplexing,and power pro ?ling through the use of VOAs,all operating at performance levels required by commercial class carrier networks (as will be described in detail in subsequent sections of the paper).

B.DWDM Receiver PIC Architecture

The RX PIC is similarly con ?gured.A single input channel is routed into a spot-size converter and subsequently through a polarization independent demultiplexing AWG in the passive section of the chip.Here,the frequency selectivity of the AWG ?lter is optimized to achieve suf ?ciently low channel-to-channel crosstalk,as well as acceptably low insertion loss.PIN photo-diodes (PDs)are monolithically integrated into the waveguides at the output of the AWG.Key operating characteristics of the PD ’s include responsivity,modulation bandwidth and dark cur-rent.These RX PICs represent the ?rst demonstration of such a combination of integrated functionality and performance —high speed (10Gb/s)waveguide photodetectors integrated with a 10channel demultiplexing AWG.Further quantitative details of the operating characteristics of these RX PICs will be described in the following sections of this paper and will demonstrate the via-bility of such devices in achieving ten-channel DWDM PIC-PIC links with performance consistent with that required for deploy-ment in a carrier-class long-haul telecommunications network.C.PIC Fabrication and Packaging

The LS-PICs are fabricated using conventional,yet state-of-the-art InP processing techniques.A block diagram of the PIC fabrication ?ow is show in Fig.2.The fabrication of the PICs

Fig. 2.Process ?ow for the fabrication of photonic integrated circuits described herein.An array of 10DFBs,10EAMs,10OPMs,10VOAs,and an AWG are simultaneously monolithically integrated on a single LS-PIC transmitter chip.In addition,10PIN PDs and an AWG are simultaneously monolithically integrated on singe PIC receiver chip.

begins with the formation of the multiple epitaxial layer struc-tures required to achieve the simultaneous monolithic integra-tion of the numerous active and passive devices on the PIC chips.The epitaxial layers are grown using MOVPE in multiwafer reactors.The active elements (DFB,EAM,OPM,and VOA)of the monolithic transmitter LS-PIC consist of multiquantum well (MQW)active regions whereas the passive regions (waveg-uides and AWG)consist of bulk double heterostructure (DH)waveguides.For the Rx PIC chip,the active region of the PIN PD is a bulk DH as are the passive regions (waveguides and AWG).Conventional growth-etch-regrowth techniques (e.g.,as described in [5],[30],and [31])are utilized to monolithically in-tegrate the multiple epitaxial layers.The epitaxial reactors and growth processes require control of compositional,strain,and thickness uniformity (in-wafer,wafer-to-wafer,and run-to-run)similar to or exceeding that required for the growth of vertical cavity surface-emitting lasers [32],making the epitaxy that is employed in the fabrication of the DWDM PICs described in this paper among the mostly highly controlled of any III-V de-vice.

After the epitaxial (re)growths and front-end wafer fabrica-tion (patterning and etching)are complete,the PIC wafers are subjected to a back-end wafer fabrication process sequence.These wafer fabrication processes are similar to that used to form a heterostructure bipolar transistor (HBT)integrated circuits [33],[34],both in complexity and number of mask levels.Speci ?cally,the back-end wafer fabrication is performed to de ?ne the active/passive waveguides,form interdevice and channel –channel electrical isolation,

contact

and regions of the active devices,form DC and RF bondpads,and facili-tate passivation of the devices,The precise control of critical dimensions (e.g.,waveguides)are realized via dry-etching (using both conventional RIE and high-density plasmas).These processes result in a very high degree of control of such param-eters as waveguide width,etch depth,sidewall roughness,etc.that are required to achieve the precise control of wavelengths while simultaneously maintaining low loss of all elements

within a channel,from channel-to-channel,and between the active and passive regions.Finally,conventional metallizations and dielectric deposition techniques utilized to fabricate III-V optoelectronic devices are employed in the fabrication of the DWDM PIC devices described herein.

After the wafer fabrication steps are complete,the wafers are subjected to a die fabrication sequence wherein they are singu-lated into individual die (via cleaving)and each die is coated with an antire ?ection coating.The die are subsequently solder die-attached to a submount.Next,the resultant chip-on-carriers are subjected to a test and reliability screening/burn-in sequence to screen for performance and wavelength stability.Wavelength stability is extremely critical in a monolithic DWDM PIC to en-sure that all devices can maintain their requisite performance on the ITU grid over life.The PIC fabrication sequence is com-pleted by a rigorous ?nal test sequence that includes DC and RF testing (including the measurement of the bit-error rate (BER).Many of the fabrication speci ?cations —from epitaxy to etching —are highly demanding,even using current state-of-the-art processes.The combination of these factors underlies the long-held concern that LS-PIC manufacturing is infeasible from a yield and cost standpoint.However,we have found that through appropriate attention to process de-velopment,diligent simpli ?cation of the processes and process sequence,and application of rigorous manufacturing process controls,suf ?ciently high yields are in fact possible to realize large-scale integration with the requisite performance.This will be evidenced by the high degree of uniformity achieved within the LS-PICs reported in Sections IV and V .

Subsequent to the assembly of the DWDM PIC transceiver line cards,the monolithically integrated PIC chip-on-carriers are soldered on a thermoelectric cooler (TEC)and enclosed in a metal package.For the TX LS-PIC,one single mode ?ber is optically coupled to the output of the TX multiplexer,and a ten-channel monolithic modulator-driver ASIC array is elec-trically coupled in a hybrid fashion to the modulators.A pho-tograph and block diagram of the fully packaged TX LS-PIC is shown in Fig.3.The RX PIC packaging is similar,including a lensed ?ber coupling to the input of the RX multiplexer,and a transimpedance ampli ?er (TIA)array electrically coupled in a hybrid fashion to the PDs on the PIC.

IV .P HOTONIC I NTEGRATED C IRCUIT P ERFORMANCE A.100-Gb/s DWDM Transmitter PIC Performance

The DFBs have been optimized for high yield manufacturing and integration into the transmitter PIC.A typical light versus current/voltage (L-I-V)plot of the DFB laser array is shown with all ten channels superimposed in Fig.4.The data was taken using the per channel OPM shown in Fig.1as the detector.The lasing threshold (Ith)for all channels ranges from 20–28mA.A typical voltage at turn on is 1.2V .The devices exhibit a forward

resistance of 5.5

(

0.3)and operate in a current range of 60–80mA,typically.This bias allows the DFBs to deliver suf-?cient power per channel into the ?ber at the output of the in-tegrated transmitter chip to effectively transmit data across all long-haul links encountered in real world networks (see Sec-tion IV).

Fig.3.Photograph and schematic of the 100Gb/s DWDM LS-PIC transmitter module with the hermetic lid

removed.

Fig.4.Typical light-current-voltage (L-I-V)characteristics for the LS-PIC transmitter.The optical power is monitored via the monitor photodiode.

Narrow laser linewidth is critical for a transmission link in which an external modulator is used.A broad linewidth results in signal distortion which degrades the BER performance and optical-signal-to-noise (OSNR)in the link.A typical linewidth spectrum of a single DFB on the LS-PIC transmitter is shown in Fig.5.The linewidth was measured using a delayed self-hetero-dyne technique.The DFB is running CW at an operating current of 67mA

(

3Ith),and the light is transmitted through the en-tire LS-PIC and into the ?ber.The data ?ts well to a Lorentzian curve giving a full-width-half maximum (FWHM)linewidth of 2.3MHz.Thus,the linewidth performance of the LS-PIC trans-mitter exceeds the 10-MHz spec of most state-of-the-art com-mercial standalone DFBs [35]–[37],and the 10MHz [38]to 20MHz speci ?cation [39]of commercial EMLs.

Data is encoded for optical transmission on each channel of the LS-PIC via electro-absorption modulators (EAMs).The dc transfer characteristic of the modulator is key in minimizing the waveform distortion in the network.A typical transfer function for an EAM on the LS-PIC transmitter is shown in Fig.6.The modulator is capable of a dc extinction of 19dB at less than 3V reverse bias and is representative of the performance of other channels of the array.The maximum extinction as well as the extinction per volt realized in the LS-PIC is comparable to or exceeds the speci ?cation of currently sold two-element EMLs [38],

[39].

Fig.5.Linewidth spectrum of a single DFB from a LS-PIC transmitter chip under direct current (DC)operation at 20

C.

Fig.6.Power transfer function of the electrabsorption (EA)modulator on the LS-PIC transmitter.Extinction ratio and extinction per volt rival that of the best commercial two-element (single-channel)

EMLs.

Fig.7.Small signal frequency response for the EAM of a DWDM LS-PIC transmitter chip.

The small signal frequency response for a chip on carrier was measured using an Agilent 8703B Lightwave Component Ana-lyzer.The response versus frequency curves for all ten channels have been superimposed and are shown in Fig.7.The 3-dB bandwidth is better than 17GHz for the worst channel.The vari-ation in frequency response from channel-to-channel is on the order of 0.5dB and largely due to variation in error of measure-ment with probe placement.The ripple on the plots is a combi-nation of small electrical re ?ections from the PIC layout and re-?ections internal to the probe.This data indicates that the unifor-

Fig.8.Power transfer function of a VOA from the DWDM LS-PIC

transmitter.

Fig.9.Superposition of the ten-channel DFB spectrum with the AWG multiplexer transmission function for the ten-channel DWDM LS-PIC transmitter.The DFB and AWG are aligned using the per channel tuning elements with <0.1dB power loss resulting from misalignment between the AWG and DFB.

mity of the modulator capacitance and the impedance matching of the bond pad con ?guration across the array is very high.The variable optical attenuators are used to control the shape of the ten-channel output power spectrum.They are the last ele-ment in the transmitter signal chain before multiplexing the sig-nals from all channels via the AWG.This capability is critical to ?attening the transmitter power spectrum before it is launched into the ?ber as we will show in Section IV .In addition the VOAs can be used to compensate for any small differences in output power between the DFBs over their lifetime.The dc transfer function for a typical VOA element is shown in Fig.8.An at-tenuation range of 5.5dB is possible by employing between 0and 2V reverse bias.

In Fig.9,we superimpose the DFB spectrum with the AWG multiplexer transmission function.This is achieved by forward biasing the EAMs to produce an spontaneous emission source to map the AWG passbands.The center position of the AWG passband comb is tuned using the TEC in the packaged module to match the ITU grid.Each DFB is subsequently individually thermally tuned onto the ITU grid as well.The tunable DFBs are further employed to account for small frequency drifts to

maintain the frequency of each channel to

within

3GHz over life.The tuning range of the DFBs exceeds 300GHz (data not shown).Control of the relative channel spacing aperiodicity

on the 200GHz grid for the AWG passbands is better than

4Fig.10.Propagation loss measured using a series of waveguides of varying lengths for the passive waveguide structure employed in the DWDM transmitter PIC.The best ?t to the data indicates a propagation loss of 0.7dB/cm.

GHz (one sigma of a normal distribution).The loss penalty due

to misalignment of any AWG passband to the ITU grid for the transmitter is less than 0.1dB.

Another point highlighted by the data in Fig.9is the tight manufacturing tolerance needed to maintain accurate alignment of the DFB and AWG arrays to the ITU grid over life.The AWGs are low loss but require precise epitaxial control in thickness and composition as well as tight waveguide width tolerances to ensure uniform passband spectra and high yield to alignment of the center channel to the ITU grid at a pre-determined initial chip temperature.The DFB arrays must be fabricated to emit over a narrow range of initial wavelengths across all 10channels in order to allow enough margin for the tuning elements to maintain the wavelength on the ITU grid over life.This alignment implies excellent manufacturing control of the DFB grating pitch,waveguide width,coupling length,epitaxial thickness and composition during both growth and https://www.sodocs.net/doc/0410202525.html,mercial viability requires this manufacturing accuracy where per channel power leveling,absolute power output,and wavelength drift over life are essential to achieve the requisite performance for use in an optical telecommunications network.

A key element to large scale integration is low loss passive waveguides to link the individual elements in a PIC.The total power loss from straight sections of passive waveguides of dif-ferent lengths is plotted in Fig.10.A linear least-squares-?t to the data,provides a propagation loss value

of 0.7dB/cm for the integrated waveguide structure in a TX LS-PIC.This prop-agation loss value for the transmitter waveguide competes with the best wet etched rib loaded slab structures at 0.2dB/cm [40],and is superior to the more typical 1.5–2dB/cm for dry etched ridge waveguides [40]–[42].

B.100Gb/s DWDM Receiver PIC Performance

The receiver PIC consists of a wavelength demultiplexer monolithically integrated with an array of high speed pho-todetectors (PD).The demultiplexer is an AWG and the PDs are each a waveguide PIN diode.Like the transmitter PIC the channel spacing is 200GHz in the receiver.There are several reports of AWG/PIN integrated receiver chips in the literature;

Fig.11.Normalized photoresponse of the100Gb/s(10210Gb/s)DWDM receiver PIC.

a ten-channel device operating at2.5Gb/s per channel[43]has been reported,and a four-channel device operating at10Gb/s per channel is also commercially available.1As far as we know, this is the?rst report of an integrated receiver optical device with ten channels operating successfully at10Gb/s per channel for an aggregate data throughput of100Gb/s.

Fig.11shows the normalized photoresponse of the receiver. In the test setup,the input to the device is from a tunable laser. The output is measured as the dc photocurrent at the PIN array. The nominal?ber coupled responsivity of the integrated device is suf?cient to effectively transmit data across all long-haul links encountered in real world networks(see Section IV)and com-pares favorably with currently available discrete combinations of commercial components.

Standalone commercial PIN receiver modules for OC-192 applications have a typical responsivity of0.8A/W(including ?ber coupling losses).2Standalone?ber coupled,Gaussian type, Silica AWG modules(?at top types have higher losses),have insertion losses between3dB(ultralow loss version)and5dB (normal version).3Silica based AWGs have larger fabrication tolerances(commensurate with the optical mode index which is less than half of that in InP)and,hence,are easier to fabricate, and have lower?ber coupling losses(similar mode index and better mode matching to glass?ber).

Unlike the transmitter PIC,the integrated receiver PIC chip needs to be polarization independent.To determine the polar-ization dependent loss(PDL)and polarization dependent wave-length shift(PDWS)of the receiver PIC,the maximum and min-imum photoresponse is measured as the polarization state of the input light is varied.Fig.12shows the nominal PDL of the re-ceiver as a function of channel number.The per-channel PDL is less than0.5dB for all ten channels with a median of0.3dB.For the single polarization spectrum shown in Fig.11,the?atness (which affects the dynamic range of the receiver)is better than 0.4dB.The median PDWS for all10channels is14GHz(the minimum value is12GHz and the maximum value is17GHz). 1ThreeFive Photonics,Argo A4D10,The Netherlands.

2JDS Uniphase,ERM568XCX,10Gb/s SONET/SDH,PIN-TIA High Gain, Optical Receiver Modules,U.S.;NEL,NLK2C1B1KC,High Speed Photodi-odes,Japan;Bookham,PT10G,10Gb/s PIN Preamp Receiver,U.K.

3NEL,AWG Multi/Demultiplexer,

Japan.Fig.12.Polarization dependent loss as a function of channel number for the 100Gb/s(10210Gb/s)DWDM receiver

PIC.

Fig.13.Propagation loss measured using a series of waveguides of varying lengths for the passive waveguide structure employed in the DWDM receiver PIC.The best?t to the data indicates a propagation loss of 0.6dB/cm.

To realize low insertion loss in the receiver PIC,it is critical to fabricate waveguides with very low propagation loss.Fig.13 shows the waveguide propagation loss measured on the receiver PIC.This is done by measuring the insertion loss of waveg-uides of multiple lengths and plotting the data as a function of propagation distance.This method gives the average insertion loss over multiple lengths of the waveguide,and also eliminates the?ber coupling loss as a source of measurement uncertainty. The average propagation loss is0.6dB/cm which is amongst the best performance reported to date for InP waveguides[41]. These waveguides were de?ned via dry etching.Dry etching is required for precise and reproducible fabrication of the AWG in InP.Since the performance of the AWG is phase sensitive,fabri-cation errors of the order of a fraction of the propagation wave-length have a deleterious effect on AWG performance[44].Dry etched InP waveguides are generally reported to have an order of magnitude higher propagation losses compared to wet etched waveguides[41].Typical propagation loss reported in literature for dry etched InP waveguides is1.5–2dB/cm[40]–[42].

The adjacent channel crosstalk is lower than25dB for all ten channels with the median value of26dB.This accounts for adjacent channel crosstalk variation over all polarization states(including the effects of both PDL and PDWS).The total crosstalk is the sum of the effects of all the adjacent channels.

Fig.14.Reverse bias dark current of the high-speed PIN photodiode array at 40C and 05-V bias voltage as a function of channel number for the DWDM receiver

PIC.

Fig.15.Electrical modulation bandwidth for all ten channels of the high-speed photodiode array in the DWDM receiver PIC as a function of reverse bias voltage.

The worst case total crosstalk is better than 20dB with a me-dian value of 21.3dB.

The high-speed PIN diodes were also designed to have very low dark current.Fig.14shows the dark current measured at 5-V reverse bias and 40C across all 10channels.The dark currents are all nominally under 10nA.This is comparable to the performance of commercial high speed PIN photodiodes for 10Gb/s applications .The 40C higher temperature screen is used to ensure that the device will be robust in the ?eld and allows for the temperature tuning of the AWG up to 40C to allow for variations in the AWG center frequency resulting from manufacturing deviations encountered in PIC fabrication.

Fig.15shows the small signal bandwidth of the ten-channel high-speed PIN array as a function of bias voltage.The band-width was measured using an Agilent 8703B Lightwave Com-ponent Analyzer.The small signal bandwidth is about 18GHz at a reverse bias of 5V .The channel to channel variation in bandwidth is very small,well within the measurement error of the instrument,attesting to the fabrication uniformity of the PD array.Across all ten channels,the median parasitic capacitance is 200fF and median series resistance is

15.Even at reverse bias voltages as low as 1V ,the bandwidth is about 14GHz,and is suf ?cient for 10Gb/s operation.The performance shows that we have not sacri ?ced bandwidth for responsivity which is

a common tradeoff in many commercial high-speed photode-tector designs.

V .S YSTEM P ERFORMANCE U TILIZING DWDM P HOTONIC

I NTEGRATED C IRCUITS A.Module and Back-To-Back Performance

The transmitter and receiver PICs were built into DWDM transceiver line cards for implementation in an optical transport system.The features of the transmitter and receiver PIC were optimized to ensure good overall system level performance,including link margin to cover spans with

loss 30dB in a network as well as suf ?cient controls and reliability to maintain performance over 20years of life.The ten-channel LS-PIC DWDM transceiver cards result in over a 30-times reduction in the number of ?ber-couplings compared to a conventional system comprised of discrete optical components.The drastic reduction in ?ber connections results in a drastic reduction in packaging and system hardware costs as well as reliability issues associated with the many ?ber couplings in traditional systems.Furthermore,the space occupied by a system based on DWDM LS-PIC ’s

is 3times less than that of a conventional optical transport system,conserving valuable ?oor space in the central of ?ce.

Although integrated transmitters and receivers have been demonstrated previously,there are a several reasons,in addition to the many obvious advantages of integration,why the current design is uniquely suited for real world deployment.First,there is the use of an EAM to encode the data.Also,the use of an AWG (its frequency discrimination properties)together with an EML,which can provide concurrent modi ?cation of the output power and chirp characteristics of the transmitter PIC.Second,there is the use of on-PIC VOAs to enable output power ?attening.Third,the use of an AWG wavelength com-biner with a DFB array requires an array of integrated tuning elements to keep the DFB array aligned to the AWG.The tuning elements deployed here also are used to compensate for the small errors in the stringent manufacturing tolerances of the transmitter PIC.Fourth,the on-PIC VOA also compensates for over life power degradation of all elements on the PIC.Finally,the integrated back facet OPM provides an independent DFB power monitor over life.No other PIC reported to date has demonstrated the level of integration of the ten-channel DWDM LS-PIC transmitter reported herein while maintaining suf ?cient performance and reliability required for deployment in a carrier-class telecommunications network.

Similarly,for the 100-Gb/s DWDM receiver PIC,the fabri-cation of a ten-channel high-speed photodetector array and po-larization insensitive AWG meeting all the performance spec-i ?cations related to crosstalk,responsivity,dark current,dy-namic range,and polarization independence simultaneously is extremely challenging,but achievable.

There are several advantages achieved in the integration of the electroptic elements in a DWDM TX LS-PIC.The ?rst advan-tage relates to the integrated EAMs.During EAM fabrication,its operating wavelength can be uniquely matched to the op-erating wavelength of the DFB for optimum performance.The second advantage is that the EAM can be biased appropriately

Fig.16.Output optical spectrum from the DWDM LS-PIC transmitter module using the on-PIC VOA for power ?

attening.

Fig.17.Output optical spectrum from the DWDM LS-PIC transmitter module in Fig.16showing the on-PIC capability to customize the power spectrum.In this case,a linear grade of 0.5dB per channel is demonstrated.

to modify its chirp to suit the dispersion properties of the trans-mission ?ber [45].Conventional DWDM systems primarily de-ploy Lithium Niobate-based MZ modulators and these have a higher insertion loss,and ?xed chirp properties [46],[47].In contrast,the EAM chirp can be easily varied by appropriate dc biasing.InP MZ modulators come in two varieties.The conven-tional design operates solely based on the electro-optic effect and has ?xed chirp properties like the Lithium Niobate devices.InP MZ modulators,which use the electroabsorption effect to realize an index change,also have the bias dependent variable chirp property [48].In our system,the EAM is typically biased to provide negative chirp.Under optimized bias conditions,its modulated signal is capable of transmission over 100km of un-compensated SMF-28?ber.4

The third advantage is the availability of on-PIC power ?at-tening capability.The individual channels are spaced at 200GHz and locked to the ITU grid.At power-up,the roll-off in power in the outer channels often follows the classic roll-off in the AWG output spectrum.Fig.16shows how power ?at-tening can be achieved using the per-channel VOA integrated on the transmitter PIC.Power ?attening is critical for EDFA-based links.Fig.17shows that we can actually achieve any de-sired “shaping ”of the powers in the output spectrum.The ?gure shows a 0.5-dB/channel tilt for a total of 4.5-dB tilt across all

4Registered

trademark of Corning,Inc.

ten channels.A tilt or some variation thereof may be desired to compensate for nonlinearities in the installed ?ber base or the gain ?atness of the EDFA.

Fig.18shows the output eye diagram for all the ten channels from the DWDM LS-PIC transmitter module measured using an Agilent 86100A In ?nium Digital Communication Analyzer (DCA)with a 86109A 30-GHz optical bandwidth plug-in.The data rate is set at 11.1Gb/s to accommodate the FEC overhead for the implementation of a 10Gb/s data transmission.The eye diagrams are very uniform over all ten channels demonstrating a robust design and a high degree of control in manufacturing.The minimum extinction ratio for all ten channels shown is in excess of 13dB.The minimum 10%/90%rise time is better than 34ps and the 90%/10%fall time is better than 37ps.The maximum peak-to-peak jitter for all ten channels is less than 12ps.B.Transmission Performance

A PIC-based transport system can be con ?gured in two dif-ferent ways.The ?rst option is to regenerate the data at every network node.This also allows for all or some part of the data traf ?c to be dropped and added at will.In addition,situations exist where the traf ?c is only required to be expressed through to the next node,and there is suf ?cient OSNR margin present.Thus,the second option for transport system design is to simply insert an optical ampli ?er at the express nodes.The PIC ’s must be designed with suf ?cient performance margin to elegantly handle both options.

One of the system test setups used to characterize the line cards is shown in Fig.19.This particular con ?guration has ?ve spans of 75-km ?ber each with an EDFA [also referred to as an optical ampli ?er module (OAM)]after every span.Fig.20shows the

back-to-back measurement,i.e.,for zero disper-sion.The data is plotted as

20log()as a function of OSNR.For reference,

a value of 15.6dB is required for an uncor-rected BER of

10and 16.9dB for 10.In Fig.20,

the values for OSNR higher than about 17dB are test time limited and,hence,the curves “appear ”to rollover.This is not as the re-sult of a back-to-back noise ?oor limit.An excellent discussion on the de ?nition

of ,its practical applications,and its experi-mental determination may be found in a publication by Bergano,et al.,[49].

Many terrestrial systems for telecommunication applications these days employ an FEC scheme to reduce

the requirement for error free transport of data [50],[51].Until just a few years ago,FEC was utilized solely in high-end submarine transmis-sion systems.There are several FEC schemes that have been demonstrated to date,and most of them are proprietary.Re-cently,the ITU has approved G.975.1(02/2004)the implemen-tation of FEC in DWDM systems.Our system employs a propri-etary FEC code.Fig.21shows the link performance across ?ve spans of 75-km ?ber spools for all ten channels of the system.These measurements are useful to characterize the number of skip sites possible with a particular system con ?guration.The system sensitivity limit

is 12dB-0.1nm of OSNR.Even after ?ve spans there is signi ?cant OSNR margin in the system.The values of the individual channels tend to spread as the number of skips increases.This is a function of the residual gain ?atness

Fig.18.Ten-channel output eye diagram from the 100Gb/s DWDM LS-PIC transmitter module.Modulation is achieved via a variable chirp EAM

array.

Fig.19.Schematic of the system test bed utilized for evaluating the performance of the DWDM transceiver PIC-based line cards over multiple ?ber

spans.

Fig.20.Back-to-back Q versus OSNR performance of a DWDM PIC-based transmitter-receiver module pair on a system line card.

variation of the EDFA chain in the transmission link and not at-tributable to the PIC ’s themselves.The on-PIC VOA allows one to correct,within limits,for a large part,but not all,of the im-perfections in gain ?atness of an EDFA chain.The demonstrated uniformity in transmission performance over ?ve ?ber segments is only possible with a very tight control of the chirp and other modulation properties of the EAM.This,is turn,is enabled by precise controls realized during PIC fabrication.

This is the ?rst-ever demonstration of a transmission system to carrier level speci ?cations based on transmitter and receiver multichannel photonic integrated

circuits.

Fig.21.OSNR as a function of number of 75-km ?ber segments in an ampli ?ed system utilizing DWDM PIC-transceiver line cards at the terminals of the link.

VI.S CALING OF P HOTONIC I NTEGRATED C IRCUITS

The development of the ?rst transistor [52]marked the begin-ning of the semiconductor electronics revolution.A little over a decade later,the integrated circuit (IC)was invented [53],[54].During this time,the commercial scaling of the IC proceeded at a staggering pace,advancing from a discrete device circa 1949[55]

to 50components/chip in 1965[1]

to 42000000tran-sistors/chip for a Pentium 4device in 2000[56].This progres-sion was predicted by Moore [1]and has driven the scaling of electronic devices to be a self-ful ?lling prophecy.

The commercial development and scaling of optoelectronic devices and photonic integrated circuits in the telecommuni-cations network has occurred at a substantially slower rate.The ?rst semiconductor-based light-emitting diode (LED)transmitters were reported in 1960[57],[66]followed shortly thereafter by the demonstration of the ?rst semiconductor lasers [58]–[61].However,the ?rst telecommunications networks utilizing such devices were not deployed until 1980for LEDs [62]and 1984for lasers [63].The incubation period from de-velopment to commercial deployment was

thus 20years for optoelectronic discrete devices (compared

to 10years for the transistor).The scaling of photonic integrated circuits versus time in the telecommunication network is shown in Fig.22for the most advanced PIC technology (transmitter devices).The ?rst commercial deployment of a semiconductor transmitter occurred in 1980(LED-based),followed by the deployment of networks utilizing DMLs [63].For over the next 10years,

Fig.22.Progression of scaling of the number of functions/chip for InP-based transmitter chips utilized in commercial telecommunications networks.The 100Gb/s DWDM transmitter PIC ’s described in this work represent over an order magnitude increase in scale compared to existing commercial devices.

commercial implementations focused on incrementally higher data rates in discrete devices.The ?rst integrated device,the EML,consisting of two functions on a single chip,was ?rst de-ployed in 1996at 2.5Gb/s and in 1998at 10Gb/s in long-haul terrestrial networks [64].This was followed by the integration of two additional functions (tuning and ampli ?cation),resulting in a transmitter consisting of a tunable EML with an SOA [13]which was ?rst deployed in a telecommunications network in 2003.

The scaling of the PIC has thus been substantially slower than the corresponding electronic IC,requiring 24years to scale by 4times (the corresponding scaling for electronic ICs

was 5,000times in the same period [56]).The most important contribu-tors to the retardation in the scaling rate of PICs have been the immaturity of the existing network infrastructure and the in-ability for the cost of the integration to be recouped in value de-livered by the integrated device.The optimal integration level was highlighted by both Moore [1]and Noyce [65]to be a balance of increased chip cost per function (which increases for increased scaling)and reduced assembly cost per function (which decreases with increased scaling).The resultant value of the device depends on the network architecture and implemen-tation.To date,the increased chip cost (due to immaturity of the III-V optoelectronic device and process technology)and the value derived in the network have been insuf ?cient to drive PIC scaling at a rate consistent with Moore ’s Law.The large-scale ten-channel DWDM transmitter PICs reported in this work re-sults in an in ?ection point in this progression,scaling by over an order of magnitude

to 50functions/chip.This PIC scaling is driven by dramatic improvements in III-V device and process technology as well as the ability for such devices to enable new network architectures (wherein OEO regeneration and add –drop functionality are pervasive in the network).

The scaling of the data capacity per chip for transmitter de-vices employed in the telecommunications network is shown in Fig.23.Unlike the PIC scaling shown in Fig.22,the scaling of the data rate per chip is exponential and shows a doubling

every 2.2years,which

is 65%of the rate of progression of Moore ’s Law.The large-scale ten-channel transmitter PIC

re-

Fig.23.Scaling of the data capacity/chip for InP-based transmitter chips utilized in commercial telecommunications networks.Over the last 25years,the data capacity per chip has doubled an average of every 2.2years.The 100Gb/s DWDM transmitter PIC ’s described in this work represent an order of magnitude increase in data capacity per chip compared to existing commercial devices.

ported in this work represents an order of magnitude improve-ment in data capacity per chip compared to existing commercial devices.The transition in scaling of data rate from discrete de-vices (solid symbols)to integrated devices (open symbols)has been driven by the presence of performance impairments in the network that arise at higher bit rates making discrete scaling less cost effective than that of integrated devices.In order to continue the progression of data capacity per chip at its historical rate,further improvements in PIC scaling will be required.Thus,the rates of the scaling of functions per chip (Fig.22)and data ca-pacity per chip (Fig.23)are expected to become more closely related over time.

VII.C ONCLUSION

Large-scale photonic integrated circuits with performance and capability suf ?cient for commercial deployment have been demonstrated.These devices represent an order of magnitude or more improvement in number of functions per chip and data capacity per chip compared to previous generation devices,

using 50functions to provide a chip operating at an aggregate data rate of 100Gb/s.Further,we have shown the ?rst use of such PICs in a complete optical transport system operating across a representative DWDM long-haul network link.The use of such LS-PICs will enable signi ?cant reductions in the cost of optical transport systems,while also enabling new simpli ?ed network architectures that make maximum use of the ability to implement low-cost OEO conversions more frequently in the https://www.sodocs.net/doc/0410202525.html,pared to existing DWDM systems,such “Digital Optical Network ”architectures offer the promise to enable simpli ?ed add/drop,easier optical network engineering,auto-mated end-end circuit provisioning,and reduced operational dif ?culties in such areas as system deployment and turn-up,performance monitoring and trouble-shooting.

A CKNOWLEDGMENT

The authors are indebted to the many contributions of their colleagues at In ?nera Corporation,without whom this work would not have been possible.

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1962.

Radhakrishnan Nagarajan(S’85–M’92–SM’97)

received the B.Eng.degree(?rst class honors)in

electrical engineering from the National University

of Singapore,Singapore,in1986,the M.Eng.degree

in electronic engineering from the University of

Tokyo,Tokyo,Japan,in1989,and a Ph.D.in elec-

trical engineering from the University of California,

Santa Barbara,in1992.

Upon?nishing his Ph.D.,he was a Member of

the Research Faculty at the University of California,

Santa Barbara.In1995,he joined SDL,Inc.San Jose,CA,where,among other things,he managed the development of the new generation980-nm pump https://www.sodocs.net/doc/0410202525.html,ter,as a Senior Manager with the Advanced Technology Group at JDS Uniphase,San Jose,CA,he was working on next-generation high-speed optical components.In2001,he joined In?nera Corporation,Sunnyvale,CA,where he is currently the Director of Advanced Development for integrated optical components.He has authored/co-authored over100publications in journals and conferences,and three book chapters mainly in the area of high-speed optical components.

Dr.Nagarajan won the Photonics Circle of Excellence Award in

2000.

Charles H.Joyner(M’01)was born in Decatur,GA,

in1953.He received the B.S.degree in chemistry

from Furman University,Greenville SC,in1975,and

the M.S.and Ph.D.degrees in physical chemistry

from Harvard University,Cambridge MA,in1978

and1981,respectively.

In1981,he joined AT&T Bell Laboratories,

Holmdel,NJ,as a Member of Technical Staff.

In August2000,he was promoted to Technical

Manager in charge of semiconductor photonics for

Lucent Bell Laboratories.In July2001,he joined In?nera Corporation,Sunnyvale,CA,as Director of Device Development.He has authored or coauthored more than100papers,received30patents,and is a coauthor of Optical Telecommunications III(San Diego,CA:Academic, 1997).His career work has centered on design and fabrication of InP based integrated photonic devices for telecommunications.

Dr.Joyner is a Fellow of the Optical Society of

America.

Richard P.Schneider,Jr.was born in Akron,OH,in

1962.He received the B.S.degree in physical met-

allurgy from Washington State University,Pullman,

W A,in1984,and the Ph.D.degree in materials sci-

ence and engineering from Northwestern University,

Evanston,IL,in1989.

From1989to1995,he was a Senior Member

of the Technical Staff at Sandia National Labo-

ratories,Albuquerque,NM,where he worked on

vertical-cavity surface-emitting laser(VCSEL)tech-

nology,including the?rst AlGaInP-based visible VCSELs,development of metalorganic vapor phase epitaxy(MOVPE)for VCSEL production,and demonstration of high-ef?ciency VCSELs using oxide con?nement.In1995,he joined Hewlett-Packard Laboratories(later Agilent Laboratories),Palo Alto,CA,where he contributed to VCSEL de-vice development and transfer to the manufacturing https://www.sodocs.net/doc/0410202525.html,ter,he was responsible for developing epitaxy processes for GaN-based visible LED’s and continuous wave(CW)violet laser diodes.He then managed the Advanced GaN Optoelectronics R&D Group.In2000,he moved to the Fiber Optics Division,Agilent,and managed VCSEL epitaxy and device manufacturing and R&D teams.In2001,he joined In?nera Corporation,Sunnyvale,CA,where he led the effort to develop epitaxial materials processes for In?nera’s photonic integrated circuits(PICs).He currently manages epitaxial materials technology and integration engineering manufacturing and development activities.He has been an Associate Editor for the Journal of Electronic Materials since1999. He has authored or coauthored more than70refereed journal articles and two book chapters,and is named on20patents.

Dr.Schneider is a member of the Optical Society of America.

Jeffrey S.Bostak(M’83)was born in Ft.Belvoir,

V A,in1963.He received the B.S.degree in electrical

engineering from the University of Virginia,Char-

lottesville,in1985,and the M.S.and Ph.D.degrees

in electrical engineering from Stanford University,

Stanford,CA,in1987and1994,respectively.

From1985to1990,he was a Member of Tech-

nical Staff with AT&T Bell Laboratories,Holmdel,

NJ,where initially he was a Digital Circuit Board De-

signer for satellite earth station telemetry,and later

a lead digital circuit designer for900-MHz cordless

telephones.From1994to2001,he was a Design Center Manager with Vitesse

Semiconductor Corporation,Santa Clara,CA,where he designed integrated cir-

cuits for high-speed optical communication.Since2001,he has been with In-

?nera Corporation,Sunnyvale,CA,as a Member of Technical Staff and Man-

ager of an integrated circuits design team in the area of high-speed optical com-

munication.

Dr.Bostak was a recipient of AT&T Bell Laboratories,United States Joint

Services Electronics Program,and National Defense Science and Engineering

Graduate fellowships while at Stanford University.He is a member of the Op-

tical Society of America.

Timothy Butrie,photograph and biography not available at the time of publi-

cation.

Andrew G.Dentai(M’74–SM’85–F’93)received

the B.S.degree from the University of Veszprem,

Veszprem,Hungary,in1966,and the M.S.and Ph.D.

degrees in ceramic science from Rutgers University,

New Brunswick,NJ,in1972and1974,respectively.

In1968,he joined Bell Laboratories,Murray Hill,

NJ.After receiving the Ph.D.degree,he rejoined Bell

Laboratories in1974,where he worked on epitaxial

crystal growth until2001.He is currently a Member

of Technical Staff at In?nera Corporation,Sunnyvale,

CA.He has over300publications and talks,and28

patents spanning31years at Bell Labsoratories.

Dr.Dentai was named a Distinguished Member of Technical Staff of Bell

Laboratories in1987.

Vincent G.Dominic,photograph and biography not available at the time of

publication.

Peter W.Evans was born in St.Louis,MO,on April

4,1972.He received the B.S.,M.S.,and Ph.D.de-

grees all in electrical engineering from the University

of Illinois,Urbana-Champaign,in1994,1996,and

1998,respectively.His Ph.D.degree was supported

by a National Science Foundation Fellowship where

he co-invented the buried tunnel-contact VCSEL.

He was a Process Development Engineer with the

Fiber-Optic Components Division,Hewlett-Packard,

Palo Alto,CA,until1999.Subsequently,he worked

at Genoa Corporation,Fremont,CA,until2002,as

an Epi Engineer,VCSEL Design Engineer,and?nally an Epi Manufacturing

Manager.In2002,he joined In?nera Corporation,Sunnyvale,CA,as a Wafer

Fab Engineer.He is currently a Device and Process Integration

Engineer.

Masaki Kato received the B.S.,M.S.,and Ph.D de-

grees in electronic engineering from the University

of Tokyo,Tokyo,Japan,in1994,1996,and1999,re-

spectively.

In1999,he joined the Department of Electrical

Engineering,University of Tokyo,as a Research

Associate,where he studied semiconductor optical

devices and their application for wavelength con-

version/all-optical switching.In2002,he became a

Member of Technical Staff with In?nera Corpora-

tion,Sunnyvale,CA.Here,he has been engaged in

the development of photonic integrated circuits.

Dr.Kato is a member of Japanese Society of Applied Physics.

Mike Kauffman,photograph and biography not available at the time of publi-

cation.

Damien https://www.sodocs.net/doc/0410202525.html,mbert,photograph and biography not available at the time of

publication.

Sheila K.Mathis,photograph and biography not available at the time of publi-

cation.

Atul Mathur,photograph and biography not available at the time of publica-

tion.

Richard https://www.sodocs.net/doc/0410202525.html,es,photograph and biography not available at the time of pub-

lication.

Matthew L.Mitchell,photograph and biography not available at the time of

publication.

Mark J.Missey,photograph and biography not available at the time of publi-

cation.

Sanjeev Murthy,photograph and biography not available at the time of publi-

cation.

Alan C.Nilsson,photograph and biography not available at the time of publi-

cation.

Frank H.Peters,photograph and biography not available at the time of publi-

cation.

Stephen C.Pennypacker received the B.S.degree in

physics from Kutztown State University,Kutztown,

PA,in1988.

After graduation,he became a Process Engineer

with the Opto-Electronics Division,AT&T Mi-

croelectronics,Breiningsville,PA.He then joined

Lucent Technologies,where he became a Technical

Manager responsible for manufacturing at the Man-

ufacturing Realization Center,Breinigsville,PA.

In July2000,he joined Agility Communications,

Palo Alto,CA,as a Director of Automated Testing

Development where he led a team to establish a high-volume tunable laser

module manufacturing line.Currently,he is a Member of Technical Staff with

In?nera Corporation,Allentown,

PA.

Jacco L.Pleumeekers was born in Woerden,The

Netherlands,in1970.He received the M.Sc.and

Ph.D.degrees in electrical engineering from the

Delft University of Technology,Delft,The Nether-

lands,in1992and1997,respectively.

From1992to1996he was with France Telecom,

CNET,Lannion,France,where he performed his

Ph.D.research on numerical simulations for opto-

electronic devices.From1996to1999,he held a

post-doctoral position at the Ecole Polytechnique

Federale de Lausanne(EPFL),Lausanne,Switzer-

land,where he did theoretical and experimental research into semiconductor

optical ampli?ers.From1999to2001,he was a member of Technical Ttaff at

Lucent Technologies,Bell Laboratories,Holmdel,NJ,where he worked in the

?eld of all-optical signal processing with integrated optoelectronic devices.In

2001,he joined In?nera Corporation,Sunnyvale,CA,where he is engaged in

research and manufacturing of advanced photonic integrated circuits.He has

(co)authored more than50papers and conference

contributions.

Randal A.Salvatore(S’91–M’96)received the

B.S.E.degree(summa cum laude)from the Uni-

versity of Michigan,Ann Arbor,in1990,and the

M.S.and Ph.D.degrees from the California Institute

of Technology,Pasadena,in1991and1996,all in

electrical engineering.

From1991to1995,he studied femtosecond and

high-repetition-rate sources and demonstrated the

?rst adjustable chirp,passively modelocked semi-

conductor laser.From1996to1997,he was a Visiting

Researcher with the University of California,Santa

Barbara,where he studied noise properties in semiconductor lasers and on

wavelength conversion.In1997,he joined Lasertron Inc.,Bedford,MA,where

he was a Principal Engineer working on high-power pump lasers,DFB lasers,

and modulators.Since2002,he has been with In?nera Corporation,Sunnyvale,

CA.He has authored over25journal papers and conference presentations and

has six patents.

Dr.Salvatore is a member of the Optical Society of America,Phi Beta Kappa,

and Tau Beta

Pi.

Rory K.Schlenker was born in Reading,PA,in

1966.He received the B.S.degree in mechanical

engineering from The Pennsylvania State University,

State College,PA,in1989.

He started his career in optoelectronics as a

Process Engineer with AT&T Microelectronics,

Breiningsville,PA.While with Lucent Technologies,

Holmdel,NJ,he became a Technical Manager

responsible for developing world class automated

process platforms for manufacturing optical com-

ponents.He joined Agility Communications,Palo

Alto,in July2000as a Director of Automated Process Platform Development,

where he led a team to establish a high volume tunable laser module assembly

line.Currently,he is a Member of Technical Staff with In?nera Corporation,

Allentown,PA.He holds?ve patents related to optoelectronic product design

and manufacturing.

Robert B.Taylor,photograph and biography not available at the time of pub-

lication.

Huan-Shang Tsai received the B.S.degree in me-

chanical engineering from National Taiwan Univer-

sity,Taipei,Taiwan,R.O.C.,in1990,and the Ph.D.

degree in electrical and computer engineering from

the University of California,Santa Barbara,in1995.

He joined the High Speed Electronics Research

Department,Lucent Bell Laboratories,Holmdel,

NJ,in1996where he was working on circuits for

wireless and?ber optic applications.In2001,he

joined In?nera Corporation,Sunnyvale,CA,as a

member of Technical Staff.His current research

interests include high-speed circuits for optical communication.

Michael F.Van Leeuwen,photograph and biography not available at the time

of

publication.

Jonas Webjorn received the the M.Sc.in engi-

neering physics and the Ph.D.degree in optics from

The Royal Institute of Technology,Stockholm,

Sweden,in1987and1993,respectively.

He is currently a Member of the Technical Staff

with the Module Engineering Department,In?nera

Corporation,Sunnyvale,CA,where hs is working

on package design and manufacturing processes.His

previous positions included Director of Photonics

Development with LightLogic,Inc.,Fremont,CA;

Research Engineer with SDL,Inc.,San Jose,CA;

and Research Fellow with the Optoelectronics Research Centre,Southampton,

U.K.He has been granted?ve U.S.patents,with another seven pending.He has

authored over25journal publications and over25conference papers,several

of which were invited.

Dr.Webjorn is a member of the Optical Society of America.

Mehrdad Ziari,photograph and biography not available at the time of publi-

cation.

Drew Perkins received the B.S.degree in electrical

engineering,computer engineering,and mathematics

from Carnegie Mellon University,Pittsburgh,PA in

1986.

He is currently Chief Technology Of?cer(CTO)

with In?nera Corporation,Sunnyvale,CA.He has

previously been the CTO of OnFiber Commu-

nications,Cupertino,CA;CIENA Corporation,

Linthicum,MD;and Lightera Networks,Cupertino.

Mr.Perkins is a member of the Association

for Computing Machinery,the Optical Society of

America,and the International Society for Optical

Engineers.

Jagdeep Singh received the B.S.degree in computer

science from the University of Maryland,College

Park,in1986,the M.B.A.degree from the University

of California,Berkeley,in1990,and the M.S.degree

in computer science from Stanford University,

Stanford,CA,in1996.

He currently serves as CEO of In?nera Corpora-

tion,Sunnyvale,CA,which he cofounded in2001.

He was previously President of the Core Switching

Division,Ciena Corporation,Linthicum,MD,which

he joined after its acquisition of Lightera Networks,

Cupertino,CA.At Lightera,which he cofounded in1998,he served as CEO and

led the team that developed the CoreDirector transport switch.Prior to Lightera,

he was Vice-President of Technology Strategy at Shiva Corporation,Boston,

MA,and,prior to that,was founder and CEO of AirSoft Inc.,Cupertino.

Stephen G.Grubb ,photograph and biography not available at the time of pub-

lication.

Michael S.Ref ?e received the B.S.degree in elec-trical engineering from Drexel University,Philadel-phia,PA,in 1989,and the M.S.degree in engineering management from the University of Dayton,Dayton,OH,in 1996.

He was previously a Member of Technical Staff,Technical Manager,and Senior Manager with Lucent Technologies,Holmdel,NJ,where he had responsibility over all manufacturing operations at the company ’s Manufacturing Realization Center (MRC),Breinigsville,PA.He also served as Vice

President and General Manager at Agility Communications,Palo Alto,CA,where he had responsibility for package assembly and test process develop-ment,manufacturing and procurement.Currently,he is the General Manager of In ?nera Corporation ’s Allentown,PA,facility,where he oversees package design,process development,and manufacturing.

Mr.Ref ?e is a member of the International Microelectronics and Packaging

Society.

David G.Mehuys (M ’87)received the B.A.Sc.de-gree in engineering science from the University of Toronto,Toronto,ON,Canada,in 1984,and the M.S.and Ph.D.degrees in electrical engineering from the California Institute of Technology,Pasadena CA,in 1985and 1989,respectively.

He is currently Vice President of Module Engi-neering at In ?nera,Corporation,Sunnyvale,CA.Prior to joining In ?nera in 2002,he was with JDS Uniphase and SDL Inc.,San Jose CA,for a total of 13years,where he commercialized innova-tive,high-power tunable semiconductor lasers and subsystems,including erbium-doped ?ber ampli ?ers and Raman pump

lasers.

Fred A.Kish (M ’93–SM ’01)received the B.S.,M.S.,and Ph.D.degrees in electrical engineering form the University of Illinois,Urbana-Champaign,in 1988,1989,and 1992,respectively.

He currently serves as Vice-President of PIC De-velopment and Manufacturing with In ?nera Corpora-tion,Sunnyvale,CA.Previously,he held the position of R&D and Manufacturing Department Manager for Agilent Technologies,San Jose,CA,where he man-aged the III-V optoelectronic component organiza-tion for Agilent ’s ?ber-optics business.He also held

several positions in Senior Management at Agilent/Hewlett-Packard,where he was responsible for the development of visible light emitter technology and was one of the core inventors of transparent-substrate AlInGaP light-emitting diodes.He has co-authored over 50peer-reviewed publications and over 30patents in the area of III-V optoelectronic devices.

Dr.Kish received the Optical Society of America Adolph Lomb Award in 1996,the International Symposium on Compound Semiconductors Young Sci-entist Award in 1997,the IEEE LEOS Engineering Achievement Award in 1999,and the IEEE David Sarnoff Award in

2004.

David F.Welch (M ’81–SM ’90)received the B.S.degree in electrical engineering from the University of Delaware,Newark,1981,and the Ph.D.degree in electrical engineering from Cornell University,Ithaca,NY ,in 1984.

In 2001,he founded In ?nera Corporation,Sunny-vale,CA,an optical networking company and is cur-rently its Chief Development Of ?cer.Previously,he was Chief Technology Of ?cer and Vice President of Corporate Development of SDL and JDS Uniphase,San Jose,CA,where he was responsible for the tech-nology and acquisition strategies that culminated in the $41billion acquisition of SDL by JDS Uniphase.

Dr.Welch was the recipient of the Optical Society of America (OSA)Adolph Lomb Award in 1992and the OSA Fraunhofer Award in 1999.He is a Fellow of the OSA.

宗教与文化的关系

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