计算机组成原理课程设计报告
题目:设计一台嵌入式CISC模型机院系:计算机科学与工程学院
专业:网络工程
姓名:麦健豪
学号:1100380215
一、课程设计的题目和内容
采用定长CPU周期、联合控制方式,并运行能完成一定功能的机器语言源程序进行验证,机器语言源程序功能如下:
输入5个有符号整数(8位二进制补码表示),求最大负数的绝对值并输出显示。
说明:
①5个有符号数从外部输入;
②一定要使用符号标志位(比如说SF),并且要使用为负的时候转移(比如JS)或不为负的时候转移(比如JNS)指令;
③采用单数据总线结构的运算器。
二、系统设计
2.1系统的总体设计
2.2设计控制器的逻辑结构框图
说明:
在T4内形成微指令的微地址,并访问控制存储器,在T2的上边沿到来时,将读出的微指令打入微指令寄存器,即图中的微命令寄存器和微地址寄存器。
2.3设计机器指令和指令系统
指令对象功能机器指令
Mov1 XX,RD
DA TA->RD 0011
DA TA
TEST XX,RD AC锁存FS 0100
ADDR->PC 0101
JNS XXXX
ADDR
INC XX,RD RD+1->RD 0110
IN XX,RD SW->RD 0111
CMP RS,RD RS-RD锁存FS 1001
MOV2 RS,RD RS->RD 1010
JMP XXXX
ADDR->PC 1011
ADDR
NEG XX,RD (0-RD)->RD 1100
OUT RS,XX RS->LED 1101
以下是对Rs,Rd的规定:
Rs或Rd 选定的寄存器
0 0 R0
0 1 R1
1 0 R2
模型机规定数据的表示采用定点整数补码表示,单字长为8位,其格式如下:
7 6 5 4 3 2 1 0
符号位尾数
2.4设计时序产生器
2.5设计微程序流程图
2.6设计操作控制器单元
(1)设计微指令格式与微指令代码表
CISC 模型机系统使用的微指令采用全水平型微指令,字长为25位,其中微命令字段为17位,P 字段为2位,后继微地址为6位,其格式如下:
设计的具体指令为:
16
进制
微地址
L O A D L D P C L D A R L D I R L D R i R D _B R B _B S 1 S 0 A L U _B L D A C L D D R W R C S S W _B L E D _B
L D F R
P 1 P 2 后继微地址 00 000000 1110011001001111000 000010 02
000010
1001011001001011010
000000
03 000011 1110011001001111000 001110
04 000100 1000001001101111000 001111
05 000101 1110011001001111001 100000
06 000110 1000001001101111000 010010
07 000111 1000111001001101000 000000
09 001001 1000010001101111000 010101
0A 001010 1000110001001111000 000000
0B 001011 1110011001001111000 011000
0C 001100 1000001001101111000 011001
000000
0D 001101 100001000100011000
0E 001110 1000111001001011000 000000
0F 001111 1000011011001111100 000000
12 010010 1000111100001111000 000000
15 010101 1000001001011111000 010110
16 010110 1000011001001111100 000000
000000
18 011000 010001100100101100
19 011001 1000111110001111000 000000
30 110000 1000011001001111000 000000
000000
20 100000 010001100100101100
(2)设计地址转移逻辑电路
地址转移逻辑电路是根据微程序流程图的棱形框部分及多个分支微地址,利用微地址寄存器的异步置‘1’端,实现微地址的多路转移的。由于是采用逻辑电路来实现的,故称之为地址转移逻辑电路。在微地址流程图中,P(1)(高电平有效)测试时,根据指令的操作I7~I4强制修改后继地址的低四位;在P(2)(高电平有效)时,根据借位标志FS进行2路分支,并且都在T4内形成后继微指令的微地址。
SE5=((NOT FS) AND P(2) AND T4 SE4=(I7 AND P(2) AND T4 SE3=(I6 AND P(2) AND T4 SE2=(I5 AND P(2) AND T4 SE1=(I4 AND P(2) AND T4
2.7设计单元顶层电路
2.8编写汇编语言源程序
算法:R0存入一个整数-4,作为五次输入循环使用;R1用于存储输入的整数;R3用于存入最后的结果,并预存一个最小负数-128.随后如下 2.9 机器语言源程序
Mov1 R0,-5 将立即数-4->R0 MOV1 R2,-128 将立即数-128 ->R2 L1 TEST R0 测试R0,锁存SF JNS L2 非负,即SF=0,跳转L2 INC R0 R0+1
IN R1 输入一个整数,并存入R1 TEST R1 测试R1 JNS L1 非负则跳转L1
CMP R2,R1 比较R2,R1的大小,锁存SF JNS L1 非负则跳转L1 MOV2 R1,R2 将R1的内容存入R2 JMP L1 跳转L1 L2 NEG R2 对R2求补 OUT R2
输出结果
CISC 模型机的单元电路 3.1 ALU 单元
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ALU IS PORT( A:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
指令 地址
地址16进制 机器指令
十六进制 备注
Mov1 R0,-5 00000000 00 00110000 30
00000001 01 11111011 FB MOV1 R2,-128 00000010 02 00110010 32 00000011 03 10000001 FF L1 TEST R0 00000100 04 01000000 40 JNS L2 00000101 05 01010000 50 00000110 06 00010010 11 INC R0 00000111 07 01100000 60 IN R1 00001000 08 01110001 71 TEST R1 00001001 09 01000001 41 JNS L1 00001010 0A 01010000 50
00001011 0B 00000100 04 CMP R2,R1 00001100 0C 10011001 99 JNS L1 00001101 0D 01010000 50
00001110 0E 00000100 04 MOV2 R1,R2 00001111 0F 10100110 A6 JMP L1 00010000 10 10110000 B0 00010001 11 00000100 04 L2 NEG R2 00010010 12 11000010 C2
OUT R2
00010011
13
11011000
D8
S1 S0 功能
0 0 AC-DR,锁存FS 0
1 AC 锁存FS 1 0 自加1 1
1
求补
B:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S1,S0:IN STD_LOGIC;
BCDOUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
SF:OUT STD_LOGIC
);
END ALU;
ARCHITECTURE A OF ALU IS
SIGNAL AA,BB,TEMP:STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN
PROCESS(S1,S0)
BEGIN
IF(S1='0' AND S0='0')THEN
TEMP<=A-B;
SF<=TEMP(7);
BCDOUT<=TEMP(7 DOWNTO 0);
ELSIF(S1='0' AND S0='1')THEN
TEMP<=A-0;
SF<=TEMP(7);
BCDOUT<=TEMP(7 DOWNTO 0);
ELSIF(S1='1' AND S0='0')THEN
TEMP<=A+1;
BCDOUT<=TEMP(7 DOWNTO 0);
ELSIF(S1='1' AND S0='1')THEN
TEMP<=0-A;
BCDOUT<=TEMP(7 DOWNTO 0);
END IF;
END PROCESS;
END A;
3.2寄存器单元
LDFR上升沿有效。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY LS74 IS
PORT(
LDFR:IN STD_LOGIC;
SF:IN STD_LOGIC;
FS:OUT STD_LOGIC
);
END LS74;
ARCHITECTURE A OF LS74 IS
BEGIN
PROCESS(LDFR)
BEGIN
IF(LDFR'EVENT AND LDFR='1')THEN
FS<=SF;
END IF;
END PROCESS;
END A;
而暂存寄存器与通用寄存器则是使用
LS273
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY LS273 IS
PORT(
D:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLK:IN STD_LOGIC;
O:OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );
END LS273;
ARCHITECTURE A OF LS273 IS
BEGIN
PROCESS(CLK)
BEGIN
IF(CLK'EVENT AND CLK='1') THEN
O<=D;
END IF;
END PROCESS;
END A;
3.3 1:2分配器单元
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FEN2 IS 通用寄存器功能表
RO_1 R1_B R2_B ALU_B 功能
1 1 1 0 输出ALU
0 1 1 1 输出R0
1 0 1 1 输出R1 1 1 0 1 输出R2
输入输出WR LED_B X[7..0] W1[7..0] W2[7..0]
0 0 X X[7..0]
其他值X X[7..0]
PORT(
X:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
WR,LED_B:IN STD_LOGIC;
W1,W2:OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );
END FEN2;
ARCHITECTURE A OF FEN2 IS
BEGIN
PROCESS(LED_B,WR)
BEGIN
IF(LED_B='0' AND WR='0') THEN
W2<=X;
ELSE
W1<=X;
END IF;
END PROCESS;
END A;
3.4 3选1数据选择器单元
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX3 IS
PORT(
ID:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
SW_B,CS:IN STD_LOGIC;
N1,N2:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
EW:OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );
END MUX3;
ARCHITECTURE A OF MUX3 IS
BEGIN
PROCESS(SW_B,CS)
BEGIN
IF(SW_B='0') THEN
EW<=ID;
ELSIF(CS='0')THEN
EW<=N2;
ELSE
EW<=N1;
END IF;
END PROCESS;
END A;
3.5 4选1数据选择器单元
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX4 IS
PORT(
C,D,E,F: IN STD_LOGIC;
X1,X2,X3,X4: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
W: out STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END MUX4;
ARCHITECTURE A OF MUX4 IS
SIGNAL SEL: STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN
SEL<=F&E&D&C;
PROCESS(SEL)
BEGIN
IF(SEL="1110") THEN --R0_out
W<=X1;
ELSIF(SEL="1101") THEN --R1_out
W<=X2;
ELSIF(SEL="1011") THEN --R2-out
W<=X3;
ELSIF(SEL="0111") THEN --R3_out
W<=X4;
ELSE
null;
END IF;
END PROCESS;
END A;
3.6 程序计数器单元
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY PC IS
PORT(
load,LDPC,CLR: IN STD_LOGIC;
D: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
O: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END PC;
ARCHITECTURE A OF PC IS
SIGNAL QOUT: STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN
PROCESS(LDPC,CLR,load)
BEGIN
IF(CLR='0') THEN
QOUT<="00000000";
ELSIF(LDPC'EVENT AND LDPC='1') THEN
IF(load='0') THEN
QOUT<=D; --BUS->PC
ELSE
QOUT<=QOUT+1; --PC+1
END IF;
END IF;
END PROCESS;
O<=QOUT;
END A;
3.7 地址寄存器单元
同寄存器单元
3.8主存储器单元
即为ROM。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ROM16 IS
PORT(
DOUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
ADDR:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CS:IN STD_LOGIC
);
END ROM16;
ARCHITECTURE A OF ROM16 IS
BEGIN
DOUT<="00110000"WHEN ADDR="00000000"AND CS='0'ELSE "11111011"WHEN ADDR="00000001"AND CS='0'ELSE
"00110010"WHEN ADDR="00000010"AND CS='0'ELSE
"10000001"WHEN ADDR="00000011"AND CS='0'ELSE
"01000000"WHEN ADDR="00000100"AND CS='0'ELSE
"01010000"WHEN ADDR="00000101"AND CS='0'ELSE
"00010010"WHEN ADDR="00000110"AND CS='0'ELSE
"01100000"WHEN ADDR="00000111"AND CS='0'ELSE
"01110001"WHEN ADDR="00001000"AND CS='0'ELSE
"01000001"WHEN ADDR="00001001"AND CS='0'ELSE
"01010000"WHEN ADDR="00001010"AND CS='0'ELSE
"00000100"WHEN ADDR="00001011"AND CS='0'ELSE
"10011001"WHEN ADDR="00001100"AND CS='0'ELSE
"01010000"WHEN ADDR="00001101"AND CS='0'ELSE
"00000100"WHEN ADDR="00001110"AND CS='0'ELSE
"10100110"WHEN ADDR="00001111"AND CS='0'ELSE
"10110000"WHEN ADDR="00010000"AND CS='0'ELSE
"00000100"WHEN ADDR="00010001"AND CS='0'ELSE
"11000010"WHEN ADDR="00010010"AND CS='0'ELSE
"11011000"WHEN ADDR="00010011"AND CS='0'ELSE
"00000000";
END A;
3.9 指令寄存器单元
3.10 时序产生器单元
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY COUNTER IS
PORT(
Q,CLR: IN STD_LOGIC;
T2,T3,T4: OUT STD_LOGIC
);
END COUNTER;
ARCHITECTURE A OF COUNTER IS
SIGNAL X: STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN
PROCESS(Q,CLR)
BEGIN
IF(CLR='0') THEN
T2<='0';
T3<='0';
T4<='0';
X<="00";
ELSIF(Q'EVENT AND Q='1') THEN
X<=X+1;
T2<=(NOT X(1)) AND X(0);
T3<=X(1) AND (NOT X(0));
T4<=X(1) AND X(0);
END IF;
END PROCESS;
END A;
3.11 操作控制器单元
地址转移逻辑电路ADDR
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ADDR IS
PORT(
I7,I6,I5,I4:IN STD_LOGIC;
FS,T4,P1,P2:IN STD_LOGIC;
SE6,SE5,SE4,SE3,SE2,SE1:OUT STD_LOGIC );
END ADDR;
ARCHITECTURE A OF ADDR IS
BEGIN
SE6<='1';
SE5<=NOT( FS AND P2 AND T4); SE4<=NOT(I7 AND P1 AND T4); SE3<=NOT(I6 AND P1 AND T4); SE2<=NOT(I5 AND P1 AND T4); SE1<=NOT(I4 AND P1 AND T4); END A;
微地址寄存器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY MMM IS
PORT(
SE:IN STD_LOGIC;
T2:IN STD_LOGIC;
D:IN STD_LOGIC;
CLR:IN STD_LOGIC;
UA:OUT STD_LOGIC
);
END MMM;
ARCHITECTURE A OF MMM IS BEGIN
PROCESS(CLR,SE,T2)
BEGIN
IF(CLR='0') THEN
UA<='0';
ELSIF(SE='0')THEN
UA<='1';
ELSIF(T2'EVENT AND T2='1') THEN
UA<=D;
END IF;
END PROCESS;
END A;
微地址转换器F1
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY F1 IS
PORT(
UA5,UA4,UA3,UA2,UA1,UA0:IN STD_LOGIC;
D:OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
);
END F1;
ARCHITECTURE A OF F1 IS
BEGIN
D(5)<=UA5;
D(4)<=UA4;
D(3)<=UA3;
D(2)<=UA2;
D(1)<=UA1;
D(0)<=UA0;
END A;
控制存储器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CONTROM IS
PORT(ADDR: IN STD_LOGIC_VECTOR(5 DOWNTO 0);
UA:OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
D:OUT STD_LOGIC_VECTOR(18 DOWNTO 0)
);
END CONTROM;
ARCHITECTURE A OF CONTROM IS
SIGNAL DATAOUT: STD_LOGIC_VECTOR(24 DOWNTO 0);
BEGIN
PROCESS(ADDR)
BEGIN
CASE ADDR IS
WHEN "000000"=>DA TAOUT<="1110011001001111000000010";
WHEN "000010"=>DA TAOUT<="1001011001001011010000000";
WHEN "000011"=>DATAOUT<="1110011001001111000001110";
WHEN "000100"=>DA TAOUT<="1000001001101111000001111";
WHEN "000101"=>DA TAOUT<="1110011001001111001100000";
WHEN "000110"=>DATAOUT<="1000001001101111000010010";
WHEN "000111"=>DATAOUT<="1000111001001101000000000";
WHEN "001001"=>DA TAOUT<="1000010001101111000010101";
WHEN "001010"=>DA TAOUT<="1000110001001111000000000"; --0A
WHEN "001011"=>DATAOUT<="1110011001001111000011000";
WHEN "001100"=>DATAOUT<="1000001001101111000011001";
WHEN "001101"=>DATAOUT<="1000010001000110000000000";
WHEN "001110"=>DATAOUT<="1000111001001011000000000";
WHEN "001111"=>DA TAOUT<="1000011011001111100000000";
WHEN "100000"=>DA TAOUT<="0100011001001011000000000";
WHEN "010010"=>DA TAOUT<="1000111100001111000000000";
WHEN "010101"=>DA TAOUT<="1000001001011111000010110";
WHEN "010110"=>DATAOUT<="1000011001001111100000000";
--WHEN "010111"=>DATAOUT<="1000111010001111000000000"; --17
WHEN "011000"=>DATAOUT<="0100011001001011000000000";
WHEN "011001"=>DATAOUT<="1000111110001111000000000";
WHEN "110000"=>DATAOUT<="1000011001001111000000000";
WHEN OTHERS=>DA TAOUT<="1000011001001111000000000";
END CASE;
UA(5 DOWNTO 0)<=DA TAOUT(5 DOWNTO 0);
D(18 DOWNTO 0)<=DATAOUT(24 DOWNTO 6);
END PROCESS;
END A;
微命令寄存器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY MCOMMAND IS
PORT(
T2,T3,T4,I3,I2,I1,I0:IN STD_LOGIC;
O:IN STD_LOGIC_VECTOR(18 DOWNTO 0);
P1,P2,LOAD,LDPC,LDAR,LDIR,LDR0,LDR1,LDR2,R0_B,R1_B,R2_B,S1,S0,ALU_B,LDAC, LDDR,WR,CS,SW_B,LED_B,LDFR:OUT STD_LOGIC
);
END MCOMMAND;
ARCHITECTURE A OF MCOMMAND IS
SIGNAL DATAOUT:STD_LOGIC_VECTOR(18 DOWNTO 0);
BEGIN
PROCESS(T2)
BEGIN
IF(T2'EVENT AND T2='1')THEN
DATAOUT(18 DOWNTO 0)<=O(18 DOWNTO 0);
END IF;
P2<=DATAOUT(0);
P1<=DATAOUT(1);
LDFR<=DATAOUT(2) AND T4;
LED_B<=DATAOUT(3);
SW_B<=DATAOUT(4);
CS<=DATAOUT(5);
WR<=DATAOUT(6)OR(NOT T3);
LDDR<=DATAOUT(7) AND T4;
LDAC<=DATAOUT(8) AND T4;
ALU_B<=DATAOUT(9);
S0<=DATAOUT(10);
S1<=DATAOUT(11);
R2_B<=(DATAOUT(13)OR(NOT I1)OR I0)AND(DATAOUT(12)OR(NOT I3)OR I2);
R1_B<=(DATAOUT(13)OR(NOT I0)OR I1)AND(DATAOUT(12)OR(NOT I2)OR I3);
R0_B<=(DATAOUT(13)OR I1 OR I0)AND(DATAOUT(12)OR I3 OR I2);
LDR2<=T4 AND DATAOUT(14)AND I1 AND (NOT I0);
LDR1<=T4 AND DATAOUT(14)AND (NOT I1) AND I0;
LDR0<=T4 AND DATAOUT(14)AND (NOT I1) AND (NOT I0);
LDIR<=DATAOUT(15)AND T3;
LDAR<=DATAOUT(16)AND T3;
LDPC<=DATAOUT(17)AND T4;
LOAD<=DATAOUT(18);
END PROCESS;
END A;
微地址转换器F2
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY F2 IS
PORT(
D:IN STD_LOGIC_VECTOR(5 DOWNTO 0);
UA5,UA4,UA3,UA2,UA1,UA0:OUT STD_LOGIC
);
END F2;
ARCHITECTURE A OF F2 IS
BEGIN
UA5<=D(5);
UA4<=D(4);
UA3<=D(3);
UA2<=D(2);