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DATA SHEET

Product speci?cation

Supersedes data of 1997Jul 02

File under Discrete Semiconductors, SC04

1998May 18

DISCRETE SEMICONDUCTORS

PDTA114ES

PNP resistor-equipped transistor

book, halfpage

M3D186

PNP resistor-equipped transistor

PDTA114ES

FEATURES

?Built-in bias resistors

R1and R2 (typ.10k ? each)?Simplification of circuit design ?Reduces number of components and board space.APPLICATIONS

?Especially suitable for space reduction in interface and driver circuit applications

?Inverter circuit configurations without use of external resistors.DESCRIPTION

PNP resistor-equipped transistor in a TO-92; SOT54 plastic package.NPN complement: PDTC114ES.PINNING

PIN DESCRIPTION 1base/input 2collector/output 3

emitter/ground (+)

Fig.1 Simplified outline (TO-92; SOT54) and symbol.

handbook, halfpage

MAM338

123

R1R2

Fig.2

Equivalent inverter symbol.

MGL136

QUICK REFERENCE DATA SYMBOL PARAMETER

CONDITIONS

MIN.

TYP .

MAX.UNIT V CEO collector-emitter voltage open base

???50V I O output current (DC)???100mA I CM peak collector current ???100mA P tot total power dissipation T amb ≤25°C

??500mW

h FE DC current gain I C =?5mA; V CE =?5V

30??R1input resistor 71013k ?resistor ratio

0.81 1.2

R2R1

-------

PNP resistor-equipped transistor

PDTA114ES

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).Note

1.Transistor mounted on an FR4 printed-circuit board.THERMAL CHARACTERISTICS Note

1.Transistor mounted on an FR4 printed-circuit board.CHARACTERISTICS

T amb =25°C unless otherwise speci?ed.SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.UNIT

V CBO collector-base voltage open emitter ??50V V CEO collector-emitter voltage open base ??50V V EBO emitter-base voltage open collector

??10V V I

input voltage positive ?+10V negative

??40V

I O output current (DC)??100mA I CM peak collector current ??100mA P tot total power dissipation T amb ≤25°C; note 1

?500mW T stg storage temperature ?65+150°C T j junction temperature

?150°C T amb operating ambient temperature

?65

+150

°C

SYMBOL PARAMETER

CONDITIONS VALUE.UNIT R th j-a thermal resistance from junction to ambient

note 1

250

K/W

SYMBOL PARAMETER

CONDITIONS

MIN.TYP .MAX.UNIT I CBO collector cut-off current I E =0; V CB =?50V ???100nA I CEO collector cut-off current I B =0; V CE =?30V

???1μA I B =0; V CE =?30V; T j =150°C ???50μA I EBO emitter cut-off current I C =0; V EB =?5V ???400μA h FE DC current gain I C =?5mA; V CE =?5V 30??V CEsat collector-emitter saturation voltage I C =?10mA; I B =?0.5mA

???150mV V i(off)input-off voltage I C =?100μA; V CE =?5V ??1.1?0.8V V i(on)input-on voltage I C =?10mA; V CE =?0.3V

?2.5?1.8?V R1input resistor 71013k ?

resistor ratio 0.81 1.2C c

collector capacitance

I E =i e =0; V CB =?10V; f =1MHz

R2R1-------

PNP resistor-equipped transistor PDTA114ES

Fig.3

DC current gain as a function of collector current; typical values.

V CE =?5V.(1)T amb =150°C.(2)T amb =25°C.(3)T amb =?40°C.

handbook, halfpage

MBK780

?10?1

?1?10

?102

I C (mA)

h FE

103

102

1(1)

(2)

(3)

Fig.4

Collector-emitter saturation voltage as a function of collector current; typical values.

I C /I B =20.

(1)T amb =100°C.(2)T amb =25°C.(3)T amb =?40°C.

handbook, halfpage

MBK779

?10

?102

(2)(3)

(1)?10?1

?10?2

I C (mA)

V CEsat (V)

Fig.5

Input-off voltage as a function of collector current; typical values.

V CE =?5V.

(1)T amb =?40°C.(2)T amb =25°C.(3)T amb =100°C.handbook, halfpage

?10

(2)(3)

(1)?1

?10?1

MBK782

?10?2

?10?1

?10

I C (mA)

V i(off)(V)

Fig.6

Input-on voltage as a function of collector current; typical values.

V CE =?0.3V.

(1)T amb =?40°C.(2)T amb =25°C.(3)T amb =100°C.

handbook, halfpage

?102

?10

?10?1

MBK781

?10?1

?1?10

?102

I C (mA)

(1)(2)(3)

V i(on)(V)

PNP resistor-equipped transistor

PDTA114ES

PACKAGE OUTLINE

UNIT A REFERENCES

OUTLINE VERSION EUROPEAN PROJECTION

ISSUE DATE IEC

JEDEC EIAJ mm

5.25.0

b 0.480.40

c 0.450.40

D 4.84.4

d 1.71.4

E 4.23.6

L 14.512.7

e 2.54

e 11.27

L 1(1)2.5

b 10.660.56

DIMENSIONS (mm are the original dimensions)Note

1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities.

SOT54

TO-92

SC-43

97-02-28

0 2.5 5 mm

scale

b 1

L 1

E Plastic single-ended leaded (through hole) package; 3 leads

SOT54

e 1

PNP resistor-equipped transistor PDTA114ES

DEFINITIONS

Data sheet status

Objective speci?cation This data sheet contains target or goal speci?cations for product development. Preliminary speci?cation This data sheet contains preliminary data; supplementary data may be published later. Product speci?cation This data sheet contains ?nal product speci?cations.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the speci?cation is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the speci?cation.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.

PNP resistor-equipped transistor PDTA114ES

NOTES

Internet: https://www.sodocs.net/doc/0711345050.html,

Philips Semiconductors – a worldwide company

? Philips Electronics N.V. 1998

SCA60

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.

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Pakistan: see Singapore

Philippines: Philips Semiconductors Philippines Inc.,

106Valero St.Salcedo Village, P.O.Box 2108MCC,MAKATI,Metro MANILA, Tel.+6328166380,Fax.+6328173474Poland: Ul.Lukiska 10, PL 04-123WARSZAWA,Tel.+48226122831,Fax.+48226122327Portugal: see Spain Romania: see Italy

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United Kingdom: Philips Semiconductors Ltd., 276Bath Road, Hayes,MIDDLESEX UB35BX, Tel.+441817305000,Fax.+441817548421United States: 811East Arques Avenue, SUNNYVALE, CA 94088-3409,Tel.+18002347381

Uruguay: see South America Vietnam: see Singapore

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For all other countries apply to: Philips Semiconductors,

International Marketing &Sales Communications,Building BE-p, P.O.Box 218,5600MD EINDHOVEN, The Netherlands,Fax.+31402724825Argentina: see South America

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Indonesia: PT Philips Development Corporation, Semiconductors Division,Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,Tel.+62217940040ext.2501, Fax.+62217940080Ireland: Newstead, Clonskeagh, DUBLIN 14,Tel.+35317640000,Fax.+35317640200

Israel: RAPAC Electronics, 7Kehilat Saloniki St, PO Box 18053,TEL AVIV 61180, Tel.+97236450444,Fax.+97236491007Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,20124MILANO, Tel.+39267522531,Fax.+39267522557Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,

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Printed in The Netherlands

115104/1200/02/pp8 Date of release: 1998May 18Document order number: 939775003751

PDTA114ES中文资料

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