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FPGA可编程逻辑器件芯片EP2S30F484C3中文规格书

Chapter 1:Stratix III Device Family Overview

Reference and Ordering Information

Signal Integrity

Stratix III devices simplify the challenge of signal integrity through a number of chip,

package, and board level enhancements to enable efficient high-speed data transfer

into and out of the device. These enhancements include:

■8:1:1 user I/O/Gnd/V CC ratio to reduce the loop inductance in the package

■Dedicated power supply for each I/O bank, limit of I/Os is 24 to 48 I/Os per bank, to help limit simultaneous switching noise

■Programmable slew-rate support with up to four settings to match desired I/O

standard, control noise, and overshoot

■Programmable output-current drive strength support with up to six settings to

match desired I/O standard performance

■Programmable output-delay support to control rise/fall times and adjust duty

cycle, compensate for skew, and reduce simultaneous switching outputs (SSO)

noise

■Dynamic OCT with auto calibration support for series and parallel OCT and

differential OCT support for LVDS I/O standard on the left/right banks

f For more information about SI support in the Quartus II software, refer to the

Quartus II Handbook.

f For more information about how to use the various configuration, PLL, external

memory interfaces, I/O, high-speed differential I/O, power, and JTAG pins, refer to

the Stratix III Device Family Pin Connection Guidelines.

Reference and Ordering Information

The following section describes Stratix III device software support and ordering

information.

Software Support

Stratix III devices are supported by the Altera Quartus II design software, version 6.1

and later, which provides a comprehensive environment for

system-on-a-programmable-chip (SOPC) design. The Quartus II software includes

HDL and schematic design entry, compilation and logic synthesis, full simulation and

advanced timing analysis, SignalTap?II logic analyzer, and device configuration.

f For more information about the Quartus II software features, refer to the Quartus II

Handbook.

The Quartus II software supports a variety of operating systems. The specific

operating system for the Quartus II software can be obtained from the Quartus II

Readme.txt file or the Operating System Support section of the Altera website. It also

supports seamless integration with industry-leading EDA tools through the

NativeLink? interface.

Ordering Information

Figure 1–1 shows the ordering codes for Stratix III devices.

f

For more information about a specific package, refer to the Stratix III Device Package Information chapter.

Chapter Revision History

Table 1–6 lists the revision history for this chapter.

Figure 1–1.Stratix III Device Packaging Ordering Information

Number of pins for a particular package:F:FineLine BGA (FBGA)

to 85 C ) to 100 C )

484115215177801760

H:Hybrid FineLine BGA (HBGA)

Table 1–6.Chapter Revision History (Part 1 of 2)

2.Logic Array Blocks and Adaptive Logic

Modules in Stratix III Devices SIII51002-1.5

Chapter 2:Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices

Adaptive Logic Modules

Carry Chain

The carry chain provides a fast carry function between the dedicated adders in

arithmetic or shared arithmetic mode. The two-bit carry select feature in Stratix III

devices halves the propagation delay of carry chains within the ALM. Carry chains can begin in either the first ALM or the sixth ALM in an LAB. The final carry-out

signal is routed to a ALM, where it is fed to local, row, or column interconnects.

The Quartus II Compiler automatically creates carry chain logic during design

processing, or you can create it manually during design entry. Parameterized

functions such as LPM functions automatically take advantage of carry chains for the appropriate functions.

The Quartus II Compiler creates carry chains longer than 20 (10 ALMs in arithmetic or shared arithmetic mode) by linking LABs together automatically. For enhanced

fitting, a long carry chain runs vertically allowing fast horizontal connections to

TriMatrix? memory and DSP blocks. A carry chain can continue as far as a full

column.

To avoid routing congestion in one small area of the device when a high fan-in

arithmetic function is implemented, the LAB can support carry chains that only utilize either the top half or the bottom half of the LAB before connecting to the next LAB.

This leaves the other half of the ALMs in the LAB available for implementing

narrower fan-in functions in normal mode. Carry chains that use the top five ALMs in the first LAB carry into the top half of the ALMs in the next LAB within the column.

Carry chains that use the bottom five ALMs in the first LAB carry into the bottom half of the ALMs in the next LAB within the column. In every alternate LAB column, the top half can be bypassed; in the other MLAB columns, the bottom half can be

bypassed.

1For more information on carry chain interconnect, refer to “ALM Interconnects” on page2–20.

Shared Arithmetic Mode

In shared arithmetic mode, the ALM can implement a three-input add within an

ALM. In this mode, the ALM is configured with 4 four-input LUTs. Each LUT either computes the sum of three inputs or the carry of three inputs. The output of the carry computation is fed to the next adder (either to adder1 in the same ALM or to adder0 of the next ALM in the LAB) via a dedicated connection called the shared arithmetic chain. This shared arithmetic chain can significantly improve the performance of an adder tree by reducing the number of summation stages required to implement an

adder tree. Figure2–13 shows the ALM using this feature.

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