Altium公司的FPGA开发板的原理图
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Project Title Size:
Date:File:Revision:Sheet of Time:A2Sheet Title NB3000 Top Level Assy:81
NB3000AL - Altera
D-820-0053
Altium Limited
3 Minna Close Belrose NSW 2085Australia
PSU
PSU.SchDoc
SRAM
SRA M1
SRAM_256Kx 16_TSOP44
STATUS_LED
U SE R _STATUS_L E DS DB_LEDS_0603
SRAM1
SRAM2
MEM_COMMON
DAU_RESET_SW
BUZZER
ONE_WIRE_DB_PB
SW
DIP
USERIO
EXT_A
RS232
KEYBOARD
MOUSE
TFT_IO
DB_PROGRAM STATUS_LED
USER_LEDS RELAY
I2C
CODEC
VGA
ETH
DBSD
DBUSB
PWM
SPDIF
DAC
ADC
RS485
MIDI
DB_JTAG DB_CLOCKS DB_SPI
ISP176X
PROTOTYPE
SPAREIO
TFT_TSC
FPGA _USE R FPGA.SCHDOC
INT
EXT
V IDE O_OU T
VGA_OUT.SCHDOC
CON
CON_VGA
CON_VGA_DB15
HOST_JTAG
LED1LED2
1WID
DB_PROGRAM
CLK_PLL
FLASH_BOOT
HOSTUSB
SRAM
RTC
SD
HOST_AUDIO DB_JTAG DB_CLOCKS
FLASH_USER
DB_SPI
PB_A
EXTSPI FLASH_GOLDEN
DIAGCOMMS
FPGA _HOST
HOST_FPGA.SchDoc
HOST_JTAG
HOST_JTA G
HOST_JTAG.SchDoc
INT EXT
R S232
RS232_HIN232
EXT
INT
KE Y BOA RD
PC_PS2
RS232#
KBD#MSE#
RS232
KEYBOARD EXT
INT MOUSE
PC_PS2
DIPSW DB_RESET CON
CON_DBU SB
CON_MINI_USBB_RA_KME04-USBMU03A01-1
DBUSB
DBUSB#
CON
CON_DBSD
CON_SD_KSDC012551
DBSD
EXT
INT
DBU SB_TX RX
USB_CY7C68001-56LFC.SchDoc
INT
EXT
E TH
Ethernet_RTL8201CL.SchDoc
ETH
CLK_PLL
CL K_PL L
CLK_ICS307-02_PLL
1WID
NB_ID
1WB_DS2502_ID
CON CON_HOST_USB
CON_MINI_USBB_RA_KME04-USBMU03A01-1
TFT_TSC
TFT_TOUCH
L CDTFT
TSC_XPT2046.SchDoc
TFT_TSC
TFT_IO CON
CON_MOU SE
CON_PS2PORT_MINIDIN6F_BLACK
INT
CON
PDA _SW ITCHE S SW_PB_SPNOx5_SMD
INT
TE ST_RE SE T
SW_RESET_SPNO
CON
USERPOWER CON_IO
CON_USER_20WBOXHDRRAMx 2
UIO
BUZZER
CODEC_AUD
AUDIO
SPK_L
SPK_R
HOST_AUDIO
AIN AOUT_PBA
A UDIO_A MP
AUDIO_AMP_NB2C
PB_AIN AUDIO
SPK_L
USER_LEDS
CON
U SE R _L E D
LED_RGB_SMDx 8.SCHDOC
USER_LEDS VGA#
VGA
SW
SRAM
SRA M2
SRAM_256Kx 16_TSOP44
RELAYS
CON
R E L AY
RELAY_X4_IM03GR
RELAY
PWM
CON
PW M
PWM_5.8A_30V_X4
PWM
1V21V82V53V35V0
PBPOW E R
1V21V82V53V35V0
I2C DIGITAL
CODEC_AUD
AIN
A UDIO_CODE C
Audio_Codec.SchDoc
CODEC SPK_L
SPK_R CON_SPE AKE R S CON_EXT_SPK
SPK_R PB_AOUT PBIO LED1LED2
LED1_EXT LED2_EXT
L E D_HOST
LED_RGB_SMDx 2
SPDIF
CON_SPDIF
CON_SPDIF_INOUT_A
SPDIF
SPI
CON
DAC
DAC_DAC084S085_SPI
SPI
CON
A DC
ADC_ADC084S021_SPI
DAC
ADC
CON
CON_E TH
CON_ETHERNET_RJ45_LEDS
ETH#
TFT_IO
TFT_TOUCH CON_L CDTFT
CON_FFC40_LCDTFT.SCHDOC
CON
CON_RE L AY
CON_RELAYx 4_KMRJIO3_5MM_12WAY
CON
CON_RS232
CON_RS232DCE_DB9_TH
BOOT_FLASH
MOUNTS Mounts.SchDoc
INT
EXT
R S485
RS485_ISL8491
CON_PSU
PWJACK+SWITCH.SchDoc
HOST_USB
HOSTUSB#
EXT
INT
HOST_USB_TXR X
USB_CY7C68001-56LFC.SchDoc
VBATT
CON_BA TT
CON_BATT_COIN
VBATT
VBATT
RTC
R T CL OCK
CLK_PCF2123_RTC
HOST_RTC
USERPOWER
U SE R _POW E R
USERPWR.SCHDOC
CON
CON_HOST_SD
CON_SD_KSDC012551
RS485#CON
CON_RS485
CON_RS485_RJ45
INT EXT
MIDI INTE RFA CE
MIDI_FULL
CON
CON_MIDI
CON_MIDI_DIN5
MIDI#
MIDI
RS485HOST_AUDIO PBCTRL DB_PROGRAM
HOST_JTAG
HOST_ID
HOST_CLK HOST_SRAM HOST_LED1
HOST_LED2
HOST_SD
DB_SRAM1
DB_SRAM2
DB_MEM
DB_STATUS ADC#
RELAYS#
PWM#
DAC#
UIO_PWR
DB_JTAG DB_CLOCKS
PB_SPI USER_FLASH DB_SPI
EXT
ONE_WIRE_DB_PB
AIN I2C
SPI
AOUT
CTRL PBPOWER
CON_PE R IPHE R AL _BRD
PBCON
USER_LEDS SW_PDA
SPARE_IO
CON_L E DKBD
CON_NB3000_LEDKB
SERFLASH
SYSBOOT
FLASH_M25PX0_SPI_8Mbit
GOLD_FLASH
SERFLASH
GOL DE N
FLASH_M25PX0_SPI_8Mbit
FLASH
U SE R _FL A SH
FLASHSPI_M25PX0
INT
SW _DIP8_SM T
SW_DIP8_SMT
CON
CON_KE YBOAR D
CON_PS2PORT_MINIDIN6F_BLACK
CON
CON_USB1
CON_USBA_RA_UPRIGHT
LEDS#
ATE
DIAGCOMMS
A TE INTE R FACE
CON_NB3000_ATE_INTF
ISP176X PORT1
PORT2
PORT3
U SB_U SE RHOST USB_ISP1760
ATE
VGA#SPDIF UIO ADC#DAC#AUDIO HOST_JTAG PWM RS232#RS485#KBD#MSE#MIDI#
HOST_ID A TE INTE R FACE
VGA#SPDIF UIO
ADC#
DAC#
AUDIO HOST_JTAG PWM#
RS232#RS485#KBD#MSE#MOUSE
ISP176X
PORT1
PORT2
PORT3
PROTOTYPE
U SE R _PROTOTYPE _AR E A
PROTOTYPE_A
PROTOTYPE CON
CON_AU DIO
CON_AUDIO_AC99_NOMIC.SCHDOC
DIAGCOMMS
MIDI#
HOST_ID SW#
SPAREIO MEM
COMM ON_ME M OR Y
CommonMemory
CON
CON_ADC
CON_ADCx 4_KMRJIO3_5MM_6WAY
CON
CON_DAC
CON_DACx 4_KMRJIO3_5MM_6WAY
CON
CON_PW M
CON_PWMx4_KMRJIO3_5MM_6WAY
CON
CON_USB2
CON_USBA_RA_UPRIGHT
CON
CON_USB3
CON_USBA_RA_UPRIGHT
SRAM
SRA M_HOST
SRAM_256Kx 16_TSOP44
TFT_TOUCH
INT
U SB_CL K
OSC_24MHZ.SchDoc
HOST_USB.XTALIN HOST_USB.XTALOUT
CMOSOUT
XTALIN XTALOUT OSC DBUSB.XTALIN
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1/02/20101:34:45 PM Host_FPGA.SchDoc
Project Title Size:
Date:File:Revision:
Sheet of Time:A2Sheet Title Host Controller - Altera - EP3C10
Assy:81
NB3000AL - Altera
D-820-0053
Altium Limited 3 Minna Close Belrose NSW 2085Australia
FLASH2_CS_N
DIN DOUT SCLK
FLASH1_CS_N
SE RIAL FL ASH TMS TDO TDI
TCK TMS TDO
TDI TCK HARD
SOFT
HAR DSOFT_JTA G
DAT[3..0]
CMD CLK DETECT PROTECT
SD
TMS TDO TDI TCK TMS TDO
TDI TCK HARD
SOFT
HAR DSOFT_JTA G
FPGA_TDI
FPGA_TCK
FPGA_TMS
FPGA_TDO
NEXUS_TMS
NEXUS_TDO
NEXUS_TDI
NEXUS_TCK
CLKOE
USER FPGA JTAG
HOST USB
SRAM - 64K/256K x 16
HOSTUSB
HOST_SOFT_TDI
HOST_SOFT_TMS
HOST_SOFT_TDO
HOST_SOFT_TCK REF_CLK
FPGA_CLK
HOST JTAG
HOST_JTAG
HOST_HARD_TDI
HOST_HARD_TMS
HOST_HARD_TDO HOST_HARD_TCK
ONE WIRE ID
USERFLASH_DOUT
USERFLASH1_CS_N
USERFLASH2_CS_N CLKGEN_CS_N
RTC_CS
RTC_DOUT
USERFLASH_SCLK
CLKGEN_SCLK
RTC_SCLK USERFLASH_DIN CLKGEN_DIN
RTC_DIN SD_DAT[3..0]SD_CMD SD_CLK
SD_DETECT
SD_PROTECT SD
DB_JTAG
SYSTEM CLOCKS
FLASH_USER
HOST RTC
FLASH_BOOT_CLK
FLASH_BOOT_DIN USER 8MB SPI FLASH x2
SYSBOOT
LED1_GREEN LED1_BLUE
LED1_RED
LED2_GREEN LED2_BLUE
LED2_RED
Host LEDs
HOST SD CARD
HOST AUDIO - Delta-Sigma
USER FPGA PROGRAM
USER FPGA SPI
USER FPGA CLOCKS
TMS TCK TDI
TDO
DCLK
HOST_NonIO
Host_FPGA_NonIO.SchDoc
L
R
STE R E O
AOUT_R AOUT_L
HOST_AUDIO
CS_N
DIN DOUT INT_N
SCLK CLKOUT CLKOE R TC RTC
CLKOUT
RTC_INT_N
FPGA_CCLK
FPGA_DIN
FPGA_DONE FPGA_ID[3..0]
FPGA_INIT
FPGA_M[2..0]
FPGA_PROG_CLK FPGA_PROG_PWR_ON
FPGA_PROGRAM
DIN
DONE INSTALLED
ID[3..0]
CCLK
PROGRAM
M[2..0]INIT PROG_PWR_ON
PROG_CLK
DAU _CTR L
DB_PROGRAM
R 1_HOST
5R6 1%
DATA EXT_PROG
1W 1WID
CLK_FIXED CLK_PROG
CS_N DIN
SCLK CL K_PL L CLK_PLL
A[18..0]
D[15..0]NCS NWE NOE NBHE NBLE
SRA M-256Kx16
SRAM_A[18..0]SRAM_D[15..0]
SRAM_NWE SRAM_NOE
SRAM_NCS SRAM_NBHE
SRAM
SRAM_NBLE
GREEN RED BLUE
R GB_L E D
LED1
GREEN RED BLUE
R GB_L E D
LED2
REF_CLK
FPGA_CLK FPGA_CLK1
DB_CL OCKS REF_CLK
FPGA_CLK
DB_CLK1
DB_CLOCKS
MODE SEL
CLK DIN DOUT DB_SPI
DAU_SPI_CLK
DAU_SPI_DIN DAU_SPI_DOUT
DAU_SPI_MODE DAU_SPI_SEL
DB_SPI
PLATFORM UPGRADE
HARD
SOFT DETECT
TDI TDO TCK TMS
TDI
TDO TCK TMS EN
CLK[2..0]ID PIO[1..2]
ONE_WIRE_PB_ID_A ONE_WIRE_PIOA[1..2]PB_SPAREA[1..4]
CLK_ENA
CLK_EXTA[2..0]
EXTSPI_CSA_N[1..0]
AUTO_TDI_HARD AUTO_TDO_HARD
AUTO_TMS_HARD
AUTO_TCK_HARD AUTO_TDI_SOFT
AUTO_TDO_SOFT AUTO_TCK_SOFT AUTO_TMS_SOFT AUTO_JTAG
JTAG
CLK
1W
SPI_CS_N[1..0]
SPARE[1..4]
PBCTR L
PB_A
PB - Control
DOUT
DIN SCLK
E X TSPI
EXTSPI_SCLK
EXTSPI_DOUT
EXTSPI_DIN
EXTSPI
DIN DOUT SCLK
FLASH_CS_N
SE RFL ASH
FLASH_BOOT
GOLDEN
FL A SH_GOL D_CS_N DIN DOUT SCLK
FLASH_CS_N
SE RFL ASH
FLASH_GOLDEN
READY INT_N SLOE FIFOADR2FIFOADR0FIFOADR1PKTEND FLAGD_CS_N
FLAGA FLAGB FLAGC WR_N RD_N D[15..0]RESET_N
IFCLK XTALIN VBUS XTALOUT
U SB_INTF
USB2
HUSB_WR_N
HUSB_RD_N
HUSB_D[15..0]HUSB_RESET_N HUSB_READY HUSB_INT_N
HUSB_SLOE
HUSB_FIFOADR2
HUSB_FIFOADR0HUSB_FIFOADR1
HUSB_PKTEND HUSB_FLAGA HUSB_FLAGB HUSB_FLAGC
HUSB_IFCLK
HUSB_VBUS
HUSB_FLAGD_CS_N R 1
4K7 1%3V3
R 24K7 1%R 3
10K 1%
GND
3V3
PB SPI
1V2
3V3
HOST_DE COUPL ING_CAPS_1V2FPGA_Bypass_1V2.SCHDOC
HOST_DE COUPL ING_CAPS_3V3FPGA_Bypass_3V3.SCHDOC
USB_XTALIN
USB_XTALOUT
3V3
3V3
R 269330R 1%
R 2702K2 1%
R 271
1K 1%DIAG_DOUT DIAG_CLK
DIAG_DIN DIAG_CS_N DIN DOUT SCLK
FLASH_CS_N
DIA GCOM MS
DIAGCOMMS
3V3
DIAG_CS_N
R 994K7 1%
ONE_WIRE_ID
B A N K 1
IO D4IO E5IO
F5IO, (DQS2L/CQ3L)/(DQS2L/CQ3L)B1IO, DIFFIO_L1p C2IO, DIFFIO_L1n, (DATA1, ASDO)
C1IO, VREFB1N0F3IO, DIFFIO_L2p, (FLASH_nCE, nCSO)D2IO, DIFFIO_L2n D1IO G5IO, DIFFIO_L3p F2IO, DIFFIO_L3n F1IO, DIFFIO_L4p, (DQS0L/CQ1L,DPCLK0)/(DQS0L/CQ1L,DPCLK0)G2IO, DIFFIO_L4n G1IO, (DATA0)H2U30A
EP3C10F256C8
B A N K 2
IO, DIFFIO_L5p, (DQ1L)/_
J2IO, DIFFIO_L5n, (DQ1L)/_
J1IO
J6IO, DIFFIO_L6p K6IO, DIFFIO_L6n L6IO, DIFFIO_L7p
K2IO, DIFFIO_L7n, (DQ1L)/_
K1IO, DIFFIO_L8p, (DQS1L/CQ1L#,DPCLK1)/(DQS1L/CQ1L#,DPCLK1)
L2IO, DIFFIO_L8n, (DQ1L)/_
L1IO, VREFB2N0
L3IO, DIFFIO_L9p, (DQ1L)/_N2IO, DIFFIO_L9n, (DQ1L)/_
N1IO, RUP1, (DQ1L)/_K5IO, RDN1, (DQ1L)/_
L4IO, (DQS3L/CQ3L#)/(DQS3L/CQ3L#)
R1IO, DIFFIO_L10p, (DQ1L)/_
P2IO, DIFFIO_L10n, (DM1L/BWS#1L)/_
P1U30B
EP3C10F256C8
B A N K 3
IO, DIFFIO_B1p
N3IO, DIFFIO_B1n, (DM3B/BWS#3B)/(DM5B1/BWS#5B1)
P3
IO, DIFFIO_B2p, (DQ3B)/(DQ5B)
R3IO, DIFFIO_B2n
T3
IO, (DQS1B/CQ1B#,DPCLK2)/(DQS1B/CQ1B#,DPCLK2)
T2IO, PLL1_CLKOUTp R4IO, PLL1_CLKOUTn
T4IO, DIFFIO_B4p, (DQ3B)/(DQ5B)N5IO, DIFFIO_B4n, (DQ3B)/(DQ5B)
N6IO, (DQ3B)/(DQ5B)
M6IO, VREFB3N0
P6IO, DIFFIO_B5p, (DQS3B/CQ3B#)/(DQS3B/CQ3B#)
M7IO, DIFFIO_B5n
K8IO, DIFFIO_B6p, (DQ3B)/(DQ5B)
R5IO, DIFFIO_B6n
T5IO, DIFFIO_B7p, (DQ3B)/(DQ5B)
R6IO, DIFFIO_B7n T6IO, (DQ3B)/(DQ5B)
L7IO, DIFFIO_B8p, (DQ3B)/(DQ5B)
R7IO, DIFFIO_B8n, (DQS5B/CQ5B#)/(DQS5B/CQ5B#)
T7IO, DIFFIO_B9p, (DQ3B)/(DQ5B)
L8IO, DIFFIO_B9n, (DM5B/BWS#5B)/(DM5B0/BWS#5B0)
M8IO, DIFFIO_B10p, (DQ5B)/(DQ5B)N8IO, DIFFIO_B10n, (DQ5B)/(DQ5B)
P8IO, DIFFIO_B11p R8IO, DIFFIO_B11n
T8
U30C EP3C10F256C8B A N K 4
IO, DIFFIO_B12p
R9IO, DIFFIO_B12n T9
IO, DIFFIO_B13p K9IO, DIFFIO_B13n L9IO, DIFFIO_B14p
M9IO, DIFFIO_B14n, (DQ5B)/(DQ5B)N9IO, DIFFIO_B15p, (DQ5B)/(DQ5B)
R10IO, DIFFIO_B15n, (DQS4B/CQ5B)/(DQS4B/CQ5B)
T10IO, DIFFIO_B16p, (DQ5B)/(DQ5B)
R11IO, DIFFIO_B16n
T11IO, DIFFIO_B17p, (DQ5B)/(DQ5B)R12IO, DIFFIO_B17n, (DQ5B)/(DQ5B)
T12IO, DIFFIO_B18p K10IO, DIFFIO_B18n
L10IO, (DQS2B/CQ3B)/(DQS2B/CQ3B)
P9IO, VREFB4N0P11IO, DIFFIO_B19p
R13IO, DIFFIO_B19n, (DQ5B)/(DQ5B)
T13IO, RUP2M10IO, RDN2
N11IO, DIFFIO_B20p, (DQ5B)/(DQ5B)
T14IO, DIFFIO_B20n, (DQS0B/CQ1B,DPCLK3)/(DQS0B/CQ1B,DPCLK3)
T15IO
R14IO, DIFFIO_B21p P14IO, DIFFIO_B21n L11IO, DIFFIO_B22p M11IO, DIFFIO_B22n
N12U30D
EP3C10F256C8B A N K 5
IO
N13IO M12IO L12IO
K12IO, RUP3, (DM1R/BWS#1R)/_
N14IO, RDN3, (DQ1R)/_
P15IO, DIFFIO_R11n, (DQS3R/CQ3R#)/(DQS3R/CQ3R#)
P16IO, DIFFIO_R11p, (DQ1R)/_
R16IO
K11IO, DIFFIO_R10n, (DQ1R)/_N16IO, DIFFIO_R10p, (DQ1R)/_
N15IO, VREFB5N0L14IO, (DQ1R)/_
L13IO, DIFFIO_R9n, (DQ1R)/_
L16IO, DIFFIO_R9p
L15IO
J11IO, DIFFIO_R8n, (DQ1R)/_
K16IO, DIFFIO_R8p, (DQS1R/CQ1R#,DPCLK4)/(DQS1R/CQ1R#,DPCLK4)
K15IO, DIFFIO_R7n, (DEV_OE)J16IO, DIFFIO_R7p, (DEV_CLRn)J15IO, DIFFIO_R6n, (DQ1R)/_
J14IO, DIFFIO_R6p J12IO, (DQ1R)/_
J13
U30E
EP3C10F256C8
B A N K 6
IO, DIFFIO_R5n H16
IO, DIFFIO_R5p H15
IO, DIFFIO_R4n, (INIT_DONE)G16
IO, DIFFIO_R4p, (CRC_ERROR)G15
IO F13IO, DIFFIO_R3n, (nCEO)F16
IO, DIFFIO_R3p, (CLKUSR)F15
IO, (DQS0R/CQ1R,DPCLK5)/(DQS0R/CQ1R,DPCLK5)
B16IO, VREFB6N0F14
IO, DIFFIO_R2n D16
IO, DIFFIO_R2p D15
IO G11IO, DIFFIO_R1n, (DQS2R/CQ3R)/(DQS2R/CQ3R)C16
IO, DIFFIO_R1p C15
U30F EP3C10F256C8
B A N K 7
IO, DIFFIO_T21n
C14IO, DIFFIO_T21p, (DQ5T)/(DQ5T)
D14IO, DIFFIO_T20n
D11IO, DIFFIO_T20p, (DQS0T/CQ1T,DPCLK6)/(DQS0T/CQ1T,DPCLK6)
D12IO, DIFFIO_T19n
A13IO, DIFFIO_T19p, (DQ5T)/(DQ5T)
B13IO, PLL2_CLKOUTn A14IO, PLL2_CLKOUTp
B14IO, RUP4E11IO, RDN4
E10IO, DIFFIO_T18n, (DQ5T)/(DQ5T)A12IO, DIFFIO_T18p, (DQ5T)/(DQ5T)B12IO, DIFFIO_T17n, (DQ5T)/(DQ5T)A11IO, DIFFIO_T17p, (DQ5T)/(DQ5T)
B11IO, VREFB7N0C11IO, DIFFIO_T16n
F10IO, DIFFIO_T16p, (DQS2T/CQ3T)/(DQS2T/CQ3T)
F9IO, DIFFIO_T15n F11IO, DIFFIO_T15p
A15IO, DIFFIO_T14n, (DQ5T)/(DQ5T)A10IO, DIFFIO_T14p, (DQ5T)/(DQ5T)B10IO, DIFFIO_T13n, (DQ5T)/(DQ5T)
C9IO, DIFFIO_T13p, (DM5T/BWS#5T)/(DM5T0/BWS#5T0)
D9IO, (DQS4T/CQ5T)/(DQS4T/CQ5T)
E9IO, DIFFIO_T12n A9IO, DIFFIO_T12p
B9
U30G
EP3C10F256C8
B A N K 8
IO, DIFFIO_T11n A8IO, DIFFIO_T11p
B8
IO, (DQS5T/CQ5T#)/(DQS5T/CQ5T#)
C8IO, (DQ3T)/(DQ5T)
D8IO, DIFFIO_T10n, (DATA2), (DQ3T)/(DQ5T)
E8IO, DIFFIO_T10p, (DATA3)F8IO, DIFFIO_T9n, (DQ3T)/(DQ5T)
A7IO, DIFFIO_T9p, (DATA4), (DQ3T)/(DQ5T)
B7IO, DIFFIO_T8n F6IO, DIFFIO_T8p F7IO, VREFB8N0
C6IO, DIFFIO_T7n, (DQS3T/CQ3T#)/(DQS3T/CQ3T#)
A6IO, DIFFIO_T7p, (DQ3T)/(DQ5T)B6IO, (DATA5), (DQ3T)/(DQ5T)E7IO, (DATA6), (DQ3T)/(DQ5T)E6IO, (DATA7), (DQ3T)/(DQ5T)
A5IO, DIFFIO_T5n
A2IO, DIFFIO_T5p, (DQ3T)/(DQ5T)
B5IO, DIFFIO_T4n, (DM3T/BWS#3T)/(DM5T1/BWS#5T1)
A4IO, DIFFIO_T4p B4IO, DIFFIO_T3n D5IO, DIFFIO_T3p D6IO, DIFFIO_T2n
A3IO, DIFFIO_T2p, (DQS1T/CQ1T#,DPCLK7)/(DQS1T/CQ1T#,DPCLK7)
B3IO, DIFFIO_T1n C3IO, DIFFIO_T1p
D3U30H
EP3C10F256C8
CLK0, DIFFCLK_0p E2
CLK1, DIFFCLK_0n E1
CLK2, DIFFCLK_1p M2
CLK3, DIFFCLK_1n M1
CLK7, DIFFCLK_3n M16
CLK6, DIFFCLK_3p M15
CLK5, DIFFCLK_2n E16
CLK4, DIFFCLK_2p E15
U30I EP3C10F256C8
FPGA_CLK
DAU_SPI_DIN FPGA_DONE FLASH_GOLD_CS_N HUSB_D14HUSB_RD_N
HUSB_D9
HUSB_D7
HUSB_D13HUSB_D2
HUSB_D10SRAM_D4SRAM_A2SRAM_D0LED2_BLUE
FPGA_DIN FPGA_ID3NEXUS_TDO FPGA_TCK HUSB_FLAGD_CS_N HUSB_PKTEND
DAU_SPI_MODE HOST_SOFT_TDO HUSB_FLAGA HUSB_VBUS SRAM_A1SRAM_NOE LED2_RED
HUSB_RESET_N HUSB_D11HUSB_INT_N HUSB_IFCLK SRAM_D6SRAM_D14SRAM_NWE RTC_DIN
LED1_GREEN AUTO_TDO_HARD
FPGA_ID1
DAU_SPI_SEL FPGA_INIT HUSB_D8
HUSB_FIFOADR2HUSB_D3SRAM_A0SRAM_NBHE SRAM_D11NEXUS_TMS DAU_SPI_DOUT DAU_SPI_CLK HUSB_FIFOADR0HUSB_FLAGC HUSB_FLAGB AUTO_TDI_HARD
AOUT_R
CLKOE
LED1_RED FPGA_TMS HUSB_D15
FPGA_TDI HUSB_D0HUSB_D6HUSB_D5SRAM_NCS DB_CLK1
CLKGEN_SCLK SRAM_D8RTC_CS SRAM_D10HOST_SOFT_TMS SRAM_D15
PB_SPAREA2SRAM_A16SRAM_A3
AUTO_TDI_SOFT USERFLASH_SCLK SRAM_A12SRAM_A14
HUSB_READY
HOST_SOFT_TDI SRAM_A18HUSB_D4PB_SPAREA3DIAG_DOUT CLK_EXTA0
SRAM_D12SRAM_A10HUSB_D12REF_CLK
EXTSPI_DIN
CLK_EXTA1CLK_EXTA2SRAM_A11ONE_WIRE_ID SRAM_D9HOST_SOFT_TCK HUSB_WR_N FLASH_BOOT_CLK
RTC_INT_N
ONE_WIRE_PIOA1DIAG_CLK
USERFLASH_DOUT EXTSPI_CSA_N0USERFLASH_DIN SD_DETECT SD_CLK
SRAM_A8
SRAM_A13EXTSPI_DOUT
DIAG_CS_N SD_DAT0AUTO_TMS_HARD FPGA_ID0SRAM_NBLE CLKGEN_CS_N SD_PROTECT SD_DAT1ONE_WIRE_PB_ID_A SRAM_A15SD_CMD
SD_DAT3
DIAG_DIN
SD_DAT2
PLL1
PLL2
HUSB_SLOE HUSB_FIFOADR1AUTO_TCK_HARD
NEXUS_TCK SRAM_A4EXTSPI_SCLK
AOUT_L
AUTO_TDO_SOFT
CLKOUT EXTSPI_CSA_N1FPGA_M0RTC_DOUT RTC_SCLK
FL A SH_BOOT_DOU T FL A SH_BOOT_CS_N
NEXUS_TDI SRAM_D1
AUTO_TCK_SOFT FPGA_CCLK PB_SPAREA4ONE_WIRE_PIOA2CLK_ENA SRAM_A7
SRAM_A9
SRAM_A6SRAM_A17USERFLASH1_CS_N CLKGEN_DIN AUTO_JTAG LED1_BLUE
AUTO_TMS_SOFT
LED2_GREEN
FPGA_TDO
FPGA_ID2SRAM_D3SRAM_D5HUSB_D1
FL A SH_BOOT_DIN USERFLASH2_CS_N PB_SPAREA1FPGA_PROGRAM SRAM_A5
SRAM_D13SRAM_D7SRAM_D2FL A SH_GOL D_CS_N FLASH_BOOT_CS_N FL A SH_GOL D_CS_N FLASH_BOOT_CLK
FLASH_BOOT_DIN FL A SH_M AIN_CS_N
FL A SH_M AIN_CS_N PLATFORM UPGRADE
NO JUMPER INSTALLED - BOOT FROM MAIN FLASH JUMPER PINS 1 AND 2 - BOOT FROM GOLD FLASH
Altera SCD
Altera SCD
FLASH_BOOT_SEL
GND
3V3
FLASH_BOOT_CLK FLASH_BOOT_SEL FLASH_BOOT_SEL FLASH_BOOT_SEL
FL A SH_M AIN_CS_N
B11GND
2
B03A
4
VCC 5
S
6U 69FSA4157
1
2
J24
1x2 HEADER MALE
FL A SH_BOOT_DA TA OUT FL A SH_BOOT_DA TA OUT
FL A SH_BOOT_DA TA OUT
E X T
INT
PULLDOWN
PU LLD N x3.SCH D O C
EXT INT
PULLDOWN
PU LLD N x3.SCH D O C
1
12
23
34
45
56
67
78
89
910
1011
1112
1213
1314
1415
1516
16
D
D
C
C
B
B
A
A
021/02/20101:34:45 PM FPGA.SCHDOC
Project Title Size:
Assy:
Date:File:Revision:Time:A0Sheet Title 13Sheet of U S E R F PGA C on n ection s
81
N B 3000A L - A ltera
D-820-0053Altium Limited 3 Minna Close Belrose NSW 2085Australia
FPGA_TCK FPGA_TDI FPGA_TMS
FPGA_TDO FPGA_PROGRAM FPGA_M 03V3
FPGA_PROGRAM FPGA_TDO FPGA_INIT SRAM 1_NCS SRAM 1_A[18..0]
SRAM 1_D[15..0]SRAM 1_NBHE SRAM 1_NWE SRAM 1_NOE FPGA_DONE
FPGA_ID3FPGA_ID0
FPGA_ID1STATUS_LED BUZZER
BUZZER
SCL SDA
IO[35..0]FPGA_CCLK
FPGA_DIN
FPGA_DONE FPGA_ID[3..0]FPGA_INIT
FPGA_M [2..0]FPGA_PROG_CLK
FPGA_PROG_PWR_ON
FPGA_PROGRAM SW[4..0]ONE_WIRE_DB_PB
ONE_WIRE_DB_PB
SRAM 2_NCS SRAM 2_A[18..0]SRAM 2_D[15..0]SRAM 2_NBHE SRAM 2_NWE SRAM 2_NOE R14K7 1%
R24K7 1%
R34K7 1%
R44K7 1%
R8100R 1%R9100R 1%R10100R 1%R12100R 1%
R14
100R 1%R18100R 1%R23100R 1%R24100R 1%R22100R 1%R20
100R 1%
SRAM 1_NBLE SRAM 2_NBLE BUS_SDRAM _CLK
BUS_SDRAM _FEEDBACK
1
2
NT212NT312NT412NT5A[18..0]
D[15..0]NCS NWE NOE NBHE NBLE
SRAM-256Kx16
SRAM 2
A[18..0]D[15..0]NCS NWE NOE NBHE NBLE
SRAM-256Kx16
SRAM 1
BUS_A[24..1]
BUS_D[31..0]BUS_NOE BUS_NWE BUS_NBE[3..0]
BUS_SRAM _NCS
BUS_FLASH_NCS BUS_SDRAM _NCS BUS_SDRAM _CKE BUS_SDRAM _CLK BUS_SDRAM _NCAS BUS_SDRAM _NRAS BUS_FLASH_NRESET BUS_FLASH_NBUSY
HOSTMEMOR Y
BUS_A[24..1]BUS_D[31..0]BUS_NBE[3..0]
BUS_NWE
BUS_NOE BUS_FLASH_NCS BUS_FLASH_NRESET BUS_FLASH_NBUSY
BUS_SDRAM _NCS
BUS_SDRAM _CKE BUS_SDRAM _CLK
BUS_SDRAM _NCAS BUS_SDRAM _NRAS
BUS_SRAM _NCS
COMMON ME MORY RE SOU RCE S
M EM_COM M ON
STAN D AL ON ME MORY RE SOU RCE S
DIN
DONE INSTALLED
ID[3..0]CCLK PROGRAM M [2..0]INIT PROG_PWR_ON
PROG_CLK
DA U_CTR L
JTA G
P RO G RA M C L O C KS DB_PROGRAM
DAU_RESET_SW
P E RIP H E RAL S
SW D[4..0]
SW5
DATA
CLOCK PS2
KBCLOCK
KBDATA
M OUSECLOCK M OUSEDATA RS232_CTS
RS232_RTS RS232_RX RS232_TX RS232
KEYBOARD
M OUSE RXD TXD
RTS CTS
RS232_IN T
DATA CLOCK
PS2
DAU_RESET_SW
USERIO IO[35..0]
IO36
SCL
SDA
I2C
I2C 3V3GND
GND GND TFT_TSC_CLK TFT_TSC_DIN TFT_TSC_CS_N TFT_TSC_BUSY TFT_TSC_DOUT GREEN RED BLUE LED0_R LED0_G LED0_B
LED1_R
LED1_G LED1_B
LED2_R LED2_G LED2_B LED3_R LED3_G LED3_B
LED4_R LED4_G LED4_B
LED5_R LED5_G LED5_B LED6_R LED6_G LED6_B LED7_R
LED7_G
LED7_B
CODECI2S_DIN CODECI2S_DOUT CODECI2S_BCLK CODECI2S_M CLK CODECI2S_WCLK CODECSPI_DOUT CODECSPI_DIN CODECSPI_CLK
CODECSPI_CS CODEC
I2S_DOUT I2S_DIN
I2S_BCLK I2S_WCLK I2S_M CLK SPI_CLK
SPI_DIN SPI_DOUT SPI_CS_N AU DIO_DIGITAL
DIP[7..0]DIP
D[7..0]
SW8
DBUSB CLK
CM D DAT[3..0]DETECT PROTECT SD
DBSD
SDCLK
SDCM D
SDDETECT SDPROTECT SDDAT[3..0]E_RXC E_M DIO E_M DC E_RXER E_CRS
E_RXDV
E_RESETB_E E_TXEN
E_COL
E_TXC E_RXC E_TXC E_TXD[3..0]
E_TXEN
E_COL E_RXD[3..0]E_RXDV E_RESETB_E
E_M DIO E_M DC E_RXER E_CRS
Ethernet
E_TXD[3..0]E_RXD[3..0]ETH
IN
OUT
SPDIF
SPDIF SPDIF_OUT SPDIF_IN RED[7..0]GREEN[7..0]BLUE[7..0]VGA_CLK VGA_VSYNC VGA_HSYNC
VGA
VGA VGA_RED[7..0]
VGA_GREEN[7..0]VGA_BLUE[7..0]VGA_CLK VGA_VSYNC
VGA_HSYNC
TFT_CS TFT_RS
TFT_WR TFT_RD TFT_RESET TFT_DB[17..0]TFT_TSC_IRQ_N TFT_BLIGHT RELAY
RELAY[3..0]RELAY[3..0]RELAY 4
ADC CS CLK
DIN
DOUT
AD C_SPI
ADC_CS ADC_CLK ADC_DIN ADC_DOUT DAC CS
CLK DIN
DA C_SPI
DAC_CS DAC_CLK DAC_DIN M IDI
M IDI_TX
M IDI_RX
MIDI_INT
M IDI_TX M IDI_RX TMS TDO TDI TCK JTAG
TMS TDO
TDI TCK JTAG HARD
SOFT
HAR DSOFT_JTA G
FPGA_TDI FPGA_TCK FPGA_TMS FPGA_TDO NEXUS_TMS NEXUS_TDO NEXUS_TDI NEXUS_TCK DB_JTAG
REF_CLK
FPGA_CLK FPGA_CLK1
DB_C LOCKS
REF_CLKa FPGA_CLK
DAU_FPGA_CLK1DB_CLOCKS
PWM
PWM 0
PWM 1PWM 2PWM 3PWM4
P0_PWM P1_PWM P2_PWM P3_PWM
RS485TX_EN RXD
RX_EN TXD
RS485_IN T
M ODE SEL CLK
DIN DOUT DB_SPI
DAU_SPI_CLK DAU_SPI_DIN DAU_SPI_DOUT DAU_SPI_M ODE DAU_SPI_SEL
DB_SPI
TFT_TSC TFT_IO CS RS WR RD RESET DB[17..0]BL IR38KTX IR38KRX
TFT_IO
485_RXD 485_RX_EN 485_TX_EN 485_TXD USER_LEDS LED0
LED1LED2LED3
LED4
LED5
LED6LED7
USER _LED S
GREEN RED BLUE GREEN RED BLUE GREEN RED BLUE GREEN RED BLUE GREEN RED BLUE
GREEN RED BLUE GREEN RED BLUE EXT_A EXTEND_A[49..0]D[49..0]
PBIO
READY
INT_N SLOE FIFOADR2FIFOADR0FIFOADR1PKTEND FLAGD_CS_N
FLAGA FLAGB FLAGC WR_N RD_N D[15..0]RESET_N
IFCLK XTALIN VBUS XTALOUT USB_IN TF
U SB2
USB_WR_N USB_RD_N USB_D[15..0]USB_RESET_N USB_READY USB_INT_N USB_SLOE USB_FIFOADR2USB_FIFOADR0USB_FIFOADR1USB_PKTEND USB_FLAGA USB_FLAGB USB_FLAGC USB_IFCLK USB_VBUS USB_FLAGD_CS_N U SE R/D B F P GA
SP I
FPGA_DIN
FPGA_INIT FPGA_CCLK 1V2
3V3
USER _DEC OUPLING_CAPS_1V2
FPGA_Bypass_1V2.SCHDOC
USER _DEC OUPLING_CAPS_3V3FPGA_Bypass_3V3.SCHDOC
12NT3BUS_A[17..1]BUS_D[31..0]BUS_NWE BUS_ISP176X_DREQ BUS_ISP176X_NIRQ BUS_ISP176X_NCS BUS_ISP176X_DACK PROTOTYPE IO[35..0]IO[35..0]
IO36
R2722K2 1%
R2732K2 1%
R2742K2 1%
R2752K2 1%
3V3
3V3
GND GND BUS_SDRAM _CKE
BUS_SDRAM _CLK BUS_NOE ISP176X_RST
DA U_FPGA _CLK1
BU S_SDR AM_FEED BAC K FPGA_CLK NEXUS_TC K REF_CLKa BU S_SDR AM_C LK
SPAREIO1
SPAREIO2SPAREIO4SPAREIO3IR38KTX IR38KRX BUS_A[17..1]
BUS_D[31..0]BUS_NREAD BUS_NCS BUS_DMA_REQ BUS_DMA_ACK
BUS_NIRQ BUS_NWRITE
ISP176X_NRESET
ISP176X
ISP176X R2774K7 1%
R2784K7 1%
3V3
3V3
ONE_WIRE_DB_PB
R2834K7 1%
3V3
1
234
SPAREIO
SPAREIO B A N K 1
IO, DIFFIO_L1p D3
IO, DIFFIO_L1n, (DQ2L)/(DQ1L)/(DQ1L)C2
IO
M 9IO, DIFFIO_L2p, (DQ2L)/(DQ1L)/(DQ1L)D2
IO, DIFFIO_L2n, (DQ2L)/(DQ1L)/(DQ1L)D1
IO, VREFB1N0H7
IO, DIFFIO_L3p E5
IO, DIFFIO_L3n
E4IO, DIFFIO_L4p, (nRESET), (DQ2L)/(DQ1L)/(DQ1L)G6
IO, DIFFIO_L4n, (DQ2L)/(DQ1L)/(DQ1L)G5
IO, DIFFIO_L5p H4
IO, DIFFIO_L5n H3
IO, DIFFIO_L6p
J5IO, DIFFIO_L6n
G7IO, DIFFIO_L7p, (DQS2L/CQ3L,CDPCLK0)/(DQS2L/CQ3L,CDPCLK0)/(DQS2L/CQ3L,CDPCLK0)E3
IO, DIFFIO_L7n, (DQ2L)/(DQ1L)/(DQ1L)F3
IO, DIFFIO_L8p, (DQ2L)/(DQ1L)/(DQ1L)
F5
IO, DIFFIO_L8n, (DATA1, ASDO)F4IO, VREFB1N1L5
IO, DIFFIO_L9p, (DQ2L)/(DQ1L)/(DQ1L)G4
IO, DIFFIO_L9n G3
IO, DIFFIO_L10p, (FLASH_nCE, nCSO)
E2IO, DIFFIO_L10n
J6IO, DIFFIO_L11p, _/(DQ1L)/(DQ1L)E1
IO, DIFFIO_L11n J7
IO, DIFFIO_L12p, (DM 2L)/(DM 1L0/BWS#1L0)/(DM 1L0/BWS#1L0)F2
IO, DIFFIO_L12n, (DQ0L)/(DQ1L)/(DQ1L)
F1IO, DIFFIO_L13p K4
IO, DIFFIO_L13n K3
IO, DIFFIO_L14p K7
IO, DIFFIO_L14n
L6
IO, DIFFIO_L15p
L8IO, DIFFIO_L15n L7
IO, DIFFIO_L16p M 8
IO, DIFFIO_L16n M 7
IO, DIFFIO_L17p L4
IO, DIFFIO_L17n L3IO, DIFFIO_L18p H6
IO, DIFFIO_L18n H5
IO, DIFFIO_L19p J4
IO, DIFFIO_L19n, (DQ0L)/(DQ1L)/(DQ1L)
J3IO, VREFB1N2N8
IO, DIFFIO_L20p, (DQ0L)/(DQ1L)/(DQ1L)G2
IO, DIFFIO_L20n G1
IO, DIFFIO_L21p M 3
IO, DIFFIO_L21n, (DQ0L)/(DQ1L)/(DQ1L)K1
IO, DIFFIO_L22p N4
IO, DIFFIO_L22n N3
IO M 4IO, (DQS0L/CQ1L,DPCLK0)/(DQS0L/CQ1L,DPCLK0)/(DQS0L/CQ1L,DPCLK0)K2
IO, DIFFIO_L23p L2
IO, DIFFIO_L23n, (DQ0L)/(DQ1L)/(DQ1L)L1
IO, VREFB1N3M 5
IO, DIFFIO_L24p M 2
IO, DIFFIO_L24n, (DQ0L)/(DQ1L)/(DQ1L)
M 1IO, DIFFIO_L25p P2
IO, DIFFIO_L25n, (DQ0L)/(DQ1L)/(DQ1L)P1
IO, (DATA0)N7
U8A
EP3C40F780C8N
B A N K 2
IO, DIFFIO_L26p, (DQ0L)/(DQ1L)/(DQ1L)R2
IO, DIFFIO_L26n, _/(DQ1L)/(DQ1L)R1
IO, DIFFIO_L27p, (DM 0L)/(DM 1L1/BWS#1L1)/(DM 1L1/BWS#1L1)U3
IO, DIFFIO_L27n U2
IO, DIFFIO_L28p, (DQ1L)/(DQ3L)/(DQ1L)R3
IO, DIFFIO_L28n R6
IO, DIFFIO_L29p, (DQ1L)/(DQ3L)/(DQ1L)R4
IO, DIFFIO_L29n R7
IO, DIFFIO_L30p, (DQ1L)/(DQ3L)/(DQ1L)T4
IO, DIFFIO_L30n T3
IO, VREFB2N0T8
IO, DIFFIO_L31p U4
IO, DIFFIO_L31n, (DQ1L)/(DQ3L)/(DQ1L)R5
IO, DIFFIO_L32p, (DQ1L)/(DQ3L)/(DQ1L)U1
IO, DIFFIO_L32n, (DQ1L)/(DQ3L)/(DQ1L)V4
IO, DIFFIO_L33p
V3IO, DIFFIO_L33n, (DQ1L)/(DQ3L)/(DQ1L)V2
IO V9IO, DIFFIO_L34p, (DQS1L/CQ1L#,DPCLK1)/(DQS1L/CQ1L#,DPCLK1)/(DQS1L/CQ1L#,DPCLK1)
AB2IO, DIFFIO_L34n AB1
IO, (DQ1L)/(DQ3L)/(DQ1L)V1
IO, DIFFIO_L35p, (DQ1L)/(DQ3L)/(DQ1L)W2
IO, DIFFIO_L35n, (DM 1L/BWS#1L)/(DM 3L0/BWS#3L0)/(DM 1L2/BWS#1L2)W1
IO, DIFFIO_L36p W3
IO, DIFFIO_L36n
W4IO, DIFFIO_L37p V6
IO, DIFFIO_L37n U5
IO, DIFFIO_L38p Y5
IO, DIFFIO_L38n Y6IO, DIFFIO_L39p V5
IO, DIFFIO_L39n, (DQ3L)/(DQ3L)/(DQ1L)U6
IO, DIFFIO_L40p AA7
IO, DIFFIO_L40n AA6
IO, VREFB2N1
T7IO, DIFFIO_L41p AA8
IO, DIFFIO_L41n Y7
IO, DIFFIO_L42p, (DQ3L)/(DQ3L)/(DQ1L)Y4
IO, DIFFIO_L42n Y3
IO, DIFFIO_L43p T9
IO, DIFFIO_L43n, (DQ3L)/(DQ3L)/(DQ1L)AC2
IO, DIFFIO_L44p W8
IO, DIFFIO_L44n, (DQ3L)/(DQ3L)/(DQ1L)AC1
IO, DIFFIO_L45p
V7IO, DIFFIO_L45n, (DQ3L)/(DQ3L)/(DQ1L)AC3
IO, DIFFIO_L46p, (DQ3L)/(DQ3L)/(DQ1L)AD2
IO, DIFFIO_L46n AD1
IO, DIFFIO_L47p, (DQ3L)/(DQ3L)/(DQ1L)AB3
IO, DIFFIO_L47n, (DQ3L)/(DQ3L)/(DQ1L)AA4
IO W9IO, DIFFIO_L48p AB7
IO, DIFFIO_L48n AC7
IO, VREFB2N2
V8IO, DIFFIO_L49p AE1
IO, DIFFIO_L49n, (DQ3L)/(DQ3L)/(DQ1L)AE2
IO, DIFFIO_L50p AA5
IO, DIFFIO_L50n, (DM 3L/BWS#3L)/(DM 3L1/BWS#3L1)/(DM 1L3/BWS#1L3)AF2
IO, DIFFIO_L51p AB6
IO, DIFFIO_L51n AB5IO AA3IO, RUP1U7
IO, RDN1U8
IO, DIFFIO_L52p AC4
IO, DIFFIO_L52n AD3
IO AD4IO, (DQS3L/CQ3L#,CDPCLK1)/(DQS3L/CQ3L#,CDPCLK1)/(DQS3L/CQ3L#,CDPCLK1)AE3
IO, VREFB2N3AB4
IO AB8
IO, DIFFIO_L53p AC5
IO, DIFFIO_L53n AD5
IO, DIFFIO_L54p AE4
IO, DIFFIO_L54n AF3
U8B
EP3C40F780C8N
B A N K 3
IO, DIFFIO_B1p
AC11IO, DIFFIO_B1n AD11
IO, DIFFIO_B2p
AD12
IO, DIFFIO_B2n, (DM 1B)/_/_AE6IO, DIFFIO_B3p, (DQ1B)/_/_
AF4IO, DIFFIO_B3n AB12IO, VREFB3N3Y10IO, DIFFIO_B4p
AG4IO, DIFFIO_B4n, (DQ1B)/_/_
AG3IO, DIFFIO_B5p AE7IO, DIFFIO_B5n
AE8IO, DIFFIO_B6p, (DQS1B/CQ1B#,CDPCLK2)/(DQS1B/CQ1B#,CDPCLK2)/(DQS1B/CQ1B#,CDPCLK2)
AD7IO, DIFFIO_B6n Y12IO, PLL1_CLKOUTp AE5IO, PLL1_CLKOUTn AF5IO, DIFFIO_B7p, (DQ1B)/_/_
AH3IO, DIFFIO_B7n W10IO, (DQ1B)/_/_AF6IO, VREFB3N2AA12IO, DIFFIO_B8p
AC12IO, DIFFIO_B8n, (DQ1B)/_/_
AH4IO, DIFFIO_B9p
AC10IO, DIFFIO_B9n, (DQ1B)/_/_AD8IO, DIFFIO_B10p, (DQ1B)/_/_
AG6IO, DIFFIO_B10n
AB13IO, DIFFIO_B11p, (DQ1B)/_/_
AH6IO, DIFFIO_B11n
AA13IO, DIFFIO_B12p, (DM 3B/BWS#3B)/(DM 3B1/BWS#3B1)/(DM 5B3/BWS#5B3)
AB9IO, DIFFIO_B12n, (DQ3B)/(DQ3B)/(DQ5B)AD10IO, DIFFIO_B13p, (DQ3B)/(DQ3B)/(DQ5B)
AG7IO, DIFFIO_B13n
Y13IO, (DQ3B)/(DQ3B)/(DQ5B)
AH7IO, DIFFIO_B14p, (DQ3B)/(DQ3B)/(DQ5B)AC8IO, DIFFIO_B14n, (DQ3B)/(DQ3B)/(DQ5B)
AA10IO
Y14IO, DIFFIO_B15p, (DQ3B)/(DQ3B)/(DQ5B)
AG8IO, DIFFIO_B15n Y15IO, VREFB3N1
AB11IO, DIFFIO_B16p, (DQS3B/CQ3B#,DPCLK2)/(DQS3B/CQ3B#,DPCLK2)/(DQS3B/CQ3B#,DPCLK2)
AE10IO, DIFFIO_B16n, (DQ3B)/(DQ3B)/(DQ5B)AH8IO, DIFFIO_B17p, (DQ3B)/(DQ3B)/(DQ5B)
AF7IO, DIFFIO_B17n
AH10IO, DIFFIO_B18p, (DQ3B)/(DQ3B)/(DQ5B)
AF9IO, DIFFIO_B18n
AH12IO, DIFFIO_B19p, (DM 5B/BWS#5B)/(DM 3B0/BWS#3B0)/(DM 5B2/BWS#5B2)
AF8IO, DIFFIO_B19n
AF12IO, DIFFIO_B20p, (DQ5B)/(DQ3B)/(DQ5B)
AE9IO, DIFFIO_B20n
AF13IO, DIFFIO_B21p, (DQ5B)/(DQ3B)/(DQ5B)
AF10IO, DIFFIO_B21n, (DQS5B/CQ5B#,DPCLK3)/(DQS5B/CQ5B#,DPCLK3)/(DQS5B/CQ5B#,DPCLK3)
AF11IO, VREFB3N0
AA14IO, DIFFIO_B22p, (DQ5B)/(DQ3B)/(DQ5B)AG10IO, DIFFIO_B22n, (DQ5B)/(DQ3B)/(DQ5B)AE12IO, DIFFIO_B23p, (DQ5B)/(DQ3B)/(DQ5B)AE11IO, DIFFIO_B23n, (DQ5B)/(DQ3B)/(DQ5B)AG11IO, DIFFIO_B24p, (DQ5B)/(DQ3B)/(DQ5B)
AH11IO, DIFFIO_B24n
AB14IO, DIFFIO_B25p, (DQ5B)/(DQ3B)/(DQ5B)
AE13IO, DIFFIO_B25n
AC14IO, DIFFIO_B26p, (DQ5B)/(DQ3B)/(DQ5B)
AG12IO, DIFFIO_B26n AD14IO, DIFFIO_B27p AE14IO, DIFFIO_B27n
AF14U8C
EP3C40F780C8N
B A N K 4
IO, DIFFIO_B28p AB15
IO, DIFFIO_B28n, (DM 4B)/(DM 5B1/BWS#5B1)/(DM 5B1/BWS#5B1)AC15
IO, DIFFIO_B29p AD15
IO, DIFFIO_B29n, _/(DQ5B)/(DQ5B)AE15
IO AA16
IO, VREFB4N3AA15
IO, DIFFIO_B30p, (DQ4B)/(DQ5B)/(DQ5B)AF15
IO, DIFFIO_B30n, (DQ4B)/(DQ5B)/(DQ5B)AG17
IO, DIFFIO_B31p, (DQ4B)/(DQ5B)/(DQ5B)AH17
IO, DIFFIO_B31n W16
IO, DIFFIO_B32p, (DQ4B)/(DQ5B)/(DQ5B)AF16
IO, DIFFIO_B32n, (DQS4B/CQ5B,DPCLK4)/(DQS4B/CQ5B,DPCLK4)/(DQS4B/CQ5B,DPCLK4)AF17
IO, DIFFIO_B33p, (DQ4B)/(DQ5B)/(DQ5B)AB16
IO, DIFFIO_B33n AE16
IO, DIFFIO_B34p, (DQ4B)/(DQ5B)/(DQ5B)AE17
IO, DIFFIO_B34n, (DQ4B)/(DQ5B)/(DQ5B)
AG18IO, DIFFIO_B35p, (DQ4B)/(DQ5B)/(DQ5B)AH18
IO, DIFFIO_B35n, (DM 2B)/(DM 5B0/BWS#5B0)/(DM 5B0/BWS#5B0)AH19
IO, DIFFIO_B36p, (DQ2B)/(DQ5B)/(DQ5B)
AD17IO, DIFFIO_B36n AF18
IO, (DQS2B/CQ3B,DPCLK5)/(DQS2B/CQ3B,DPCLK5)/(DQS2B/CQ3B,DPCLK5)AE18
IO, VREFB4N2Y17
IO, DIFFIO_B37p, (DQ2B)/(DQ5B)/(DQ5B)AG21
IO, DIFFIO_B37n AC17
IO, DIFFIO_B38p, (DQ2B)/(DQ5B)/(DQ5B)
AH21IO, DIFFIO_B38n, (DQ2B)/(DQ5B)/(DQ5B)AG22
IO, DIFFIO_B39p, (DQ2B)/(DQ5B)/(DQ5B)AH22
IO, DIFFIO_B39n AG19
IO, DIFFIO_B40p, (DQ2B)/(DQ5B)/(DQ5B)AH23
IO, DIFFIO_B40n, (DQ2B)/(DQ5B)/(DQ5B)AE19
IO, DIFFIO_B41p, (DQ2B)/(DQ5B)/(DQ5B)AF24
IO, DIFFIO_B41n AF19
IO, DIFFIO_B42p, (DM 0B)/(DQ5B)/(DQ5B)AF25
IO, DIFFIO_B42n, (DQ0B)/_/_
AF20IO, (DQ0B)/_/_AD18
IO, DIFFIO_B43p Y19
IO, DIFFIO_B43n, (DQ0B)/_/_AE21
IO, VREFB4N1AC18
IO, DIFFIO_B44p AB18
IO, DIFFIO_B44n AA19
IO, DIFFIO_B45p AD19
IO, DIFFIO_B45n AE20
IO, DIFFIO_B46p
AC19IO, DIFFIO_B46n AB19
IO, RUP2AA17
IO, RDN2AB17
IO AD21IO, DIFFIO_B47p AF21
IO, DIFFIO_B47n, (DQ0B)/_/_AE25
IO, DIFFIO_B48p AC21
IO, DIFFIO_B48n, (DQS0B/CQ1B,CDPCLK3)/(DQS0B/CQ1B,CDPCLK3)/(DQS0B/CQ1B,CDPCLK3)AF26
IO, DIFFIO_B49p
AG25IO, DIFFIO_B49n, (DQ0B)/_/_AH25
IO, VREFB4N0AB20
IO, DIFFIO_B50p AG23
IO, DIFFIO_B50n, (DQ0B)/_/_AF22
IO, DIFFIO_B51p, (DQ0B)/_/_AE24
IO, DIFFIO_B51n, (DQ0B)/_/_AG26IO, PLL4_CLKOUTp AE23
IO, PLL4_CLKOUTn AF23
IO, DIFFIO_B52p AD22
IO, DIFFIO_B52n AE22
IO, DIFFIO_B53p AB21
IO, DIFFIO_B53n AC22
IO AH26U8D
EP3C40F780C8N
B A N K 5
IO, DIFFIO_R56n AA21IO, DIFFIO_R56p
AB22IO, DIFFIO_R55n, (DM 3R/BWS#3R)/(DM 3R1/BWS#3R1)/(DM 1R3/BWS#1R3)
AB24
IO, DIFFIO_R55p
AC24IO, RUP3AA22IO, RDN3
AB23IO
AD25IO, (DQS3R/CQ3R#,CDPCLK4)/(DQS3R/CQ3R#,CDPCLK4)/(DQS3R/CQ3R#,CDPCLK4)
AF27IO, DIFFIO_R54n AE26IO, DIFFIO_R54p AE27IO, DIFFIO_R53n Y22IO, DIFFIO_R53p AD24IO, VREFB5N3AA24IO, DIFFIO_R52n
AC25IO, DIFFIO_R52p, (DQ3R)/(DQ3R)/(DQ1R)AD26IO, DIFFIO_R51n, (DQ3R)/(DQ3R)/(DQ1R)
AE28IO, DIFFIO_R51p
AA23IO, DIFFIO_R50n, (DQ3R)/(DQ3R)/(DQ1R)
AD28IO, DIFFIO_R50p
Y23IO, DIFFIO_R49n, (DQ3R)/(DQ3R)/(DQ1R)
AD27IO, DIFFIO_R49p
AC26IO, DIFFIO_R48n, (DQ3R)/(DQ3R)/(DQ1R)
Y24IO, DIFFIO_R48p
W22IO, DIFFIO_R47n, (DQ3R)/(DQ3R)/(DQ1R)
AC28IO, DIFFIO_R47p
W21IO, DIFFIO_R46n, (DQ3R)/(DQ3R)/(DQ1R)AC27IO, DIFFIO_R46p, (DQ3R)/(DQ3R)/(DQ1R)
AB26IO
V26IO, VREFB5N2
U24IO
V22IO, DIFFIO_R45n, (DQ3R)/(DQ3R)/(DQ1R)
AA26IO, DIFFIO_R45p
U26IO, DIFFIO_R44n, (DM 1R/BWS#1R)/(DM 3R0/BWS#3R0)/(DM 1R2/BWS#1R2)
AB28IO, DIFFIO_R44p, (DQ1R)/(DQ3R)/(DQ1R)
AB27IO, DIFFIO_R43n
V21IO, DIFFIO_R43p, (DQ1R)/(DQ3R)/(DQ1R)
Y26IO, DIFFIO_R42n
U20IO, DIFFIO_R42p, (DQ1R)/(DQ3R)/(DQ1R)W26IO, DIFFIO_R41n, (DQ1R)/(DQ3R)/(DQ1R)W27IO, DIFFIO_R41p, (DQ1R)/(DQ3R)/(DQ1R)
W28IO, DIFFIO_R40n
AB25IO, DIFFIO_R40p, (DQ1R)/(DQ3R)/(DQ1R)
V28IO, DIFFIO_R39n AA25IO, DIFFIO_R39p V27IO, VREFB5N1
U23IO
W25IO, DIFFIO_R38n, (DQ1R)/(DQ3R)/(DQ1R)
V25IO, DIFFIO_R38p R22IO, DIFFIO_R37n V24IO, DIFFIO_R37p U27IO, DIFFIO_R36n
V23IO, DIFFIO_R36p, (DQ1R)/(DQ3R)/(DQ1R)
U28IO, DIFFIO_R35n Y25IO, DIFFIO_R35p T26IO, DIFFIO_R34n W20IO, DIFFIO_R34p U22IO, DIFFIO_R33n
V20IO, DIFFIO_R33p, (DQS1R/CQ1R#,DPCLK6)/(DQS1R/CQ1R#,DPCLK6)/(DQS1R/CQ1R#,DPCLK6)
T25IO, DIFFIO_R32n, (DEV_OE)T22IO, DIFFIO_R32p, (DEV_CLRn)
T21IO, DIFFIO_R31n, (DQ1R)/(DQ3R)/(DQ1R)
R26IO, DIFFIO_R31p
R25IO, DIFFIO_R30n, (DM 0R)/(DM 1R1/BWS#1R1)/(DM 1R1/BWS#1R1)
R28IO, DIFFIO_R30p U25IO, VREFB5N0R24IO, _/(DQ1R)/(DQ1R)
R27IO, DIFFIO_R29n R23IO, DIFFIO_R29p
R21IO
P21
U8E
EP3C40F780C8N
B A N K 6
IO, DIFFIO_R28n
K25IO, DIFFIO_R28p
M 24
IO, DIFFIO_R27n, (INIT_DONE)P26
IO, DIFFIO_R27p, (CRC_ERROR)
P25IO, DIFFIO_R26n H26IO, DIFFIO_R26p L25
IO, VREFB6N3N21IO, DIFFIO_R25n N25IO, DIFFIO_R25p
G24IO, DIFFIO_R24n, (nCEO)P28IO, DIFFIO_R24p, (CLKUSR)
P27IO, DIFFIO_R23n, (DQS0R/CQ1R,DPCLK7)/(DQS0R/CQ1R,DPCLK7)/(DQS0R/CQ1R,DPCLK7)
N26IO, DIFFIO_R23p
L22IO, DIFFIO_R22n, (DQ0R)/(DQ1R)/(DQ1R)
M 28IO, DIFFIO_R22p
M 23IO, (DQ0R)/(DQ1R)/(DQ1R)
M 27IO, DIFFIO_R21n
L20IO, DIFFIO_R21p, (DQ0R)/(DQ1R)/(DQ1R)
M 26IO, DIFFIO_R20n K22IO, DIFFIO_R20p
L23IO
J26IO, DIFFIO_R19n H25IO, DIFFIO_R19p K21IO, VREFB6N2M 25IO, DIFFIO_R18n
J23IO, DIFFIO_R18p, (DQ0R)/(DQ1R)/(DQ1R)L28IO, DIFFIO_R17n, (DQ0R)/(DQ1R)/(DQ1R)L27IO, DIFFIO_R17p, (DQ0R)/(DQ1R)/(DQ1R)
L24IO, DIFFIO_R16n
E25IO, DIFFIO_R16p, (DQ0R)/(DQ1R)/(DQ1R)
K28IO, DIFFIO_R15n
F24IO, DIFFIO_R15p, (DQ0R)/(DQ1R)/(DQ1R)
K27IO, DIFFIO_R14n
J24IO, DIFFIO_R14p, (DM 2R)/(DM 1R0/BWS#1R0)/(DM 1R0/BWS#1R0)
L26IO, DIFFIO_R13n
H23IO, DIFFIO_R13p, _/(DQ1R)/(DQ1R)
J25IO, DIFFIO_R12n, (nWE), (DQ2R)/(DQ1R)/(DQ1R)G28IO, DIFFIO_R12p, (nOE), (DQ2R)/(DQ1R)/(DQ1R)
G27IO, DIFFIO_R11n H22IO, DIFFIO_R11p H24IO, VREFB6N1M 21IO, DIFFIO_R10n
G25IO, DIFFIO_R10p, (DQ2R)/(DQ1R)/(DQ1R)
K26IO, DIFFIO_R9n G26IO, DIFFIO_R9p
G23IO, DIFFIO_R8n, (nAVD), (DQ2R)/(DQ1R)/(DQ1R)
F28IO, DIFFIO_R8p, (RDY)
F27IO, DIFFIO_R7n, (PADD23), (DQ2R)/(DQ1R)/(DQ1R)
E28IO, DIFFIO_R7p
G22IO, DIFFIO_R6n, (DQ2R)/(DQ1R)/(DQ1R)
E27IO, DIFFIO_R6p
H21IO, (DQ2R)/(DQ1R)/(DQ1R)F26IO, DIFFIO_R5n, (PADD22)
D28IO, DIFFIO_R5p, (PADD21), (DQ2R)/(DQ1R)/(DQ1R)
D27IO, DIFFIO_R4n, (PADD20), (DQS2R/CQ3R,CDPCLK5)/(DQS2R/CQ3R,CDPCLK5)/(DQS2R/CQ3R,CDPCLK5)
C27IO, DIFFIO_R4p F25IO, VREFB6N0J22IO, DIFFIO_R3n E26IO, DIFFIO_R3p E24IO, DIFFIO_R2n D25IO, DIFFIO_R2p D24IO, DIFFIO_R1n D26IO, DIFFIO_R1p
C26U8F
EP3C40F780C8N
B A N K 7
IO G21
IO, DIFFIO_T52n, (DQ0T)/_/_B26
IO, DIFFIO_T52p, (DQ0T)/_/_
D22
IO, DIFFIO_T51n, (DQ0T)/_/_E22
IO, DIFFIO_T51p J19
IO, DIFFIO_T50n, (DQ0T)/_/_A26
IO, DIFFIO_T50p G20
IO, (DQ0T)/_/_
B25IO, DIFFIO_T49n G19
IO, DIFFIO_T49p, (DQS0T/CQ1T,CDPCLK6)/(DQS0T/CQ1T,CDPCLK6)/(DQS0T/CQ1T,CDPCLK6)A25
IO, DIFFIO_T48n, (DQ0T)/_/_F21
IO, DIFFIO_T48p, (DQ0T)/_/_C25
IO, VREFB7N0
F22IO, (DQ0T)/_/_
A23IO, DIFFIO_T47n H19
IO, DIFFIO_T47p, (DM 0T)/_/_B23
IO, PLL2_CLKOUTn
C23
IO, PLL2_CLKOUTp D23
IO, DIFFIO_T46n, (DQ2T)/(DQ5T)/(DQ5T)C24
IO, DIFFIO_T46p E21
IO, RUP4F19
IO, RDN4
E19IO, (DQ2T)/(DQ5T)/(DQ5T)
C22IO, DIFFIO_T45n, (DQ2T)/(DQ5T)/(DQ5T)D21
IO, DIFFIO_T45p, (PADD0)B22
IO, VREFB7N1F18
IO, DIFFIO_T44n, (DQ2T)/(DQ5T)/(DQ5T)
C21IO, DIFFIO_T44p D19
IO, DIFFIO_T43n, (DQ2T)/(DQ5T)/(DQ5T)A22
IO, DIFFIO_T43p, (DQ2T)/(DQ5T)/(DQ5T)A21
IO, DIFFIO_T42n, (DQ2T)/(DQ5T)/(DQ5T)
B21
IO, DIFFIO_T42p, (DQ2T)/(DQ5T)/(DQ5T)
E18IO, DIFFIO_T41n, (PADD1), _/(DQ5T)/(DQ5T)C18
IO, DIFFIO_T41p, (PADD2)D18
IO, DIFFIO_T40n, (DM 2T)/(DM 5T0/BWS#5T0)/(DM 5T0/BWS#5T0)C20
IO, DIFFIO_T40p H17
IO, VREFB7N2G17IO, DIFFIO_T39n, (DQ4T)/(DQ5T)/(DQ5T)D20
IO, DIFFIO_T39p, (DQ4T)/(DQ5T)/(DQ5T)C19
IO, DIFFIO_T38n, (PADD3), (DQ4T)/(DQ5T)/(DQ5T)C17
IO, DIFFIO_T38p
G18IO H15IO, DIFFIO_T37n F17
IO, DIFFIO_T37p, (PADD4), (DQS2T/CQ3T,DPCLK8)/(DQS2T/CQ3T,DPCLK8)/(DQS2T/CQ3T,DPCLK8)D17
IO, DIFFIO_T36n, (PADD5), (DQ4T)/(DQ5T)/(DQ5T)A19
IO, DIFFIO_T36p, (PADD6), (DQ4T)/(DQ5T)/(DQ5T)B19IO, DIFFIO_T35n, (PADD7)A18
IO, DIFFIO_T35p, (PADD8), (DQ4T)/(DQ5T)/(DQ5T)B18
IO, DIFFIO_T34n, (DQ4T)/(DQ5T)/(DQ5T)E17
IO, DIFFIO_T34p J16
IO, DIFFIO_T33n J17
IO, DIFFIO_T33p H16
IO, DIFFIO_T32n G16
IO, DIFFIO_T32p F15
IO, VREFB7N3
G15IO, DIFFIO_T31n, (PADD9), (DQ4T)/(DQ5T)/(DQ5T)C16
IO, DIFFIO_T31p, (PADD10)D16
IO, DIFFIO_T30n H14
IO, DIFFIO_T30p K15
IO, DIFFIO_T29n, (PADD11), _/(DQ5T)/(DQ5T)A17
IO, DIFFIO_T29p, (PADD12), (DQS4T/CQ5T,DPCLK9)/(DQS4T/CQ5T,DPCLK9)/(DQS4T/CQ5T,DPCLK9)B17
IO, DIFFIO_T28n, (DM 4T)/(DM 5T1/BWS#5T1)/(DM 5T1/BWS#5T1)E15
IO, DIFFIO_T28p J14
IO, DIFFIO_T27n, (PADD13)
C15
IO, DIFFIO_T27p, (PADD14), (DQ5T)/(DQ3T)/(DQ5T)D15
U8G
EP3C40F780C8N
B A N K 8
IO, DIFFIO_T26n, (DQ5T)/(DQ3T)/(DQ5T)C13IO, DIFFIO_T26p, (DQ5T)/(DQ3T)/(DQ5T)D13
IO, DIFFIO_T25n, (DQ5T)/(DQ3T)/(DQ5T)
C14
IO, DIFFIO_T25p, (PADD15)
D14IO, DIFFIO_T24n, (PADD16), (DQ5T)/(DQ3T)/(DQ5T)
C12IO, DIFFIO_T24p, (PADD17), (DQS5T/CQ5T#,DPCLK10)/(DQS5T/CQ5T#,DPCLK10)/(DQS5T/CQ5T#,DPCLK10)
D12
IO, DIFFIO_T23n, (DQ5T)/(DQ3T)/(DQ5T)
A12IO, DIFFIO_T23p B12IO, VREFB8N0G14IO, DIFFIO_T22n K13IO, DIFFIO_T22p
F14IO, (DQ5T)/(DQ3T)/(DQ5T)
E14IO, DIFFIO_T21n H12IO, DIFFIO_T21p
J12IO, DIFFIO_T20n, (DATA2), (DQ5T)/(DQ3T)/(DQ5T)A11IO, DIFFIO_T20p, (DATA3), (DQ5T)/(DQ3T)/(DQ5T)
B11IO, DIFFIO_T19n, (PADD18)
A10IO, DIFFIO_T19p, (DATA4), (DM5T/BWS#5T)/(DM 3T0/BWS#3T0)/(DM 5T2/BWS#5T2)
B10IO, DIFFIO_T18n, (PADD19)
G13IO, DIFFIO_T18p, (DATA15), (DQ3T)/(DQ3T)/(DQ5T)
H13IO, DIFFIO_T17n
B8IO, DIFFIO_T17p, (DQ3T)/(DQ3T)/(DQ5T)
C10IO
D11IO, VREFB8N1
F11IO, DIFFIO_T16n, (DATA14), (DQS3T/CQ3T#,DPCLK11)/(DQS3T/CQ3T#,DPCLK11)/(DQS3T/CQ3T#,DPCLK11)
E12IO, DIFFIO_T16p, (DATA13)
F12IO, DIFFIO_T15n, (DQ3T)/(DQ3T)/(DQ5T)
D10IO, DIFFIO_T15p
F10IO, DIFFIO_T14n, (DQ3T)/(DQ3T)/(DQ5T)
E11IO, DIFFIO_T14p E8IO, DIFFIO_T13n E10IO, DIFFIO_T13p
E7IO, DIFFIO_T12n, (DQ3T)/(DQ3T)/(DQ5T)
A7IO, DIFFIO_T12p G10IO, DIFFIO_T11n
G11IO, DIFFIO_T11p, (DATA5), (DQ3T)/(DQ3T)/(DQ5T)
B7IO, DIFFIO_T10n B3IO, DIFFIO_T10p J10IO, DIFFIO_T9n F8IO, DIFFIO_T9p F7IO, VREFB8N2G12IO, DIFFIO_T8n
A6IO, DIFFIO_T8p, (DATA6), (DQ3T)/(DQ3T)/(DQ5T)B6IO, DIFFIO_T7n, (DATA7), (DQ3T)/(DQ3T)/(DQ5T)
C11IO, DIFFIO_T7p
H10IO
G8IO, DIFFIO_T6n, (DQ3T)/(DQ3T)/(DQ5T)
C9IO, DIFFIO_T6p, (DATA8)
D9IO, DIFFIO_T5n, (DATA9), (DM 3T/BWS#3T)/(DM 3T1/BWS#3T1)/(DM 5T3/BWS#5T3)
A8IO, DIFFIO_T5p, (DQ1T)/_/_
C8IO, (DQ1T)/_/_
D8IO, DIFFIO_T4n, (DATA10), (DQ1T)/_/_
C7IO, DIFFIO_T4p, (DATA11)
D7IO, VREFB8N3G9IO, (DQ1T)/_/_
D6IO, DIFFIO_T3n, (DQ1T)/_/_
A4IO, DIFFIO_T3p, (DATA12), (DQS1T/CQ1T#,CDPCLK7)/(DQS1T/CQ1T#,CDPCLK7)/(DQS1T/CQ1T#,CDPCLK7)
B4IO, DIFFIO_T2n, (DQ1T)/_/_A3IO, DIFFIO_T2p, (DQ1T)/_/_
C6IO, DIFFIO_T1n
H8IO, DIFFIO_T1p, (DQ1T)/_/_
C4IO, (DM 1T)/_/_D4IO, PLL3_CLKOUTn C5IO, PLL3_CLKOUTp
D5IO
C3U8H
EP3C40F780C8N
TMS CONF_DONE DCLK TCK nSTATUS
TDI
nCONFIG
TDO U_FPGA_Power FPGA_NonIO.SchDoc
CLK0, DIFFCLK_0p
J2CLK1, DIFFCLK_0n J1CLK2, DIFFCLK_1p Y2CLK3, DIFFCLK_1n Y1CLK15, DIFFCLK_6p AG14CLK14, DIFFCLK_6n AH14CLK13, DIFFCLK_7p AG15CLK12, DIFFCLK_7n AH15CLK7, DIFFCLK_3n Y28CLK6, DIFFCLK_3p Y27CLK5, DIFFCLK_2n J28CLK4, DIFFCLK_2p J27CLK8, DIFFCLK_5n A15CLK9, DIFFCLK_5p B15CLK10, DIFFCLK_4n A14CLK11, DIFFCLK_4p B14U8I EP3C40F780C8N
PLL1PLL2PLL3PLL4
FPGA_CLK DA U_FPGA _CLK1REF_CLKb
DA U_FPGA _CLK1REF_CLKa FPGA_CLK AVOID PIN AVOID PIN FPGA_DONE
E_CRS VGA_RED0RELAY3
SRAM 2_D12SRAM 2_D14
BUZZER
TFT_DB17
USB_FLAGB USB_FLAGA EXTEND_A11DIP3DIP0
BUS_NOE
EXTEND_A3
LED2_G EXTEND_A13EXTEND_A1ISP176X_RST
P1_PWM VGA_RED1VGA_BLUE4BUS_A19SRAM 1_D13RELAY0VGA_RED4
RELAY1VGA_HSYNC
BUS_A3
BUS_A5
BUS_A18BUS_A6
SRAM 2_D2
VGA_GREEN0CODECSPI_CLK
SRAM 2_A17BUS_FLASH_NBUSY
SRAM 1_NOE SRAM 2_D11E_TXD1E_RESETB_E SRAM 1_A1ADC_DIN
E_TXEN E_TXD0E_TXD3VGA_BLUE6CODECI2S_M CLK SRAM 1_NBHE SRAM 2_D1SRAM 1_D6SRAM 1_D8IO24
E_RXD3E_TXD2VGA_VSYNC SRAM 2_A16SRAM 1_D7IO22
IO20
VGA_BLUE2SRAM 2_D0SRAM 1_A14BUS_A7SRAM 1_NWE SRAM 1_A6IO4SRAM 2_A11BUS_A10
IO26
BUS_D30BUS_D1BUS_D4BUS_D3
SDA EXTEND_A33BUS_D26BUS_D5
SRAM 1_A4BUS_NBE1
TFT_TSC_DIN SRAM 2_A2SRAM 2_NBLE
SRAM 2_D13
SRAM 2_NOE
SRAM 2_NBHE
SRAM 1_D2E_RXDV E_M DIO SRAM 1_A3
SRAM 1_NCS SRAM 2_D3
USB_WR_N EXTEND_A18485_RX_EN P3_PWM VGA_CLK M IDI_RX
P2_PWM
E_RXD0RS232_RTS ADC_CS RS232_RX NC1NC2
NC3
NC4
NC5
NC6
NC7VGA_GREEN1BUS_A4
SW4
EXTEND_A45EXTEND_A40
IO35
SPAREIO1SPAREIO2EXTEND_A0
TFT_DB2IR38KRX USB_D3TFT_DB13
BUS_SDRAM _NCS TFT_TSC_DOUT LED6_G
LED5_G
LED6_B BUS_D21SW2EXTEND_A29EXTEND_A28
EXTEND_A39EXTEND_A16SW3EXTEND_A41
CODECI2S_DIN
SPAREIO3EXTEND_A8SPAREIO4BUS_ISP176X_NCS IR38KTX
TFT_TSC_CLK TFT_DB15TFT_TSC_IRQ_N
LED5_B
USB_RD_N LED4_B
LED4_R
LED5_R BUS_D23DAU_SPI_DOUT BUS_D22
EXTEND_A27EXTEND_A22EXTEND_A30DIP7
DIP6
LED2_R DIP1LED3_G
SDPROTECT USB_FIFOADR0USB_FIFOADR2NEXUS_TDO TFT_DB10
BUS_SDRAM _NRAS USB_FIFOADR1BUS_SDRAM _NCAS
BUS_NBE2LED7_G EXTEND_A26SCL
EXTEND_A31EXTEND_A38
EXTEND_A15KBDATA
LED2_B LED3_B BUS_A17
SDDETECT TFT_DB1USB_SLOE
NEXUS_TDI
USB_FLAGC SDDAT0LED4_G LED7_B
TFT_TSC_CS_N EXTEND_A14EXTEND_A24EXTEND_A23EXTEND_A21CODECI2S_DOUT KBCLOCK DIP5M OUSECLOCK
DIP2TFT_DB7SDCLK
DAU_SPI_CLK USB_IFCLK USB_VBUS TFT_DB12
NEXUS_TMS DAU_SPI_SEL
BUS_A12BUS_A15USB_D4EXTEND_A10EXTEND_A20
SPDIF_IN EXTEND_A17EXTEND_A9EXTEND_A7EXTEND_A2BUS_ISP176X_DACK CODECI2S_WCLK
TFT_DB0BUS_ISP176X_NIRQ BUS_A1
TFT_DB16USB_D0
TFT_RS TFT_DB14TFT_RD TFT_WR USB_INT_N SDDAT1TFT_BLIGHT DAU_SPI_M ODE EXTEND_A19CODECSPI_DOUT EXTEND_A12EXTEND_A6DIP4
DAU_RESET_SW TFT_DB3TFT_CS
USB_D2USB_D6
USB_FLAGD_CS_N DAU_SPI_DIN USB_RESET_N TFT_DB4SPDIF_OUT EXTEND_A5EXTEND_A4TFT_DB6TFT_DB5
BUS_ISP176X_DREQ USB_D5USB_D7USB_PKTEND BUS_A16TFT_DB11E_RXER RELAY2
E_M DC
485_TXD
VGA_GREEN3VGA_RED7BUS_A2
DAC_CLK
SRAM 1_A15SRAM 1_D4
BUS_FLASH_NCS
E_RXD1RS232_TX
M IDI_TX
VGA_GREEN4VGA_GREEN2VGA_BLUE5
BUS_SRAM _NCS SRAM 1_A2SRAM 1_NBLE
SRAM 1_D15SRAM 1_D0
SRAM 1_D14
SRAM 1_D10SRAM 2_D10
SRAM 1_D11SRAM 2_D7E_RXD2VGA_GREEN7
VGA_GREEN5
485_RXD
VGA_BLUE7SRAM 1_A17
SRAM 2_A0
SRAM 2_A15SRAM 2_A3
SRAM 2_D15
SRAM 1_D1SRAM 2_D5
SRAM 2_D6
SRAM 1_D9DAC_CS
VGA_GREEN6P0_PWM
VGA_RED2
VGA_BLUE1ADC_CLK SRAM 1_D3SRAM 2_A1SRAM 2_A4
SRAM 2_D9SRAM 2_D8BUS_D24
BUS_NWE VGA_RED5VGA_RED6SRAM 1_D12VGA_BLUE3SRAM 1_A0E_RXC
SRAM 1_D5BUS_D7
SRAM 1_A18SRAM 1_A7485_TX_EN VGA_RED3VGA_BLUE0SRAM 1_A16SRAM 1_A12
BUS_A21BUS_A8E_COL
IO18E_TXC SRAM 2_NCS SRAM 2_A5SRAM 1_A13BUS_A20RS232_CTS IO27DAC_DIN IO25
IO21CODECI2S_BCLK SRAM 1_A5BUS_A9BUS_D8
BUS_A14
IO12IO19ADC_DOUT IO14
IO16IO23IO6IO10SRAM 1_A11SRAM 2_A18SRAM 2_A14BUS_A11
SRAM 2_A8
BUS_A13IO13
IO17SW0
IO8IO11IO2IO15
SRAM 2_NWE BUS_A22SRAM 2_A12SRAM 2_A6SRAM 1_A8BUS_A24
SRAM 2_A10IO5
IO0
SRAM 2_A13BUS_D0
IO29
BUS_FLASH_NRESET
BUS_D31BUS_D15BUS_D14BUS_D2IO31LED0_R LED0_B IO3IO7
IO1SRAM 2_A7
SRAM 1_A10BUS_D11BUS_D12USB_READY BUS_D16LED1_G
EXTEND_A47IO9BUS_D13BUS_A23
BUS_D17LED0_G ONE_WIRE_DB_PB EXTEND_A48
IO30
IO33
IO28
EXTEND_A46EXTEND_A43
SRAM 2_A9BUS_D29
BUS_D18BUS_D10SRAM 1_A9EXTEND_A44EXTEND_A37LED1_B
IO34EXTEND_A49
IO32
BUS_D27BUS_D28BUS_NBE3
BUS_D19BUS_D9SW1
EXTEND_A42EXTEND_A36CODECSPI_CS
EXTEND_A32LED1_R
EXTEND_A34SDDAT2
BUS_NBE0BUS_D25LED6_R BUS_D20TFT_TSC_BUSY EXTEND_A35
CODECSPI_DIN
EXTEND_A25M OUSEDATA SDDAT3LED3_R
SDCM D TFT_RESET
USB_D1
LED7_R BUS_SDRAM _CKE BUS_D6
SRAM 2_D4FPGA_ID2FPG A_ID = 0x1 (Altera)
HOST_SPARE1
HOST_SPARE1CLK
CS_N DIN DOUT BUSY TFT_INT
TFT_TSC
REF 1
CLK2
2CLK1
3
GND
4CLK35
VDD 6CLK47
CLKOUT 8
U70
CY2305 Zero-delay Buffer
3V3
GND
DB_REF_CLK R213
5R6 1%
EXT INT
PULLDOWN
PULLDNx3.SCHDOC
EXT INT
PULLDOWN
PULLDNx3.SCHDOC
EXT INT
PULLDOWN
PULLDNx3.SCHDOC
EXT INT
PULLDOWN
PULLDNx3.SCHDOC
EXT INT
PULLDOWN
PULLDNx3.SCHDOC
EXT INT
PULLDOWN
PULLDNx3.SCHDOC
EXT INT
PULLDOWN
PULLDNx3.SCHDOC
EXT INT
PULLDOWN
PULLDNx3.SCHDOC
R314
5R6 1%
REF_CLKb
1
12
23
34
45
56
67
78
8
D D
C
C
B
B
A
A
14021/02/20101:34:45 PM FPGA_NonIO.SchDoc
Project Title Size:
Date:File:Revision:Sheet of Time:A3
Sheet Title User FPGA Pwr and Programming
Assy:81
NB3000AL - Altera
D-820-0053
Altium Limited 3 Minna Close Belrose NSW 2085Australia
TMS
CONF_DONE DCLK
TCK
TDI nCONFIG
TDO
1V2
GND
3V3
GND
nSTATUS
VCCA_PLL2VCCA_PLL3VCCA_PLL4
VCCA_PLL11V2
GND
i FPGACONF
i FPGACONF i FPGACONF i FPGACONF i FPGACONF
i FPGACONF i FPGACONF i
FPGACONF GND
nSTATUS
M6DCLK P3nCONFIG P4TDI P7TCK P5TMS P8TDO P6nCE
R8CONF_DONE P24MSEL0
N22
MSEL1P23MSEL2M22MSEL3
P22U8J
EP3C40F780C8N
VCCINT K9
VCCINT K11
VCCINT L16
VCCINT K17
VCCINT K19
VCCINT L10
VCCINT L12
VCCINT L14
VCCINT L18
VCCINT N20
VCCINT M11
VCCINT M13
VCCINT M15
VCCINT M17
VCCINT M19
VCCINT N10
VCCINT N12
VCCINT N14
VCCINT N16
VCCINT N18
VCCINT P9
VCCINT P11
VCCINT P13
VCCINT P15
VCCINT P17
VCCINT P19
VCCINT R10
VCCINT R12
VCCINT R14
VCCINT R16
VCCINT R18
VCCINT R20
VCCINT T11
VCCINT T13
VCCINT T15
VCCINT T17
VCCINT T19
VCCINT U10
VCCINT U12
VCCINT U14
VCCINT U16
VCCINT U18
VCCINT V11
VCCINT V15
VCCINT V17
VCCINT V19
VCCINT V13
VCCINT W12
VCCINT W14
VCCINT W18
VCCIO1B1VCCIO1H1VCCIO1K5VCCIO1K8VCCIO1N1VCCIO1N5VCCIO2
AA1VCCIO2AG1VCCIO2T1VCCIO2T5VCCIO2W7VCCIO2W5VCCIO3AA11VCCIO3AD6VCCIO3AD9VCCIO3AD13VCCIO3AH2VCCIO3AH5VCCIO3AH9VCCIO3AH13VCCIO3AB10VCCIO4AA18VCCIO4AD16VCCIO4AD20VCCIO4AD23VCCIO4AH16VCCIO4AH20VCCIO4AH24VCCIO4AH27VCCIO4Y16VCCIO5AA28VCCIO5AG28VCCIO5T24VCCIO5T28VCCIO5U21VCCIO5W24VCCIO6B28VCCIO6H28VCCIO6K24VCCIO6L21VCCIO6N24VCCIO6N28VCCIO7A16VCCIO7A20VCCIO7A24VCCIO7A27VCCIO7E16VCCIO7E20VCCIO7E23VCCIO7H18VCCIO7J15VCCIO8A2VCCIO8A5VCCIO8A9VCCIO8A13VCCIO8E6VCCIO8E9VCCIO8E13VCCIO8H11VCCIO8
J13U8K
EP3C40F780C8N
GND K10GND K12GND K14GND K18GND K20GND L11GND L15GND L17GND L19GND L9GND M10GND M12GND M14GND M16GND M18GND N11GND N13GND N15GND N17GND N19GND P10GND P12GND P14GND P16GND P18GND P20GND R11GND R13GND R15GND R17GND R19GND R9GND T10GND T12GND T14GND T16GND T18GND U11GND U13GND U15GND U17GND U19GND V10GND V12GND V14GND V18GND W11GND W15GND W17GND W19GND AA2GND AA27GND AC6GND AC9GND AC13GND AC16GND AC20GND AC23GND AF1GND AF28GND AG2GND AG5GND AG9GND AG13GND AG16GND AG20GND AG24GND AG27GND B2GND B5GND B9GND B13GND B16GND B20GND B24GND B27GND C1GND C28GND F6GND F9GND F13GND F16GND F20GND F23GND H2GND H27GND J11GND J18GND K6GND K16GND K23GND L13GND M20GND N2GND N6GND N9GND N23GND N27GND T2GND T6GND T20GND T23GND T27GND U9GND V16GND W6GND W13GND W23GND Y11GND Y18U8L
EP3C40F780C8N
VCCD_PLL3J9
GNDA3H9VCCA3
J8VCCA1
Y8GNDA1AA9VCCD_PLL1Y9
VCCD_PLL4
Y20
GNDA4
AA20
VCCA4
Y21VCCA2
J21GNDA2H20
VCCD_PLL2J20U8M
EP3C40F780C8N
GND GND GND GND GND
PLL VCC Decoupling
2V5
VCCA_PLL2
VCCA_PLL3
VCCA_PLL4
VCCA_PLL1
2V5
2V5
2V5
GND GND GND
i PLL
i PLL
i PLL
i PLL
L4
1K at 100MHz 300mA
L51K at 100MHz 300mA
L61K at 100MHz 300mA
L71K at 100MHz 300mA
C343
2.2uF 6.3V
C347
2.2uF 6.3V C351
2.2uF 6.3V
C355
2.2uF 6.3V C344
0.1uF 16V
C348
0.1uF 16V
C352
0.1uF 16V
C356
0.1uF 16V
C34910nF 16V
C35310nF 16V
C35710nF 16V
C34510nF 16V
C3461nF 50V
C3501nF 50V
C3541nF 50V
C3581nF 50V
FPGA开发板
FPGA开发板 FPGA开发板ALTERA FPGA是世界上十几家生产CPLD/FPGA的公司中最大的可编程逻辑器件供应商之一，生产的FPGA产品有：FLEX6000/8000/10K、APEX20K、ACEX1K、APEXⅡ、Mercury、Excalibur、Cyclone、Stratix、CycloneⅡ和StratixⅡ等系列。 Altera的FPGA器件采用钢铝布线的先进CMOS技术，具有非常低的功耗和相当高的速度，而且采用连续式互连结构，提供快速的、连续的信号延时。Altera器件密度从300门到400万门，能很容易地集成现有的各种逻辑器件，高集成度的FPGA提供更高的系统性能，更高的可靠性，更高的性能价格比。 Altera Cyclone系列FPGA是Altera公司2003年9月份推出的，基于1.5V，0.13μm 工艺，Cyclone 是一个性价比很高的FPGA系列。其中EP1C3T144是Cyclone系列中的一员，共有2910逻辑单元，59904RAM bits，1个PLLs，最多有104个用户I/O，可以说这款FPGA的资源非常丰富，足够满足大型设计的需要。 本公司因此特推出Cyclone EP1C3T144C8 FPGA开发板，该开发板功能强大，接口丰富，可做大型综合实验。 FPGA开发板硬件资源主要有：
1、Altera EP1C3T144C8 FPGA芯片 2、Altera 串行配置芯片EPCS1 3、DAC0832芯片 4、ADC0809芯片 5、液晶接口 6、TP3057PCM编解码芯片 7、八位高亮数码管 8、八位拨码开关 9、4×4阵列键盘 10、4个复位轻触按键 11、9个高亮发光二极管（红、绿、黄色各三灯） 12、双刀双掷继电器 13、异步通信串口（UART） 14、双有源晶振（24MHz和32.768MHz） 15、5V，3.3V，1.5V电源管理系统 FPGA开发板带以下DEMO程序： 1、FPGA实现流水灯实验 2、FPGA实现电子钟实验 3、FPGA实现串口发送实验 4、FPGA实现串口接收、点阵显示实验 5、FPGA实现矩阵键盘和点阵显示（实时扫描方式） 6、FPGA实现矩阵键盘和数码管显示（延时扫描方式） 7、FPGA实现AD转换、数码显示和拨码选择通道实验 8、FPGA实现DA转换，产生锯齿、三角、正弦波；拨码开关选择波形
ARM+FPGA开发板规格书
2014
Revision History
阅前须知 版权声明 本手册版权归属广州创龙电子科技有限公司所有，非经书面同意，任何单位及个人不得擅自摘录本手册部分或全部，违者我们将追究其法律责任。本文档一切解释权归广州创龙电子科技有限公司所有。 ?2014-2018Guangzhou TronlongElectronicTechnologyCo.,Ltd. All rights reserved. 公司简介 广州创龙电子科技有限公司（简称“广州创龙” ，英文简称"Tronlong"），是杰出的 嵌入式方案商，专业提供嵌入式开发平台工具及嵌入式软硬件定制设计及技术支持等服务，专注于DSP+ARM+FPGA 三核系统方案开发，和国内诸多著名企业、研究所和高校有密切的技术合作，如富士康、威胜集团、中国科学院、清华大学等国内龙头企业和院校。 TI 嵌入式处理业务拓展经理ZhengXiaolong 指出：“Tronlong 是国内研究OMAP-L138 最深入的企业之一，Tronlong 推出OMAP-L138+Spartan-6三核数据采集处理显示解决方案，我们深感振奋，它将加速客户新产品的上市进程，带来更高的投资回报率，使得新老客户大大受益。” 经过近几年的发展，创龙产品已占据相关市场主导地位，特别是在电力、通信、工控、 音视频处理等数据采集处理行业广泛应用。创龙致力于让客户的产品快速上市、缩短开发周期、降低研发成本。选择创龙，您将得到强大的技术支持和完美的服务体验。 产品保修 广州创龙所有产品保修期为一年，保修期内由于产品质量原因引起的，经鉴定系非 人为因素造成的产品损坏问题，由广州创龙免费维修或者更换。 更多帮助
基于DE2-115开发板的FPGA入门设计实验
基于DE2-115开发板的FPGA入门设计实验 1、Lab1: 4位加法器、减法器的设计 1.1 摘要 在文件add_sub里面的工程文件operation_4.v为顶层文件，该顶层文件包含了三个子模块，分别为数码管显示模块，4位带进位的二进制加法器模块和4位带借位的二进制减法器模块，最后通过DE2-115开发板显示实验结果。 1.2 程序 1）add_4bits.v 加法器 module adder_4bits ( input clk, input rst_n, input [3:0] x, input [3:0] y, output reg [3:0] sum, output reg carry_out //溢出位 ); always@(posedge clk or negedge rst_n) begin if(!rst_n)
{carry_out, sum} <= 0; else {carry_out, sum} = x + y; end endmodule 2）substractor_4bits.v减法器module subtractor_4bits ( input clk, input rst_n, input [3:0] x, input [3:0] y, output r eg [3:0] sub, output r eg borrow_out ); always@(posedge clk or negedge rst_n) begin if(!rst_n) {borrow_out, sub} <= 0; else begin
if(x >= y) {borrow_out, sub} = {1'b0, x - y}; else {borrow_out, sub} = {1'b1, x - y}; end end endmodule 3)seg7_lut.v 数码管显示译码模块 module Seg7_lut ( input [3:0] iDIG, output r eg [6:0] oSEG ); always @(iDIG) begin case(iDIG) 4'h1: oSEG = 7'b1111001; // ---t---- 4'h2: oSEG = 7'b0100100; // | | 4'h3: oSEG = 7'b0110000; // lt rt 4'h4: oSEG = 7'b0011001; // | | 4'h5: oSEG = 7'b0010010; // ---m---- 4'h6: oSEG = 7'b0000010; // | |
FPGA开发板EP1C12用户手册(一版)
使用手册
目 录 第一章综述 (1) EP1C12核心板资源介绍 (1) FPGA开发板资源介绍 (2) 第二章 系统模块功能介绍 (5) EP1C12核心板模块说明 EP1C12F324C8芯片说明 (7) NOR FLASH模块说明 (8) SRAM模块说明 (9) FPGA接口I/O说明 (10) 调试接口JTAG、AS说明 (11) 其它功能模块 (12) EP1C12核心板使用注意事项 (15) FPGA开发平台模块说明 液晶显示模块 (17) RTC实时时钟模块 (19) USB接口模块 (19) 音频CODEC接口模块 (20) EEPROM存储模块 (21) 数字温度传感器模块 (22) 其它功能模块 (23) FPGA开发平台使用注意事项 (24) 附表一 核心板载资源与FPGAEP1C12I/O接口对照表 (25) 附表二 EP1C12与开发板硬件资源I/O接口对照表 (30)
第一章综述 FPGA开发来台是根据现代电子发展的方向，集EDA和SOPC系统开发为一体的综合性实验开发系统，除了满足高校专、本科生和研究生的SOPC教学实验开发之外，也是电子设计和电子项目开发的理想工具。整个开发系统由核心板EP1C12、SOPC开发平台和扩展板构成，根据用户不同的需求配置成不同的开发系统。 EP1C12核心板 EP1C12核心板为基于Altera Cyclone器件的嵌入式系统开发提供了一个很好的硬件平台，它可以为开发人员提供以下资源： 1主芯片采用Altera Cyclone器件EP1C12F324C8 2EPCS4I8配置芯片 34个用户自定义按键 44个用户自定义LED 51个七段码LED 6标准AS编程接口和JTAG调试接口 750MHz高精度时钟源 8三个高密度扩展接口 9系统上电复位电路 10支持+5V直接输入，板上电源管理模块 系统主芯片采用324引脚、BGA封装的E1C12 FPGA，它拥有12060个LE，52个M4K 片上RAM（共计239616bits），2个高性能PLL以及多达249个用户自定义IO。同时，系统还可以根据用户不同的设计需求来更换其它不同系列的核心板，如： EP1C6、EP2C20、EP3C25等。所以，不管从性能上而言，还是从系统灵活性上而言，无论您是初学者，还是资深硬件工程师，它都会成为您的好帮手。
Altium公司的FPGA开发板的原理图
1 12 23 34 45 56 67 78 8 D D C C B B A A 1 02 1/02/20101:34:44 PM NB3000_Top.SchDoc Project Title Size: Date:File:Revision:Sheet of Time:A2Sheet Title NB3000 Top Level Assy:81 NB3000AL - Altera D-820-0053 Altium Limited 3 Minna Close Belrose NSW 2085Australia PSU PSU.SchDoc SRAM SRA M1 SRAM_256Kx 16_TSOP44 STATUS_LED U SE R _STATUS_L E DS DB_LEDS_0603 SRAM1 SRAM2 MEM_COMMON DAU_RESET_SW BUZZER ONE_WIRE_DB_PB SW DIP USERIO EXT_A RS232 KEYBOARD MOUSE TFT_IO DB_PROGRAM STATUS_LED USER_LEDS RELAY I2C CODEC VGA ETH DBSD DBUSB PWM SPDIF DAC ADC RS485 MIDI DB_JTAG DB_CLOCKS DB_SPI ISP176X PROTOTYPE SPAREIO TFT_TSC FPGA _USE R FPGA.SCHDOC INT EXT V IDE O_OU T VGA_OUT.SCHDOC CON CON_VGA CON_VGA_DB15 HOST_JTAG LED1LED2 1WID DB_PROGRAM CLK_PLL FLASH_BOOT HOSTUSB SRAM RTC SD HOST_AUDIO DB_JTAG DB_CLOCKS FLASH_USER DB_SPI PB_A EXTSPI FLASH_GOLDEN DIAGCOMMS FPGA _HOST HOST_FPGA.SchDoc HOST_JTAG HOST_JTA G HOST_JTAG.SchDoc INT EXT R S232 RS232_HIN232 EXT INT KE Y BOA RD PC_PS2 RS232# KBD#MSE# RS232 KEYBOARD EXT INT MOUSE PC_PS2 DIPSW DB_RESET CON CON_DBU SB CON_MINI_USBB_RA_KME04-USBMU03A01-1 DBUSB DBUSB# CON CON_DBSD CON_SD_KSDC012551 DBSD EXT INT DBU SB_TX RX USB_CY7C68001-56LFC.SchDoc INT EXT E TH Ethernet_RTL8201CL.SchDoc ETH CLK_PLL CL K_PL L CLK_ICS307-02_PLL 1WID NB_ID 1WB_DS2502_ID CON CON_HOST_USB CON_MINI_USBB_RA_KME04-USBMU03A01-1 TFT_TSC TFT_TOUCH L CDTFT TSC_XPT2046.SchDoc TFT_TSC TFT_IO CON CON_MOU SE CON_PS2PORT_MINIDIN6F_BLACK INT CON PDA _SW ITCHE S SW_PB_SPNOx5_SMD INT TE ST_RE SE T SW_RESET_SPNO CON USERPOWER CON_IO CON_USER_20WBOXHDRRAMx 2 UIO BUZZER CODEC_AUD AUDIO SPK_L SPK_R HOST_AUDIO AIN AOUT_PBA A UDIO_A MP AUDIO_AMP_NB2C PB_AIN AUDIO SPK_L USER_LEDS CON U SE R _L E D LED_RGB_SMDx 8.SCHDOC USER_LEDS VGA# VGA SW SRAM SRA M2 SRAM_256Kx 16_TSOP44 RELAYS CON R E L AY RELAY_X4_IM03GR RELAY PWM CON PW M PWM_5.8A_30V_X4 PWM 1V21V82V53V35V0 PBPOW E R 1V21V82V53V35V0 I2C DIGITAL CODEC_AUD AIN A UDIO_CODE C Audio_Codec.SchDoc CODEC SPK_L SPK_R CON_SPE AKE R S CON_EXT_SPK SPK_R PB_AOUT PBIO LED1LED2 LED1_EXT LED2_EXT L E D_HOST LED_RGB_SMDx 2 SPDIF CON_SPDIF CON_SPDIF_INOUT_A SPDIF SPI CON DAC DAC_DAC084S085_SPI SPI CON A DC ADC_ADC084S021_SPI DAC ADC CON CON_E TH CON_ETHERNET_RJ45_LEDS ETH# TFT_IO TFT_TOUCH CON_L CDTFT CON_FFC40_LCDTFT.SCHDOC CON CON_RE L AY CON_RELAYx 4_KMRJIO3_5MM_12WAY CON CON_RS232 CON_RS232DCE_DB9_TH BOOT_FLASH MOUNTS Mounts.SchDoc INT EXT R S485 RS485_ISL8491 CON_PSU PWJACK+SWITCH.SchDoc HOST_USB HOSTUSB# EXT INT HOST_USB_TXR X USB_CY7C68001-56LFC.SchDoc VBATT CON_BA TT CON_BATT_COIN VBATT VBATT RTC R T CL OCK CLK_PCF2123_RTC HOST_RTC USERPOWER U SE R _POW E R USERPWR.SCHDOC CON CON_HOST_SD CON_SD_KSDC012551 RS485#CON CON_RS485 CON_RS485_RJ45 INT EXT MIDI INTE RFA CE MIDI_FULL CON CON_MIDI CON_MIDI_DIN5 MIDI# MIDI RS485HOST_AUDIO PBCTRL DB_PROGRAM HOST_JTAG HOST_ID HOST_CLK HOST_SRAM HOST_LED1 HOST_LED2 HOST_SD DB_SRAM1 DB_SRAM2 DB_MEM DB_STATUS ADC# RELAYS# PWM# DAC# UIO_PWR DB_JTAG DB_CLOCKS PB_SPI USER_FLASH DB_SPI EXT ONE_WIRE_DB_PB AIN I2C SPI AOUT CTRL PBPOWER CON_PE R IPHE R AL _BRD PBCON USER_LEDS SW_PDA SPARE_IO CON_L E DKBD CON_NB3000_LEDKB SERFLASH SYSBOOT FLASH_M25PX0_SPI_8Mbit GOLD_FLASH SERFLASH GOL DE N FLASH_M25PX0_SPI_8Mbit FLASH U SE R _FL A SH FLASHSPI_M25PX0 INT SW _DIP8_SM T SW_DIP8_SMT CON CON_KE YBOAR D CON_PS2PORT_MINIDIN6F_BLACK CON CON_USB1 CON_USBA_RA_UPRIGHT LEDS# ATE DIAGCOMMS A TE INTE R FACE CON_NB3000_ATE_INTF ISP176X PORT1 PORT2 PORT3 U SB_U SE RHOST USB_ISP1760 ATE VGA#SPDIF UIO ADC#DAC#AUDIO HOST_JTAG PWM RS232#RS485#KBD#MSE#MIDI# HOST_ID A TE INTE R FACE VGA#SPDIF UIO ADC# DAC# AUDIO HOST_JTAG PWM# RS232#RS485#KBD#MSE#MOUSE ISP176X PORT1 PORT2 PORT3 PROTOTYPE U SE R _PROTOTYPE _AR E A PROTOTYPE_A PROTOTYPE CON CON_AU DIO CON_AUDIO_AC99_NOMIC.SCHDOC DIAGCOMMS MIDI# HOST_ID SW# SPAREIO MEM COMM ON_ME M OR Y CommonMemory CON CON_ADC CON_ADCx 4_KMRJIO3_5MM_6WAY CON CON_DAC CON_DACx 4_KMRJIO3_5MM_6WAY CON CON_PW M CON_PWMx4_KMRJIO3_5MM_6WAY CON CON_USB2 CON_USBA_RA_UPRIGHT CON CON_USB3 CON_USBA_RA_UPRIGHT SRAM SRA M_HOST SRAM_256Kx 16_TSOP44 TFT_TOUCH INT U SB_CL K OSC_24MHZ.SchDoc HOST_USB.XTALIN HOST_USB.XTALOUT CMOSOUT XTALIN XTALOUT OSC DBUSB.XTALIN
基于FPGA开发板的数字钟设计初探
基于FPGA开发板的数字钟设计初探 摘要：本文介绍了基于FPGA开发板的数字钟设计的基本构想，所提供的功能，基本的模块和控制逻 辑。 关键词: 模块，数字钟 1引言 VHDL结合FPGA可以方便地，可重复利用地实现各种设计，本文主要从原理上规划出设计一个数字钟需要的模块和功能逻辑，以便后期使用VHDL和FPGA实现。 2 设计原理 本文打算实现的数字钟向用户提供的功能包括：秒、分、时、日、月显示，闹钟设定，时间校准。鉴于所提供的功能，电路应当包括以下五大模块：控制模块，分频模块，闹钟模块，计时模块和显示模块。控制模块包括了输入部分，用户通过外部按钮选择数字钟工作模式和输入基准时间，闹钟时刻；分频模块主要是给需要的模块提供特定频率的时钟信号；闹钟模块的主要作用是接收并存储用户输入的闹钟时刻，比较当前时刻是否是用户所设定的闹钟时刻，进而决定是否启动闹钟提醒装置（蜂鸣器）；计时模块包括了秒、分、时、日，月计数模块，并提供给显示模块显示输出；显示模块包括数码管及驱动部分，蜂鸣器。 3 电路设计 控制模块主要是一个译码电路，控制系统所处的模式：正常计时显示，时间校准，设定闹钟。 计时模块通过六十进制、二十四进制、三十或三十一进制和十二进制的计数器实现计时。计时模式下利用分频器提供的基准时钟信号实现计时；时间校准模式下，用户输入按钮的脉冲作时钟信号。 分频模块是一个分频器，将系统提供的时钟分频到需要的频率。 闹钟模块在计时模式下利用比较电路检测当前时间，如果是闹钟时刻，则启动蜂鸣器；闹钟模式下，用户通过输入按钮脉冲设定闹钟，闹钟模块记录并存储。 显示模块在计时模式和时间校准模式下由计时模块控制显示，设定闹钟时由闹钟模块控制显示，方便用户设定闹钟，蜂鸣器由闹钟模块控制。
Altera Cyclone III系列FPGA开发板简介
ETL-002 Altera Cyclone III 系列FPGA开发板简介 概述 ETL-002 FPGA开发板是以Altera公司的最新系列Cyclone III中的3C10为主芯片，并提供了极为丰富的芯片外围接口资源以及下载线，数据线以及资料光盘等。除了这些硬件外，我们还提供了十多个接口实验，并公开了电路原理图和实验的Verilog源代码，以便于大家对照学习，并可以在该开发板上进行二次开发。
单板描述 主芯片EP3C10提供了10320个逻辑单元（LE），46块SRAM（每块9K bits）, 23个18*18的乘法器。开发板自带USB供电电路：您只需将USB线插上您的USB端口，无需外接＋5V直流电源，开发板即可工作。开发板同时支持AS模式下载和JTAG模式下载。程序固化既可通过JTAG口也可直接对板上的FLASH进行编程。 丰富的外围接口可满足常用的外设的人机交互，我们还将剩下未用的40个用户I/O引脚全部引出，使得您可以通过这些信号对本开发板进行电路扩展。这些接口主要包括： PS2鼠标接口：可以将PS2鼠标的任何移动的信息反应在数码管上 PS2键盘接口：可以将PS2键盘上的任意按键以16进制的信息反应在数码管上 VGA显示器接口：可以将FPGA产生的信息反映在VGA显示器上。开发板自带了动态彩条显示的功能 双串口接口：可以与任何的串口设备相接。开发板自带的演示程序是将PC上的超级终端中输入的任何信息返回PC 4位数码管：可以实时显示任何的数字信息。开发板自带的演示程序实时地显示分钟和秒钟的信息。 4位LED灯：用于指示状态。开发板自带了跑马灯实验。 4位按键开关：可用于复位等作用。 4位拨码开关：可用于电路的选择作用
FPGA开发板实验手册2017
FPGA开发板实验指导书(2017) 第一章注意事项 工程未使用到的IO请设置为三态 所有程序请一定将未定义的引脚设为三态输入(As input tri-stated)，一定不能将未使用的引脚设置为输出(As outputs driving ground)，否则可能会造成核心板主芯片及存储芯片冲突损坏！或是造成其它意想不到的损坏！ 如何设置未使用的引脚为三态？ 答：Quartus--菜单Assignments--Device---Device and Pin Options---Unused Pins---Reserve all unused pins==改为As input tri-stated 每个例程下载前都养成习惯，先查下设置对不对，不对的话，改好，要重新编译一下。 如果程序下载进去，数码管、LED灯都乱亮了，那肯定是没设置好，请严格遵照上面的修改好，重新编译。 1.1JTAG及AS的插拔安全 开发板带有JTAG和AS下载接口，严禁带电拔抽JTAG及AS下载线！带电操作容易对FPGA芯片的内部配置部分电路造成致命损坏，损坏后是无法修复的！请牢记一条：插拔下载线时必须断电！平时建议大家使用JTAG下载插口，如图1.1所示，红色框的为JTAG下载口。AS插口在必要时再使用。 图1.1 下载接口JTAG和AS 1.2外接电源 开发板套装里面附带标准5V/2A电源一条，5V输入，内正外负。建议使用我们标配电源，如果使用其它电源，请您一定确认输出电压是否为5V，以免由于电压不同造成开发板损坏！ 核心板和接口板均设有5V电源插口，位置在PCB左上角。如图1.2所示：使用开发板时，只用随便接一个插口即可。不必要核心板和接口板都插电源。因为电源走线内部是相通的。 注意图1.2蓝白色那个按键就是全板电源总开关，按下后即可接通电源，这时底板与核心板左上角均有电源指示灯LED点亮。正常情况下：板载的流水灯程序就运行了。
手把手教你学FPGA 设计思想篇
泽屹电子 手把手教你学FPGA 设计思想篇 阿东团队编著
手把手教你学FPGA 设计思想篇
目录 写在前面...................................................................................................................................... - 4 - 1 什么是设计思想.................................................................................................................... - 6 - 2 概述........................................................................................................................................ - 6 - 3 代码简单化............................................................................................................................ - 6 - 4 注释层次化............................................................................................................................ - 7 - 5 交互界面清晰化.................................................................................................................... - 7 - 6 模块划分最优化.................................................................................................................... - 7 - 7 代码工具化............................................................................................................................ - 8 - 8 方案精细化............................................................................................................................ - 8 - 9 资源合理化............................................................................................................................ - 9 - 10 时序流水化.......................................................................................................................... - 9 - 11 资源优化方法.................................................................................................................... - 10 - 12 代码自检............................................................................................................................ - 10 - 13 通用电路BB化.................................................................................................................. - 10 -
[整理]FPGA开发板使用说明书.
目录 第一章综述 (1) 第二章系统模块 (2) 第三章软件的介绍 (11) 第四章USB 电缆的安装与使用 (28)
第一章综述 THSOPC-3型FPGA开发板是根据现代电子发展的方向，集EDA和SOPC系统开发为一体的综合性实验开发板，除了满足高校专、本科生和研究生的SOPC教学实验开发之外，也是电子设计和电子项目开发的理想工具。 一、实用范围： ●自主创新应用开发； ●单片机与FPGA联合开发； ●IC设计硬件仿真； ●科研项目硬件验证与开发； ●高速高档自主知识产权电子产品开发； ●毕业设计平台； ●研究生课题开发； ●电子设计竞赛培训； ●现代DSP开发应用； ●针对各类CPU IP核的片上系统开发； ●DSP Biulder系统设计。 二、硬件配置： THSOPC-3型FPGA开发板基于Altera Cyclone II 器件的嵌入式系统开发提供了一个很好的硬件平台，它可以为开发人员提供以下资源： ●支持+5V 电源适配器直接输入或者USB接口供电，5V、3.3V、1.2V混合电压源； ●FPGACycloneII FPGA EP2C8，40万门，2个锁相环； ●isp单片机AT89S8253。isp单片机AT89S8253及开发编程工具，MCS51兼容，12KB isp可编程Flash ROM，2KB ispEEPROM，都是10万次烧写周期；2.7-5.5V工作电压；0-24MHz工作时钟；可编程看门狗；增强型SPI串口，9个中断源等。此单片机可与FPGA联合开发，十分符合实现当今电子设计竞赛项目的功能与指标实现； ●EPM3032 CPLD； ● 4 Mbits 的EPCS4 配置芯片； ●512KB高速SRAM； ●20MHz 高精度时钟源（可倍频到300MHz）； ● 4 个用户自定义按键； ●8 个用户自定义开关； ●8 个用户自定义LED； ● 2 个七段码LED； ●标准AS 编程接口和JTAG调试接口； ●两个标准2.54mm扩展接口，供用户自由扩展；
FPGA入门系列实验教程——点亮LED
FPGA入门系列实验教程V1.0 前言 目前市场销售FPGA开发板的厂商很多，但大多只提供些简单的代码，没有详尽的文档和教程提供给初学者。经验表明，很多学生在学习FPGA设计技术的过程中，虽然刚开始学习热情很高，但真正坚持下来一直到“学会”的却寥寥无几，除了学生个人毅力的因素外，另外一个更主要的原因就是所选的开发板缺少配套的说明文档和手把手系列的入门教程。原本FPGA的学习门槛相对于单片机来说就高了不少，再加上缺少手把手系列教程资料，这就给初学者学习FPGA增添了更多的困难，很多初学者因为找不到入门的方法而渐渐失去了学习FPGA的兴趣和信心。 作者从接著到系统学习FPGA有两年多的时间了，学习FPGA的时间不长，期间因为没有专业的老师指导，自己摸索学习FPGA走了很多的弯路。有过问题迎刃而解的快乐,也有过苦苦寻求结果和答案的痛苦历程，回想起自己学习FPGA的历程，从开始的茫然，到后来的疯狂看书，购买开发板，在开发板上练习各种FPGA实例，到最后能独立完成项目，一路走来，感受颇多。发觉学习FPGA只要选择正确的方法是有捷径可走的，有很多人学习FPGA很长时间，因为没有找到正确的方法还是停留在入门阶段。 针对现状，作者从初学者的角度出发，结合作者学习FPGA的经验和亲身体会，遵循“宁可啰嗦一点，也不放过细节”的原则编写了详尽的实验教程作为艾米电子工作室开发套件的配套教程使用，主要面向FPGA初学者。FPGA的学习只有通过大量的操作与实践才能很好并快速的掌握。为此本实验教程从点亮LED 灯写起，深入浅出，以图文并茂的方式由易到难地列举了很多实例，采用手把手、Step by Step的方式让初学者以最快的方式掌握FPGA技术的开发流程以及Quartus II软件的使用，从而激起初学者学习FPGA的兴趣。在教程中作者采用“授人以渔”的方式，努力做到不仅讲述怎样进行试验，而且分析为什么这样做，以便初学者深刻理解并快速掌握FPGA的学习方法。 FPGA技术是不断发展变化的，要掌握FPGA技术的精髓，需要设计者在实践中不懈地摸索与积累，逐步提高自己的设计水平，本实验教程试图对初学者起到快速入门的作用。但由于作者学习FPGA时间不长，水平有限，错漏和不严谨之处在所难免，欢迎大家批评指正
FPGA助学板教材-睿智FPGA开发板硬件详解
睿智FPGA助学板硬件详解 开发板套件硬件是保证实验学习的基础，这部分内容主要针对硬件部分做简单描述，可适当阅读或翻查，特别是涉及到硬件接口定义等信息时，了解这部分内容很有必要。同时，可与光盘附带的硬件原理图一并参考使用。 1.睿智FPGA助学板硬件 1.1 总体介绍 图1 助学板硬件实拍图
主硬件资源 1 .主芯片采用ALTERA公司最新四代FPGA CycloneIV系列EP4CE6E22C8N； 2 .板载EPCS4N/EPCS16大容量串行配置芯片，支持JTAG/AS模式； 3. 板载64MbitSDRAM,支持SOPC，NIOSII开发（很多价低的板不带SDRAM，无法支持NIOS SOPC开发） ； 4 .板载50MHz有源晶振，提供系统工作主时钟 ； 5 .采用1117-3.3V稳压芯片，提供3.3V电压输出 ； 6 .采用1117-1.2V稳压芯片，提供FPGA内核电压 ； 7 .采用1117-2.5V稳压芯片，提供PLL电压 ； 8 .精心的去耦设计，采用大量去耦电容； 9. 提供5V直流电源插座； 10. 提供方口USB接口电源插座； 11. 一个系统复位按键Reset，也可做为用户输入按键 ； 12. 自锁按键电源开关 ； 13. LED电源指示灯 ； 14. 精心设计分配的IO资源，所有IO引出,3个扩展接口，通用2.54mm间距，任由您自己扩展；
15．JTAG下载接口对应下载的文件是.SOF，速度快，平常学习推荐使用此接口 ； 16． AS下载接口对应下载的文件是.POF，速度较慢，需要固化程序时使用 。 丰富外设资源 1 .板载4个独立按键，可做按键控制，数字逻辑基础实验等 ； 2 .板载4位LED发光二极管，可做LED控制，数字逻辑基础实验等 ； 3. 板载4位数码管，频率计，秒表 ； 4. 板载4位拨码开关，可做开关控制等实验 ； 5 .设有1X20液晶屏排座，支持LCD1602，LCD12864，TFT液晶屏（不包括LCD，需另购） ； 6 .精密可调电阻，调节液晶背光； 7 .板载1路蜂鸣器，可做发声及音乐实验 ； 8 .PS2接口，可做PS/2键盘实验 ； 9 .板载全新原装进口温度传感器芯片LM75A，可以做温度计实验 ； 10 .RS232串口，可做串口通讯实验 ； 11 .VGA接口，可做显示器实验等 ； 12. I2C串行EEPROM AT24C08，做IIC总线实验 ；
谈谈如何利用FPGA开发板进行ASIC原型开发
谈谈如何利用FPGA开发板进行ASIC原型开发 ASIC设计在尺寸和复杂性上不断增加，现代FPGA的容量和性能的新进展意味着这些设计中的2/3能够使用单个FPGA进行建模。然而，这些设计中仍然保留有1/3(那就是说，所有ASIC设计中的1/9)要求一个基于多个FPGA的原型开发板。 在不太遥远的过去，对ASIC设计团队而言，在这类情况下主要的解决方案就是在内部建立他们自己的定制多个FPGA的原型开发板。然而，今天，使用现成的多个FPGA原型开发板例如，由Synplicity公司的原型开发伙伴生产的开发板与合适的设计工具相结合能够节省数周时间，否则的话将花费几个月的验证时间以及在NRE费用上花费数万美元。 本文首先讨论了ASIC验证能够采用的主要技术。接着，文章考虑了与使用一个现成的产品相比，建立一个定制的多个FPGA的原型开发板的优势和缺陷。最后，论文介绍了目前最先进的用于验证大型设计的分割和综合设计工具，其采用内部开发或现成的多个FPGA 的原型开发板。 可供选择的验证技术今天高端ASIC，例如那些在手机、通讯、图形子系统以及信号处理应用中使用的，经常包含多个CPU和DSP内核，其结合了硬件加速器、外围设备、接口和存储器管理内核。(由于这些讨论的目的，术语ASIC被假设包括了ASSP和SoC器件。)所以，为了满足芯片的市场需求，尽可能早的在设计阶段开发、端口、集成、调试和验证任何嵌入式软件的内容。 ASIC的RTL全功能验证其本身与任何嵌入式软件是ASIC设计过程中最耗费时间和最困难的部分之一。统计表明今天ASIC设计中的70%要求重制。除了费用极其昂贵之外，重制能够引起项目失去其市场空间，这将严重损害公司的声誉和金融底线。 对ASIC设计者开放的三个主要验证选择是仿真，模拟和FPGA原型开发。 *仿真：基于软件的仿真被广泛使用，但即使在一个真正的高端(并且，相对昂贵)的计算机平台运行时，其运行比实际的ASIC硬件慢六到十个数量级，这使得其成为一项极大花费时间并且效率极差的技术。为了提供整个系统的尺寸认识，软件仿真能够典型地达到仅仅几Hz相当的速度(那就是，设计的系统时钟相对真实时间每秒钟的几个周期)。实际上，
Cyclone V开发板
Cyclone V开发板 Altera 的Cyclone V 实现了业界最低的系统成本和功耗，其性能水平使得该器件系列成为突出您大批量应用优势的理想选择。与前几代产品相比，总功耗降低了40%，具有高效的逻辑集成功能，提供集成收发器型号以及具有基于ARM? 的硬核处理器系统(HPS) 的SoC FPGA 型号。Cyclone? V FPGA为业界提供系统成本最低、功耗最低的FPGA 解决方案，以及小尺寸封装选项。这些优点结合其性能和逻辑利用率特性，实现了能够突出您大批量应用优势的器件。内核 ARM+FPGA 架构中精度可调数字信号处理(DSP) 模块、多端口存储器控制器和多功能PCI Express Gen2 增强IP 等丰富的硬核知识产权(IP) 模块帮助您以更低的系统总成本和更短的设计时间完成更多的工作。作为一种可以马上使用的功能，这些硬核IP 模块简化了您的开发过程，进一步降低了功耗，在增强存储器控制器方面，相对于软核逻辑占用了更少的电路板空间。而且还节省了很多的逻辑资源，从而用于实现独特的功能，突出您的产品优势。 Cyclone V 收发器 低成本收发器各有不同。借助Altera Cyclone? V FPGA 系列的灵活性，您可以全面利用所有收发器资源，在体积更小、成本更低的器件中实现设计。Cyclone V FPGA 能够非常灵活的通过增强构建模块以尽可能低的功耗来实现独立协议和专用协议。
Cyclone V SoC FPGA使用宽带互联干线链接，Altera SoC 集成了基于ARM 的硬核处理器系统(HPS)，包括处理器、外设和存储器接口。Cyclone? V SoC 在一个基于ARM 的用户可定制芯片系统(SoC) 中集成了分立处理器、FPGA 和数字信号处理(DSP) 功能，帮助您降低了系统功耗、系统成本，减小了电路板面积，提高了系统性能。Altera FPGA 同时实现了硬核知识产权(IP) 的性能和低功耗特性以及可编程逻辑的灵活性。 功耗降低40% Altera 的Cyclone V FPGA 采用了28-nm 低功耗(LP) 工艺技术进行开发，为需要5G 收发器的应用提供了最低功耗解决方案。与前几代产品相比，Cyclone V FPGA 功耗降低了40%，均衡的降低了所有领域的功耗。 智明力强光电cyclone V核心板让您拥有稳定的开发平台、强大的技术支持，加快了研发进度，降低了研发风险。 产品特点 ?可在线远程升级，升级安全无忧； ?提供两种加密方式，设计安全无忧； ?军规检测保证，质量安全无忧； ?FPGA级双机热备，可靠性安全无忧； ?提供Open CL支持，满足并行加速需求； ?硬件成熟稳定，经过军方与工业客户验证
6713-FPGA开发板手册
DSP6713-FPGA-USB2.0高速采集板 用户手册 (Ver2.21)
目录 1．产品简介 (3) １．１ 系统简介 (4) １．２ 系统资源 (4) １．３ 扩展接口 (5) １．４ 代码及实验项目 (5) １．５ 相关资料 (6) １．６ 相关配件 (6) １．７ 完好性快速检查 (7) 2．学习之前的准备工作 (8) ２．１ 硬件准备 (8) ２．２ 软件准备 (8) 3．软件安装及设置 (10) ３．１ 安装ＣＣＳ ２．２ ｆｏｒ Ｃ６０００ (10) ３．２ 安装仿真器驱动 (10) ３．３设置ＣＣＳ (10) 3.3.1 使用并口仿真器设置CCS (10) 3.3.2 使用USB接口仿真器设置CCS (16) ３．４ ＣＣＳ软件简介 (17) 3.4.1建立或打开一个PROJECT工程文件 (17) 3.4.2 CMD文件设置 (17) ４．硬件电路讲解 (18) ４．１ 供电电路 (18) ４．２ ＤＳＰ复位电路 (19) ４．３ 外扩ＳＤＲＡＭ电路 (20) ４．４ 外扩ＦＬＡＳＨ电路 (21) ４．５ ＤＳＰ标准ＪＴＡＧ调试接口 (22) ４．６ ＦＰＧＡ标准ＪＴＡＧ下载接口 (22) ４．８ ＦＰＧＡ配置电路 (23) ４．８ 扩展ＡＤ接口 (23) ４．９ 扩展ＦＰＧＡ通用ＩＯ接口 (24) ４．１０ 扩展ＤＳＰ控制信号接口 (24) ４．１１ ＵＳＢ部分固件电路 (25) ４．１２ ＵＳＢ部分串口调试电路 (25) ４．１３ ＵＳＢ部分扩展ＳＲＡＭ电路 (26) ４．１４ 数码管控制电路 (26) ５．软件实验讲解 (27) ５．１ 操作步骤 (27) ５．２ 烧写ＦＬＡＳＨ (33)