ITE布线-电容式触摸屏Sensor内部结构设计规则

Application Note

Title: Layout Guidelines of IT7250/ 7260

Part No.: IT7250/7260 Chip Ver: BX

Doc No.: ITAE-AN-09-1-09 Doc Ver: V1.0

Date: June 25, 2010 Confidential Table of Contents

1 IT7250/7260 FPC/PCB Layout Guidelines (2)

1.1 Reference circuit (2)

1.2 Layout guidelines (3)

2 IT7250/IT7260 ITO Layout Guidelines (6)

2.1 Cap. sensor traces and shield signal layout (6)

2.2 IT7250/IT7260 Support Three Types of ITO sensors (8)

2.3 ITO with button format (17)

1. IT7250/7260 FPC/PCB Layout Guidelines

1.1 Reference circuit

(1) The reference circuit of IT7250 is shown in Figure1-1 and 1-2. And the

IT7260’s components are the same with IT7250.

Figure.1-1 IIC interface

R1, R2, R3, and R4: are optional for host address setting

If host’s I2C bus has pull up resisters, R6 and R7 can be removed on FPC

Fig. 1-2 SPI Interface

(2) The recommended component area of FPC is 9 X 9 mm for IT7250 and

12 X 12 mm for IT7260.

(3) If the FPC connector still have unused pins, it is recommended to add

ground pins to reduce grounding impedance.

1.2 Layout guidelines

Capacitance sensor trace (CIN trace) width: 4 mils are recommended. The air gap between each CIN trace and signal which is connected to ITO sensor should be bigger than 4 mils if 4-mils width line is used for each trace.

The FPC grounding impedance needs smaller than 3 ohm.

The way via a hole is not recommended for capacitance sensor traces.

If this way is required for PCB/FPC, please drill the hole near

IT7250/7260 and/or ITO connector; and the maximum number of via holes are 2.

Analog ground could be a plane or wide trace line and is connected to digital ground plane by a 40-mil width short trace line. It should be

separated from FPC/PCB connector side’s digital ground, as shown in Figure 2.

Fig. 2

IIC signal trace layout should be separated farther apart from capacitance sensor traces to further decrease unknown noise coupling to ITO. A GND plane under IIC signals is recommended to get good IIC bus performance, as shown in Figure 3.

The ITO shield pin should be connected to the IT7250/IT7260 shield pin, and the pin could not be connected to GND. Whole CINs (from

IT7250/7260) connected to ITO layout trace should be surrounded with shield plane to get good performance. The upper layer of the FPC is shield plane while the lower layer of it is capacitance sensor’s golden fingers which connect FPC to ITO in order to enhance the accuracy of the position

estimation, as shown in Figure 3.

Fig. 3

Thermal pad of IT7250/7260 is connected to GND plane, as shown in Figure 4.

Fig. 4

To improve the ESD capability, please implement the following design.

More FPC space is required to add extra GND pad in order to contact that GND plane of FPC and the GND chassis of system module, as shown in Figure 5.

Fig. 5

2. IT7250/IT7260 ITO Layout Guidelines

2.1 Cap. sensor traces and shield signal layout

(1) Shield Signal of IT7250/7260:

To decrease the noise, it is recommended to add a trace line out of ITO’s Capacitance sensor signal area and connect it to IT7250/7260 Shield signal, as shown in Figure 6.

Fig. 7-1 Fig. 7-2 (3)

Cap. sensor trace with dummy line on ITO:

Adding a dummy line as shown in Figure 8 can decrease noise and avoid the positioning error

Fig. 8

2.2 IT7250/IT7260 support three types of ITO sensors (1) One layer without bridge: Right triangle set format

One layer without bridge:

The number of right triangle set in each bar should be 4(as shown in Figure 9-1) if the bar height is above 7mm. Otherwise, a bar with 3-set right triangle (as shown in Figure 9-2) is enough

Fig. 9-1

Fig. 9-2

Height of bar:

10mm of the maximum height is recommended for each bar. For the bar height above 7mm and below 10mm, 4 pairs of right triangle in each bar is recommended (Figure10-1). Otherwise, 3 pairs are for the height

below 7mm, as shown in Figure 10-2.

Fig. 10-2

Right triangle set format:

The bar pattern is formatted by two symmetrical right triangle sets, as shown in Figure 11.

Fig.11

Gap between two bars:

The gap between each bar should be as small as possible to increase

the touch sensing area, as shown in Figure 12

Fig. 13

Gap between two caps sensor traces:

The gap shown in Figure 14 between each dummy line and the nearby traces should be as small as possible to enhance the positioning

accuracy of the border area.

Fig. 15

Gap between shielding signal and bar of board side:

The gap shown in Figure 16 between shielding signal and the bar

should be as close as possible to enhance the positioning accuracy of the border area.

(2) One layer with bridge (SITO): Diamond format

One-layer ITO:

For the one-layer ITO sensor shown in Figure 18-1 and 18-2 with the diamond pattern, it is necessary to add bridges to x-axis or y-axis.

Fig. 18-1

Fig. 18-2 x-axis or y-axis ITO pattern

Diamond Size:

To enhance the positioning accuracy, it is recommended to have the diamond width and height about 5mm to 6mm, as shown in Figure 19.

Fig. 19

(3) Two layers without bridge (DITO): Diamond format

Two-Layer ITO:

For the two-layer ITO sensor See Figure 20-1 and 20-2 with the diamond pattern, it is not necessary to add any bridges to x-axis or y-axis.

Fig. 20-1

Fig. 20-2 two-layer –x-axis or y-axis form.

Diamond size:

To enhance the positioning accuracy, it is recommended to have the diamond width and height about 5mm to 6mm, as shown in Figure 19.

The common issue for two layer ITO layout and ITE’s solution:

Since IT7250/60 detects the finger touch by sensing the capacitance difference between channels, sometimes the improper trace layout may cause ghost point. For example, once finger touches on Area-F where traces from A to B are covered (Figure 21). Line X since trace B got

CDC value and the line will be detected abnormally. That usually

happens on film sensor.

Fig. 21

There are some solutions to decrease this ghost point issue.

(a) For two-layer sensor, please put Figure 22-1 layout on top layer and

Figure 22-2 on bottom layer.

Fig. 22-1 Fig.22-2

(b) Insert shield signal trace line of IT7250/7260 between X-axis and Y-axis,

as shown in Figure 23.

Shield Signal of IT7250/7260

Fig. 23

(c) For FPC side, please put shield or GND plane on top layer and

capacitance sensor traces on bottom layer, then the finger cannot touch on capacitance sensor trace directly.

2.3 ITO with button format

Please check with Figure 24. There has a dummy Capacitance sensor trace line (blue line) be other buttons differential pair to enhance button detection.

Fig. 24