英文与译文
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All About Direct Digital Synthesis
By Eva Murphy [eva.murphy@https://www.sodocs.net/doc/1616908225.html,]
Colm Slattery [colm.slattery@https://www.sodocs.net/doc/1616908225.html,]
What is Direct Digital Synthesis?
Direct digital synthesis (DDS) is a method of producing an analog waveform —usually a sine wave —by generating a time-varying signal in digital form and then performing a digital-to-analog conversion. Because operations within a DDS device are primarily digital, it can offer fast switching between output frequencies, fine frequency resolution, and operation over a broad spectrum of frequencies. With advances in design and process technology, today’s DDS devices are very compact and draw little power.
Why would one use a direct digital synthesizer (DDS)? Aren’t there other methods for easily generating frequencies?
The ability to accurately produce and control waveforms of various frequencies and profiles has become a key requirement common to a number of industries. Whether providing agile sources of low-phase-noise variable-frequencies with good spurious performance for communications, or simply generating a frequency stimulus in industrial or biomedical test equipment applications, convenience, compactness, and low cost are important design considerations.
Many possibilities for frequency generation are open to a designer, ranging from phase-locked-loop (PLL)-based techniques for very high-frequency synthesis, to dynamic programming of digital-to-analog converter (DAC) outputs to generate arbitrary waveforms at lower frequencies. But the DDS technique is rapidly gaining acceptance for solving frequency- (or waveform) generation requirements in both communications and industrial applications because single-chip IC devices can generate programmable analog output waveforms simply and with high resolution and accuracy.
Furthermore, the continual
improvements in both process
technolog y and design have
resulted in cost and power
consumption levels that were previously unthinkably low. For example, the AD9833, a DDS-based programmable
waveform generator (Figure 1), operating at 5.5 V with a 25-MHz clock, consumes a Figure 1. The AD9833-a one-chip waveform generator.
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What are the main benefits of using a DDS?
DDS devices like the AD9833 are programmed through a high speed serial peripheral-interface (SPI), and need only an external clock to generate simple sine waves. DDS devices are now available that can generate frequencies from less than 1 Hz up to 400 MHz (based on a 1-GHz clock). The benefits of their low power, low cost, and single small package, combined with their inherent excellent performance and the ability to digitally program (and re-program) the output waveform, make DDS devices an extremely attractive solution —preferable to less-flexible solutions comprising aggregations of discrete elements.
What kind of outputs can I generate with a typical DDS device?
DDS devices are not limited to purely
sinusoidal outputs. Figure 2 shows the
square-, triangular-, and sinusoidal outputs
available from an AD9833.
How does a DDS device create a sine
wave?
Here’s a breakdown of the internal
circuitry of a DDS device: its main
components are a phase accumulator, a
means of phase-to-amplitude conversion
(often a sine look-up table), and a DAC.
These blocks are represented in Figure 3.
A DDS produces a sine wave at a given frequency. The frequency depends on two variables, the reference-clock frequency and the binar y number programmed into the frequency register (tuning word).
The binary number in the
frequency register provides
the main input to the phase
accumulator. If a sine
look-up table is used, the phase accumulator computes
Figure 2. Square-, triangular-, and sinusoidal outputs from a DDS.
Figure 3. Components of a direct digital synthesizer.
a phase (angle) address for the look-up table, which outputs the digital value of amplitude—corresponding to the sine of that phase angle—to the DAC. The DAC, in turn, converts that number to a corresponding value of analog voltage or current. To generate a fixed-frequency sine wave, a constant value (the phase increment—which is determined by the binary number) is added to the phase accumulator with each clock cycle. If the phase increment is large, the phase accumulator will step quickly through the sine look-up table and thus generate a high frequency sine wave. If the phase increment is small, the phase accumulator will take many more steps, accordingly generating a slower waveform.
What do you mean by a complete DDS?
The integration of a D/A converter and a DDS onto a single chip is commonly known as a complete DDS solution, a property common to all DDS devices from ADI.
Let’s talk some more about the phase accumulator. How does it work?
Continuous-time sinusoidal signals have a repetitive angular phase range of 0 to 2.The digital implementation is no different. The counter’s carry function allows the phase accumulator to act as a phase wheel in the DDS implementation.
To understand this basic function, visualize the sine-wave oscillation as a vector rotating around a phase circle (see Figure 4). Each designated point on the phase wheel corresponds to the equivalent point on a
cycle of a sine wave. As the vector rotates
around the wheel, visualize that the sine of the
angle generates a corresponding output sine
wave. One revolution of the vector around the
phase wheel, at a constant speed, results in
one complete cycle of the output sine wave.
The phase accumulator provides the equally
spaced angular values accompanying the
vector’s linear rotation around the phase Figure 4. Digital phase wheel.
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wheel. The contents of the phase accumulator correspond to the points on the cycle of the output sine wave.
The phase accumulator is actually a modulo- M counter that increments its stored number each time it receives a clock pulse. The magnitude of the increment is determined by the binary-coded input word (M). This word forms the phase step size between reference-clock updates; it effectively sets how many points to skip around the phase wheel. The larger the jump size, the faster the phase accumulator overflows and completes its equivalent of a sine-wave cycle. The number of discrete phase points contained in the wheel is determined by the resolution of the phase accumulator (n), which determines the tuning resolution of the DDS. For an n = 28-bit phase accumulator, an M value of 0000...0001 would result in the phase accumulator overflowing after 28 reference-clock cycles (increments). If the M value is changed to 0111...1111, the phase accumulator will overflow after only 2 reference-clock cycles (the minimum required by Nyquist). This relationship is found in the basic tuning equation for DDS architecture:
n C out f M f 2
?= where:
fOUT = output frequency of the DDS
M = binary tuning word
fC = internal reference clock frequency (system clock)
n = length of the phase accumulator, in bits
Changes to the value of M result in immediate and phase-continuous changes in the output frequency. No loop settling time is incurred as in the case of a phase-locked loop.
As the output frequency is increased, the number of samples per cycle decreases. Since sampling theory dictates that at least two samples per cycle are required to reconstruct the output waveform, the maximum fundamental output frequency of a DDS is fC/2. However, for practical applications, the output frequency is limited to somewhat less than that, improving the quality of the reconstructed waveform and
permitting filtering on the output.
When generating a constant frequency, the output of the phase accumulator increases linearly, so the analog waveform it generates is inherently a ramp.
Then how is that linear output translated into a sine wave?
A phase -to - amplitude lookup table is used to convert the phase-accumulat or’s instantaneous output value (28 bits for AD9833)—with unneeded less-significant bits eliminated by truncation—into the sine-wave amplitude information that is presented to the (10 -bit) D/A converter.
The DDS architecture exploits
the symmetrical nature of a sine
wave and utilizes mapping logic
to synthesize a complete sine
wave from one-quarter-cycle of
data from the phase accumulator.
Figure 5. Signal flow through the DDS architecture. The phase-to- amplitude lookup
table generates the remaining data by reading forward then back through the lookup table. This is shown pictorially in Figure 5.
What are popular uses for DDS?
Applications currently using DDS-based waveform generation fall into two principal categories: Designers of communications systems requiring agile (i.e., immediately responding) frequency sources with excellent phase noise and low spurious performance often choose DDS for its combination of spectral performance and frequency-tuning resolution. Such applications include using a DDS for modulation, as a reference for a PLL to enhance overall frequency tunability, as a local oscillator (LO), or even for direct RF transmission.
Alternatively, many industrial and biomedical applications use a DDS as a programmable waveform generator. Because a DDS is digitally programmable, the phase and frequency of a waveform can be easily adjusted without the need to change the external components that would normally need to be changed when using
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traditional analog-programmed waveform generators. DDS permits simple adjustments of frequency in real time to locate resonant frequencies or compensate for temperature drift. Suchapplications include using a DDS in adjustable frequency sources to measure impedance (for example in an impedance-based sensor), to generate pulse-wave modulated signals for micro-actuation, or to examine attenuation in LANs or telephone cables.
What do you consider to be the key advantages of DDS to designers of
real-world equipment and systems?
Today’s cost- competitive, high - performance, functionally integrated DDS ICs are becoming common in both communication systems and sensor applications. The advantages that make them attractive to design engineers include:
? digitally controlled micro-hertz frequency-tuning and sub-degree phase-tuning capability,
? extremely fast hopping s peed in tuning output frequency (or phase); phase - continuous frequency hops with no overshoot/undershoot or analog-related loop settling-time anomalies,
? the digital architecture of DDS eliminates the need for the manual tuning and tweaking related to component aging and temperature drift in analog synthesizer solutions, and
? the digital control interface of the DDS architecture facilitates an environment where systems can be remotely controlled and optimized with high resolution under processor control.
How would I use a DDS device for FSK encoding?
Binary frequency-shift keying (usually referred to simply as FSK) is one of the simplest forms of data encoding. The data is transmitted by shifting the frequency of a continuous carrier to one of two discrete frequencies (hence binary). One frequency, f1, (perhaps the higher) is designated as the mark frequency (binary one) and the other, f0, as the space frequency (binary zero). Figure 6 shows an example of the relationship between the mark-space data and the transmitted signal.
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This encoding scheme is easily
implemented using a DDS. The DDS
frequency tuning word, representing the
output frequencies, is set to the
appropriate values to generate f0 and f1
as they occur in the pattern of 0s and 1s
to be transmitted. The user programs the
two required tuning words into the device before transmission. In the case of the AD9834, two frequency registers are available to facilitate convenient FSK encoding. A dedicated pin on the device
(FSELECT) accepts the modulating signal and selects the appropriate tuning word (or frequency register). The block diagram in Figure 7 demonstrates a simple
implementation of FSK encoding.
And how about PSK coding?
Phase-shift keying (PSK) is another
simple form of data encoding. In PSK, the
frequency of the carrier remains constant
and the phase of the transmitted signal is
varied to convey the information.
Of the schemes to accomplish PSK, the simplest-known as binary PSK (BPSK)—
uses just two signal phases, 0 degrees and 180 degrees. BPSK encodes 0 phase shift for a logic 1 input and 180 phase shift for a logic 0 input. The state of each bit is determined according to the state of the preceding bit. If the phase of the wave does not change, the signal state stays the same (low or high). If the phase of the wave reverses (changes by 180 degrees), then the signal state changes (from low to high, or from high to low).
PSK encoding is easily implemented with DDS ICs. Most of the devices have a separate input register (a phase register) that can be loaded with a phase value. This value is directly added to the phase of the carrier without changing its frequency. Figure 6. FSK modulation. Figure 7. A DDS-based FSK encoder.
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Changing the contents of this register modulates the phase of the carrier, thus generating a PSK output signal. For applications that require high speed modulation, the AD9834 allows the preloaded phase registers to be selected using a dedicated toggling input pin (PSELECT), which alternates between the registers and modulates the carrier as required.
More sophisticated forms of PSK employ four- or eight- wave phases. This allows binary data to be transmitted at a faster rate per phase change than is possible with BPSK modulation. In four-phase modulation (quadrature PSK or QPSK), the possible phase angles are 0, +90, –90, and 180 degrees; each phase shift can represent two signal elements. The AD9830, AD9831, AD9832, and AD9835 provide four phase registers to allow complex phase modulation schemes to be implemented by continuously updating different phase offsets to the registers.
Can multiple DDS devices be synchronized for, say, I-Q capability?
It is possible to use two single DDS devices that operate on the same master clock to output two signals whose phase relationship can then be directly controlled. In Figure 8, two AD9834s are programmed using one reference clock, with the same reset pin being used to update both parts. Using this setup, it is possible to do I-Q modulation.
A reset must be asserted after power-up
and prior to transferring any data to the DDS.
This sets the DDS output to a known phase,
which serves as the common reference point
that allows synchronization of multiple DDS
devices. When new data is sent simultaneously
to multiple DDS units, a coherent phase relationship can be maintained, and their relative phase offset can be predictably shifted by means of the phase-offset register. The AD9833 and AD9834 have 12 bits of phase resolution, with an effective
resolution of 0.1 degree. [For further details on synchronizing multiple DDS units please see Application Note AN-605.] Figure 8. Multiple DDS ICs in synchronous mode.
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What are the key performance specs of a DDS based system?
Phase noise, jitter, and spurious-free dynamic range (SFDR).
Phase noise is a measure (dBc/Hz) of the short-term frequency instability of the oscillator. It is measured as the single-sideband noise resulting from changes in frequency (in decibels below the amplitude at the operating frequency of the oscillator using a 1-Hz bandwidth) at two or more frequency displacements from the operating frequency of the oscillator. This measurement has particular application to performance in the analog communications industry.
Do DDS devices have good phase noise?
Noise in a sampled system depends on many factors. Reference-clock jitter can be seen as phase noise on the fundamental signal in a DDS system; and phase
truncation may introduce an error level into the system, depending on the code word chosen. For a ratio that can be exactly expressed by a truncated binary-coded word, there is no truncation error. For ratios requiring more bits than are available, the resulting phase noise truncation error results in spurs in a spectral plot. Their magnitudes and distribution depends on the code word chosen. The DAC also
contributes to noise in the system. DAC quantization or linearity errors will result in both noise and harmonics. Figure 9
shows a phase noise plot for a typical
DDS device —in this case an
AD9834.
What about jitter?
Jitter
is the dynamic displacement of digital signal edges from their long-term average
positions, measured in degrees rms. A perfect oscillator would have rising and falling edges occurring at precisely regular moments in time and would never vary. This, of course, is
Figure 9. Typical output phase noise plot
for the AD9834. Output frequency is 2
MHz and M clock is 50 MHz.
impossible, as even the best oscillators are constructed from real components with sources of noise and other imperfections. A high-quality, low-phase-noise crystal oscillator will have jitter of less than 35 picoseconds (ps) of period jitter, accumulated over many millions of clock edges
Jitter in oscillators is caused by thermal noise, instabilities in the oscillator electronics, external interference through the power rails, ground, and even the output connections. Other influences include external magnetic or electric fields, such as RF interference from nearby transmitters, which can contribute jitter affecting the oscillator’s output. Even a simple amplifier, inverter, or buffer will contribute jitter to a signal.
Thus the output of a DDS device will add a certain amount of jitter. Since every clock will already have an intrinsic level of jitter, choosing an oscillator with low jitter is critical to begin with. Dividing down the frequency of a high-frequency clock is one way to reduce jitter. With frequency division, the same amount of jitter occurs within a longer period, reducing its percentage of system time.
In general, to reduce essential sources of jitter and avoid introducing additional sources, one should use a stable reference clock, avoid using signals and circuits that slew slowly, and use the highest feasible reference frequency to allow increased oversampling.
Spurious-Free Dynamic Range (SFDR)refers to the ratio (measured in decibels) between the highest level of the fundamental signal and the highest level of any spurious, signal—including aliases and harmonically related frequency components—in the spectrum. For the very best SFDR, it is essential to begin with a high-quality oscillator.
SFDR is an important specification in an application where the frequency spectrum is being shared with other communication channels and applications. If a transmitter’s output sends spurious signals into other frequency bands, they can corrupt, or interrupt neighboring signals.
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Typical output plots taken from an AD9834 (10-bit DDS) with a 50MHz master clock are shown in Figure10. In (a), the output frequency is exactly 1/3 of the master clock frequency (MCLK). Because of the judicious choice of frequencies, there are no harmonic frequencies in the 25-MHz window, aliases are minimized, and the spurious behavior appears excellent, with all spurs at least 80 dB below the signal (SFDR = 80 dB). The lower frequency setting in (b) has more points to shape the waveform (but not enough for a really clean waveform), and gives a more realistic picture; the largest spur, at the second-harmonic frequency, is about 50 dB below the
signal (SFDR = 50 dB).
(a) f OUT = 16.667MHz (b) f OUT = 4.8MHz.
Figure 10. Output of an AD9834 with a 50MHz master clock
Do you have tools that make it
easier to program and predict the
performance of the DDS?
The on-line interactive design
tool is an assistant for selecting
tuning words, given a reference
clock and desired output
frequencies and/or phases. The
required frequency is chosen, and
idealized output harmonics are shown after an external
Figure 11. Screen presentation provided by an interactive design tool. A sinx/x presentation of a typical device output.
reconstruction filter has been applied. An example is shown in Figure 11. Tabular data is also provided for the major images and harmonics.
How will these tools help me program the DDS?
All that’s needed is the
required frequency output and
the system’s reference clock
frequency. The design tool will
output the full programming
sequence required to program
the part. In the example in
Figure 12, the MCLK is set to
Figure 12. Typical display of programming sequence.
25 MHz and the desired output
frequency is set to 10MHz. Once the update button is pressed, the full programming sequence to program the part is contained in the Init Sequence register.
How can I evaluate your DDS devices?
All DDS devices have an evaluation board available for purchase. They come with dedicated software, allowing the user to test/evaluate the part easily within minutes of receiving the board. A technical note accompanying each evaluation board contains schematic information and shows best recommended board-design and layout practice.
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关于直接数字频率合成器
由伊娃墨菲[eva.murphy @ https://www.sodocs.net/doc/1616908225.html,]
寇斯拉特里[colm.slattery @ https://www.sodocs.net/doc/1616908225.html,]
什么是直接数字频率合成器？
直接数字频率合成器（DDS）是一种通过产生一个以数字形式时变的信号，然后执行由数字至模拟转换的方法。由于DDS设备的操作主要是数字的，它可以提供快速解决输出频率之间切换，优点是有精细的频率和运行频率范围广泛。由于设计方面和工艺技术的进步，今天的DDS器件是非常紧凑的小功率。
为什么要使用直接数字频率合成器（DDS）？不同频率和配置文件是不是有其他的方法能够很容易地产生频率？
能够准确地产生和控制波形已经成为一些行业的主要要求。无论是提供低相位噪声的杂散性能良好的可变频率通信，还是只需在生成的频率上激活工业或生物医学检测设备的应用程序，成本低是重要的设计考虑。
设计师以相位锁定回路（PLL）为基础的需要非常高的频率的合成技术，以DAC的动态规划的数字toanalog转换器（输出产生较低的频率任意波形）来产生许多可能产生的频率，但DDS技术迅速获得了解决频率（或波形）产生和工业应用要求的方法，因为单芯片集
成电路器件可以产生简单的可编
程的模拟输出高分辨率和准确性
的波形。
此外，在这两个过程中不断改
图1 AD9833波形发生器
进技术和设计，使成本和功耗水平
前所未有的低。例如AD9833，一个基于DDS的可编程波形发生器（图1），工作电压5.5V与25MHz的时钟，消耗的最大功率为30mW。
使用DDS有什么主要好处？
对DDS的AD9833器件进行编程，如通过一个高速串行外设接口（SPI），而且只需要一个外部时钟来生成简单的正弦波。DDS器件现已可以产生从1到400MHz的频率，（时钟基于103MHz兆赫）。电源效益低，成本低，包装单小，
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加上其固有的优良性能，并能够以数字
形式（和重新编程）输出波形使DDS 器
件是极具吸引力的解决方案，相比不太
灵活的包括分子聚合离散在内的解决方
案。
一个典型的DDS 的设备可以产出什
么样的输出？
DDS 器件不仅限于纯粹的正弦波输
出。图2显示了方波、三角波和正弦波
输出。
如何使用DDS 的设备创建一个正弦波？
这里有一个DDS 的内部电路：其主
要成分是相位累加器，振幅
转换（通常是正弦查找）和
一个DAC 。这些模块的代表图如图3。
DDS 产生一个特定频
率的正弦波。它的频率取决于两个变量，参考时钟频率和（控制字）数字编程的频率。
二进制数的频率主要输入到相位累加器。在使用正弦查找表时，用相位累加器计算一个阶段（角）的地址查找表，输出幅度的数字值对应相位角的正弦。反过来，DAC 把这个数字转换为相应值的模拟电压或电流。要生成一个固定频率的正弦波，恒定值（相位增量，这是由二进制数决定）被添加到时钟周期的相位累加器。如果相位增量大，相位累加器会迅速通过正弦查找表，从而产生高频率的正弦波。如果相位增量小，相位累加器将采取更多的步骤，因而产生较慢的波形。
完整的DDS 是什么意思？
D/A 转换器和一个DDS 的单一芯片的整合通常被称为一个完整的DDS 的解决方案，ADI 公司的普通性质DDS 。让我们说些有关累加器的知识。它是如何
图2 DDS 输出的矩形波-三角波-正弦波 图3 组件的直接数字合成器
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工作的？连续时间正弦信号的角度范围内有一个重复的阶段0至2。数字的实施没有什么不同，该计数器可以把相位累加器作为DDS 的功能来执行。
为了理解这一点的基本功能，将可视化的正弦波振荡作为一个阶段轮围绕旋转圆向量（见图4）。每个阶段轮指向对应的等效点1波周期的正弦。由于矢量旋转的轮子，形象化的角度的正弦值产生相应的正弦波。一个车轮周围的相速度向量，为一个常数，正弦波输出结果为一
个完整周期。相位累加器提供等距相角值
随车轮周围的向量线性旋转。相位累加器
对应于点的波周期输出的正弦。
相位累加器实际上是一个模- M 的计数
器，每次收到一个时钟脉冲其存储的数量
递增。递增幅度取决于输入字（米）。这
个字形成相位步长之间的参考，它有效地
设置跳过多少分左右相轮。规模越大的跳
跃，相位累加器以越快的速度溢出，且其
周期相当于一个正弦波。该轮在数字离散
相点中，取决于分辨率的相位累加器（n ），这决定了DDS 的调谐。对于一个n = 28位相位累加器，1 ... 0001 M 值的0000会导致相位累加器溢出后228参考时钟周期（增量）。如果M 值更改为0111 ... 1111，相位累加器溢出后，将只有2参考时钟周期（取决于奈奎斯特最低要求）。这种关系是发生在基本调整方程DDS 的结构为：
n C out f M f 2?= 其中：FOUT 是DDS 的输出频率
M 是频率控制字的二进制
f C 是内部参考时钟频率（系统时钟）
n 是每组长度的相位累加器位，
M 的值发生变化导致输出频率的变化。无回路的建立时间发生在一个循环锁相内。由于输出频率的增加，减少样本周期数。
图4 数字相位轮
由于抽样理论决定了至少两个周期，每样都需要重建的输出波形，基本的DDS 输出频率是f C/2。
然而，对于实际应用中，输出频率是有限的，在一定程度改善波形质量的重建，并允许滤波输出。当产生
一个恒定的频率，相位输出线性
增加，因此模拟波形生成本身就
是一个斜坡。
试问，线性输出波形怎样转
化为正弦波？
A相方法-振幅查找表用于转
图5 流过DDS的信号
换相位累加器的瞬时输出值（28
比特AD9833）将正弦波振幅信息，提交（10位）到D/A转换器。DDS的结构充分利用了正弦波对称的性质和利用的一个映射逻辑合成一个完整周期的正弦波。该相位对振幅查找表其余数据通过阅读然后再向前，这形象地显示在图5。什么是DDS的常用用途？
应用程序当前正在使用基于DDS产生的基本波形，分为两个主要类别：根据通信系统的设计要求，性能优良的频率源的相位噪声低，往往选择其组合的DDS光谱性能和频率调谐分辨率。这些应用包括使用DDS调制，作为一个PLL 参考频率，以提高整体可调，作为本地振荡器，甚至直接射频传输。
另外，许多工业和生物医学应用DDS的波形发生器作为一个可编程的器件。因为DDS是数字可编程，相位和波形频率可以很容易地调整，而无需改变外部元件，通常需要改变时，使用传统的模拟编程即可。DDS调整简单，找到共振的频率或补偿温度漂移。这样应用包括使用频率源DDS在一个可调节测量阻抗的阻抗传感器（例如在1），产生的脉冲波调制信号电缆用于微型驱动，或在局域网检查电话衰减。
你认为对于现实世界系统设备的设计者，DDS的关键优点是什么？
今天的成本竞争力，高性能，功能集成DDS IC是越来越常见的两种通信系统和传感器应用。他们的优点，对设计工程师的吸引力，包括：
?数字控制微赫兹的频率调整和相位调谐能力，跳跃速度非常快；
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?在调整输出频率（或阶段）连续频率无过冲或模拟相关的循环时间异常； ?DDS 的数字架构消除了需要解决的手动调谐合成器和调整相关的模拟元件老化和温度漂移；
?DDS 的数字控制接口的架构有利于实现高分辨率环境下，系统可以进行远程控制和优化控制处理器。
我会用怎样的FSK 编码DDS 设备？
二进制频移键控（简称为FSK ）
是一个最简单的数据编码形式。数据
传输通过将载波频率连续的传到两个
分立的频率。因此一个频率，f1，（或
许较高的）被指定为标记频率（二进
制的），另一个频率f0作为基频（二
进制零）。图6显示了一个例子，空间数据和传输信号之间的关系。
这种编码方案很容易实现DDS 的使用。DDS 的频率控制字，代表输出频率，设置为适当的值来生成f0和f1的，因为它
们在0和1以进行传输。传输到设备之前
用户需要调整方案。在AD9834，两个频
率寄存器，可方便的进行FSK 编码。A 的
设备专用针（FSELECT ）接受调制信号，
并选择合适的控制字（或频率寄存器）。
该框图图7演示了简单的FSK 信号的编码。
频移键控PSK 编码怎么样？
相移键控（PSK ）是另一种数据编码的简单形式。在PSK ，载波频率保持不变，并在第二阶段的信号传输传达的信息是多种多样的。
在这计划完成的PSK ，（最简单的-）被称为二进制的PSK （BPSK 调制），只用两个信号相位，0度和180度。每个位的状态来决定该位的状态上。如果波阶段的不改变，信号状态保持不变（低或高）。如果波阶段（180度的变化），那么信号状态变化（从低到高，或从高至低）。
容易实现的PSK 编码是用DDS 芯片。设备大部分有一个单独的输入寄存器 图6 FSK 调制 图7 一个基于DDS 的编码
（相位寄存器），可以装载一个阶段的值。这个值直接添加到载波相位而不改变其频率。改变这种调制的载波相位，因此产生的PSK输出信号。用于需要高速调制，AD9834允许预装阶段寄存器进行切换选择使用专用输入引脚（PSELECT），这之间交替按规定调控的载体。
更多复杂的PSK形式选用4或8波阶段。这使得被传送二进制数据在每个阶段的变化速度可能比BPSK调制慢。在fourphase调制（正交PSK或QPSK调制），可能相角为0，+90，-90，和180度，每相移可以代表两个信号分子。在AD9830，AD9831，AD9832，AD9835的提供4个阶段和寄存器，允许复杂的相位调制的计划实施，不断更新注册不同相位偏移。
多个DDS器件可以同步吗，也就是说，智商能力？
它可以使在同一主机两个单DDS器件
的时钟运行输出的两个信号的相位关系可
直接控制。在图8里，两个AD9834s是用一
个程序参考时钟引脚，以同样的重置用于更
新两个部分。使用这种设置，有可能做智商
图8 多个DDS同步模式
调制。
传输任何数据之前，先复位该DDS，做之前必须断电。这将设置DDS输出到一个已知的阶段，它作为共同的参照点，允许符合多个DDS的同步装置。当新的数据同时发送到多个DDS的单位，一连贯的相位关系可以保持，以及它们的相对相位偏移可预见由相位偏移寄存器方式转变。AD9833和AD9834的有12位分辨率的阶段，具有有效分辨率为0.1。多个DDS的同步如需进一步详情请参阅应用笔记AN-605。
什么是基于DDS系统的主要性能规格？
相位噪声，抖动，无杂散动态范围（SFDR）。相位噪声（dB/Hz的）的频率不稳定,振荡器短。它是衡量作为单边带从频率变化造成的噪音低于在使用振荡器的（工作频率为1Hz）的带宽在两个或多个频率位移振荡器工作频率振幅分贝。这种具有特殊性能的测量方法应用在模拟通信。
DDS器件具有良好的相位噪音？
对采样系统的噪声，取决于很多因素。参考时钟抖动可以被看作是对基本
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信号的相位噪声在DDS 的制度，相位截断可以根据码字选择引入到系统中的一个错误级别。对于一个完全可以由一个二进制编码表示的比例，也没有截断误差。对于需要更多超过可用的位数，由此产生的相位噪声截断误差结果如光谱图。他们的大小和分布取决于选择
的代码字。该DAC 还有助于在系
统中的噪音。DAC 的量化或线性
误差会造成噪音及谐波。图9显示
了相位噪声DDS 在这种情况下一
个典型情节，设备的AD9834。
怎么样抖动？
度均方根抖动是数字信号的
动态位移的长期测量。振荡器将有
一个完美的上升和下降沿时间正是经常在瞬间发生的，绝不会有所不同。这当然是不可能的，因为即使是最好的振荡器也会由于噪音和其他来源的实际组件构建不完善。高品质，低相位噪声晶体振荡器将抖动小于35皮秒（ps ）的时期，积累了许多以百万计的由热噪声引起的抖动时钟边缘，不稳定的电子振荡器，外部干扰通过电源，甚至输出连接。其他影响因素包括外部磁场或射频电从附近的发射机，这将有助于抖动影响振荡器的输出干扰领域。即使是一个简单的放大器，
逆变器，或将有助于缓冲抖动信号。因此DDS 的设备输出的将增加一定量的抖动。由于每个时钟将已经有一定抖动，选择一个低抖动振荡器是至关重要的开始。划分了一个高频率的时钟频率是一种减少抖动方法。随着频率的划分，相同数量的抖动一段较长的时间内发生，减少其对系统时间的百分比。一般而言，以减少抖动重要来源，避免引入额外的来源，应该使用一个稳定的参考时钟，避免使用信号和电路慢慢的杀死，并使用可行的最高频率，以便增加过采样。无杂散动态范围（SFDR ）是指信号和水平最高的比率（衡量分贝之间）的最高级别，在频谱信号包括相关的谐波频率分量。对于最好的无杂散动态范围，必须首先具有高品质的振荡器。SFDR 是一个重要的规范和应用渠道的应用程序，通信频谱的频率与其他被共享。如果发射机的输出发送到其他频段的杂散 图9 典型的AD9834输出相位噪声图 输出频率为2兆赫,时钟是50M 赫兹。
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信号，他们可能会损坏邻近信号或中断信号。
(a)频率为16.667MHz (b)频率为4.8MHz
图10 控制时钟为50MHz 的AD9834输出
输出时钟为50的典型情节取自AD9834是在图10所示。输出频率正好是1/3的主时钟频率（MCLK ）。由于频率明智的选择，有在25MHz 的窗口没有谐
波频率，至少有80dB 以下的信号（SFDR=80dB ）。较低的频率设定在（b ）有更多的点，形状的波形（但不够的，一个真正干净的波形），并给出了一个更为现实的图片，在二次谐波频率，大约是50dB 以下信号（SFDR=50dB ）。 你有更容易进行编程和DDS 的性能
预测的工具吗？
在线互动设计工具是一个选拔调整，给定一个时钟和期望输出频率
和阶段。选择所需的频率，以及理想
化的输出谐波滤波器后重建的外部
显示已被应用。一个例子是如图11
所示。表格数据也提供了重要的图像
和谐波。
这些工具将如何帮助我的DDS 方案？
所有这一切需要的是必要的频率输出和系统的参考时钟频率。该设计工具输出的是完整的编程序列所需方案的一部分。以图12为例，MCLK 的是设置为 图11 由互动设计工具提供屏幕上陈述