DS1230WP-100IND中文资料
FEATURES
10 years minimum data retention in the absence of external power
Data is automatically protected during power loss
Replaces 32k x 8 volatile static RAM, EEPROM or Flash memory Unlimited write cycles Low-power CMOS
Read and write access times as fast as 100ns Lithium energy source is electrically
disconnected to retain freshness until power is applied for the first time
Optional industrial temperature range of -40°C to +85°C, designated IND JEDEC standard 28-pin DIP package PowerCap Module (PCM) package - Directly surface-mountable module
- Replaceable snap-on PowerCap provides
lithium backup battery
- Standardized pinout for all nonvolatile
SRAM products
- Detachment feature on PowerCap allows
easy removal using a regular screwdriver
PIN ASSIGNMENT
PIN DESCRIPTION
A0 - A14 - Address Inputs DQ0 - DQ7 - Data In/Data Out CE - Chip Enable WE - Write Enable OE - Output Enable V CC - Power (+3.3V) GND - Ground NC - No Connect
DS1230W
3.3V 256k Nonvolatile SRAM
NC NC NC
NC V CC WE OE DQ7DQ6DQ5DQ4DQ3DQ2DQ1DQ0GND NC A14A13A12A11A10A9A8A7A6A5A4A3A2A1A0
NC 34-Pin PowerCap Module (PCM) (Uses DS9034PC PowerCap)
DESCRIPTION
The DS1230W 3.3V 256k Nonvolatile SRAM is a 262,144-bit, fully static, nonvolatile SRAM organized as 32,768 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry, which constantly monitors V CC for an out-of-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. DIP-package DS1230W devices can be used in place of existing 32k x 8 static RAMs directly conforming to the popular bytewide 28-pin DIP standard. The DIP devices also match the pinout of 28256 EEPROMs, allowing direct substitution while enhancing performance. DS1230W devices in the PowerCap Module package are directly surface mountable and are normally paired with a DS9034PC PowerCap to form a complete Nonvolatile SRAM Module. There is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing.
READ MODE
The DS1230W executes a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip Enable) and OE (Output Enable) are active (low). The unique address specified by the 15 address inputs (A0 – A14) defines which of the 32,768 bytes of data is to be accessed. Valid data will be available to the eight data output drivers within t ACC (Access Time) after the last address input signal is stable, providing that CE and OE (Output Enable) access times are also satisfied. If OE and CE access times are not satisfied, then data access must be measured from the later-occurring signal (CE or OE) and the limiting parameter is either t CO for CE or t OE for OE rather than address access.
WRITE MODE
The DS1230W executes a write cycle whenever the WE and CE signals are active (low) after address inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE. All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (t WR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output drivers are enabled (CE and OE active) then WE will disable the outputs in t ODW from its falling edge.
DATA RETENTION MODE
The DS1230W provides full functional capability for V CC greater than 3.0 volts and write protects by 2.8 volts. Data is maintained in the absence of V CC without any additional support circuitry. The nonvolatile static RAMs constantly monitor V CC. Should the supply voltage decay, the NV SRAMs automatically write protect themselves, all inputs become “don’t care,” and all outputs become high-impedance. As V CC falls below approximately 2.5 volts, a power switching circuit connects the lithium energy source to RAM to retain data. During power-up, when V CC rises above approximately 2.5 volts, the power switching circuit connects external V CC to RAM and disconnects the lithium energy source. Normal RAM operation can resume after V CC exceeds 3.0 volts.
FRESHNESS SEAL
Each DS1230W device is shipped from Dallas Semiconductor with its lithium energy source disconnected, guaranteeing full energy capacity. When V CC is first applied at a level greater than 3.0 volts, the lithium energy source is enabled for battery back-up operation.
PACKAGES
The DS1230W is available in two packages: 28-pin DIP and 34-pin PowerCap Module (PCM). The 28-
pin DIP integrates a lithium battery, an SRAM memory and a nonvolatile control function into a single
package with a JEDEC-standard, 600-mil DIP pinout. The 34-pin PowerCap Module integrates SRAM
memory and nonvolatile control into a module base along with contacts for connection to the lithium
battery in the DS9034PC PowerCap. The PowerCap Module package design allows a DS1230W to be
surface mounted without subjecting its lithium backup battery to destructive high-temperature reflow
soldering. After a DS1230W module base is reflow soldered, a DS9034PC PowerCap is snapped on top
of the base to form a complete Nonvolatile SRAM module. The DS9034PC is keyed to prevent improper
attachment. DS1230W module bases and DS9034PC PowerCaps are ordered separately and shipped in
separate containers. See the DS9034PC data sheet for further information.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground -0.3V to +4.6V
70°C, -40°C to +85°C for IND parts
Operating
to
Temperature 0°C
to
+70°C, -40°C to +85°C for IND parts
-40°C
Storage
Temperature
Soldering Temperature
10
seconds
for
DIP
Module
+260°C
Caution: Do Not Reflow (Wave or Hand Solder Only)
IPC/JEDEC
J-STD-020
Module
See
PowerCap
*This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS(t A: See Note 10)
NOTES
MAX
UNITS PARAMETER SYMBOL MIN
TYP
Power Supply Voltage V CC 3.0 3.3 3.6 V
Logic 1 V IH 2.2 V CC V
Logic 0 V IL 0.0 0.4 V
CAPACITANCE (t A=25°C)
NOTES
MAX
UNITS PARAMETER SYMBOL MIN
TYP
Input Capacitance C IN 5 10 pF
Input/Output Capacitance C I/O 5 10 pF
DS1230W READ CYCLE
SEE NOTE 1
WRITE CYCLE 1
SEE NOTES 2, 3, 4, 6, 7, 8 AND 12
WRITE CYCLE 2
SEE NOTES 2, 3, 4, 6, 7, 8 AND 13
POWER-DOWN/POWER-UP CONDITION
(t A=25°C)
UNITS
NOTES
TYP
PARAMETER SYMBOL MIN
MAX
Expected Data Retention Time t DR 10 years 9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1.WE is high for a Read Cycle.
2.OE = V IH or V IL. If OE = V IH during write cycle, the output buffers remain in a high-impedance state.
3.t WP is specified as the logical AND of CE and WE. t WP is measured from the latter of CE or WE
going low to the earlier of CE or WE going high.
4.t DH, t DS are measured from the earlier of CE or WE going high.
5.These parameters are sampled with a 5 pF load and are not 100% tested.
6.If the CE low transition occurs simultaneously with or latter than the WE low transition, the output
buffers remain in a high-impedance state during this period.
7.If the CE high transition occurs prior to or simultaneously with the WE high transition, the output
buffers remain in high-impedance state during this period.
8.If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition,
the output buffers remain in a high-impedance state during this period.
9.Each DS1230W has a built-in switch that disconnects the lithium source until V CC is first applied by
the user. The expected t DR is defined as accumulative time in the absence of V CC starting from the
time power is first applied by the user.
10.All AC and DC electrical characteristics are valid over the full operating temperature range. For
commercial products, this range is 0°C to 70°C. For industrial products (IND), this range is -40°C to
+85°C.
11.In a power-down condition the voltage on any pin may not exceed the voltage on V CC.
12.t WR1 and t DH1 are measured from WE going high.
13.t WR2 and t DH2 are measured from CE going high.
14.DS1230 modules are recognized by Underwriters Laboratory (U.L.?) under file E99151.
DC TEST CONDITIONS AC TEST CONDITIONS
Outputs Open Output Load: 100pF + 1TTL Gate
Cycle = 200ns for operating current Input Pulse Levels: 0 to 2.7V
All voltages are referenced to ground Timing Measurement Reference Levels
Input:
1.5V
Output: 1.5V
Input
pulse
Rise
and
Fall
Times:
5ns ORDERING INFORMATION
Part Number Temperature Range
Supply
Tolerance
Pin/Package Speed
Grade
DS1230W-100 0°C
to
+70°C
3.3V ± 0.3V 28 / 740 EMOD 100ns
DS1230W-100+ 0°C
to
+70°C
3.3V ± 0.3V 28 / 740 EMOD 100ns
DS1230WP-100 0°C
to
+70°C
3.3V ± 0.3V 34 / PowerCap* 100ns
DS1230WP-100+ 0°C
to
+70°C
3.3V ± 0.3V 34 / PowerCap* 100ns
DS1230W-100IND -40°C
to
+85°C
3.3V ± 0.3V 28 / 740 EMOD 100ns
DS1230W-100IND+ -40°C
to
+85°C
3.3V ± 0.3V 28 / 740 EMOD 100ns
DS1230WP-100IND -40°C
to
+85°C
3.3V ± 0.3V 34 / PowerCap* 100ns
DS1230WP-100IND+ -40°C
to
+85°C 3.3V ± 0.3V 34 / PowerCap* 100ns
DS1230W-150 0°C
to
+70°C
3.3V ± 0.3V 28 / 740 EMOD 150ns
DS1230W-150+ 0°C
to
+70°C
3.3V ± 0.3V 28 / 740 EMOD 150ns
DS1230WP-150 0°C
to
+70°C
3.3V ± 0.3V 34 / PowerCap* 150ns
DS1230WP-150+ 0°C
to
+70°C
3.3V ± 0.3V 34 / PowerCap* 150ns
+ Denotes lead-free/RoHS-compliant product.
* DS9034PC or DS9034PCI (PowerCap) required. Must be ordered separately.
PACKAGE INFORMATION
(For the latest package outline information, go to https://www.sodocs.net/doc/271171991.html,/DallasPackInfo.) PACKAGE TYPE DOCUMENT NO.
28 DIP 56-G0002-001
DS1230W NONVOLATILE SRAM, 34-PIN POWERCAP MODULE
INCHES
PKG
DIM MIN NOM MAX
A 0.920 0.925 0.930
B 0.980 0.985 0.990
C - -
0.080
D 0.052 0.055 0.058
E 0.048 0.050 0.052
F 0.015 0.020 0.025
G 0.020 0.025 0.030
DS1230W NONVOLATILE SRAM, 34-PIN POWERCAP MODULE WITH
POWERCAP
INCHES
PKG DIM MIN NOM MAX A 0.920 0.925 0.930 B 0.955 0.960 0.965 C 0.240 0.245 0.250 D 0.052 0.055 0.058 E 0.048 0.050 0.052 F 0.015 0.020 0.025 G
0.020 0.025 0.030
ASSEMBLY AND USE
Reflow soldering
Dallas Semiconductor recommends that PowerCap Module bases experience one pass through solder reflow oriented label-side up (live-bug).
Hand soldering and touch-up
Do not touch soldering iron to leads for more than 3 seconds. To solder, apply flux to the pad, heat the lead frame pad and apply solder. To remove part, apply flux, heat pad until solder reflows, and use a solder wick.
LPM replacement in a socket
To replace a Low Profile Module in a 68-pin PLCC socket, attach a DS9034PC PowerCap to a module base then insert the complete module into the socket one row of leads at a time, pushing only on the corners of the cap. Never apply force to the center of the device. To remove from a socket, use a PLCC
extraction tool and ensure that it does not hit or damage any of the module IC components. Do not use any other tool for extraction.
RECOMMENDED POWERCAP MODULE LAND PATTERN
INCHES
PKG
DIM MIN NOM
MAX
A - 1.050 -
B - 0.826 -
C - 0.050 -
D - 0.030 -
E - 0.112 -
RECOMMENDED POWERCAP MODULE SOLDER STENCIL
INCHES
PKG
DIM MIN NOM MAX
A - 1.050 -
B - 0.890 -
C - 0.050 -
D - 0.030 -
E - 0.080 -
REVISION HISTORY
REVISION DATE DESCRIPTION PAGES
CHANGED
121907 Added ordering information table.
Removed the DIP module package drawing and
dimension table.
8