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emmc_2gb_4gb_8gb_16gb_32gb_64gb-wt.pdf

e·MMC ? Memory

MTFC2GMVEA-0M WT, MTFC4GLVEA-0M WT, MTFC4GMVEA-1M WT,MTFC8GLVEA-1M WT, MTFC16GJVEC-2M WT, MTFC32GJVED-3M WT,MTFC64GJVDN-3M WT Features

?MultiMediaCard (MMC) controller and NAND Flash ?153- or 169-ball WFBGA/VFBGA/LFBGA (RoHS 6/6-compliant)?V CC : 2.7–3.6V

?V CCQ (dual voltage): 1.65–1.95V; 2.7–3.6V ?Temperature ranges

–Operating temperature: –25?C to +85?C –Storage temperature: –40?C to +85?C ?Typical current consumption

–Standby current: 110μA for 2GB, 120μA for 4GB,8GB, 16GB; 140μA for 32G; 160μA for 64GB –Active current (RMS): 70mA (2GB); 80mA (4GB,8GB, 16GB, 32GB, 64GB)

MMC-Specific Features

?JEDEC/MMC standard version 4.41-compliant (JEDEC Standard No. 84-A441) – SPI mode not supported (see https://www.sodocs.net/doc/221863584.html,/sites/default/files/docs/JESD84-A441.pdf )

–Advanced 11-signal interface

–x1, x4, and x8 I/Os, selectable by host –MMC mode operation

–Command classes: class 0 (basic); class 2 (block read); class 4 (block write); class 5 (erase);class 6 (write protection); class 7 (lock card)–MMC plus ? and MMC mobile ? protocols –Temporary write protection –52 MHz clock speed (MAX)

–Boot operation (high-speed boot)–Sleep mode

–Replay-protected memory block (RPMB)–Secure erase and trim –Hardware reset signal

–Multiple partitions with enhanced attribute –Permanent and power-on write protection –Double data rate (DDR) function –High-priority interrupt (HPI)

Figure 1: Micron e ·MMC Device

MMC-Specific Features (Continued)–Enhanced reliable write

–Configurable reliability settings –Background operation

–Fully enhanced configurable

–Backward-compatible with previous MMC modes

?ECC and block management implemented

e·MMC Performance

Table 1: MLC Partition Performance

Note: 1.Random access of 4KB chunk; sequential read access of 1MB chunk. Additional performance data, such as power consumption or timing for different device modes, will be provided in a separate document upon

customer request.

Ordering Information

Table 2: Ordering Information

Part Numbering Information

Micron?e·MMC memory devices are available in different configurations and densities. Verify valid part numbers by using Micron’s part catalog search at https://www.sodocs.net/doc/221863584.html,. To compare features and specifications by device type, visit https://www.sodocs.net/doc/221863584.html,/products. Contact the factory for devices not found.

Figure 2: Marketing Part Number Chart

MT FC 2G M V x EA - 0 M WT

Micron Technology

Product Family

FC = NAND Flash + controller

NAND Flash Density

2G = 2GB

4G = 4GB

8G = 8GB

16G = 16GB

32G = 32GB

64G = 64GB

NAND Flash Component Controller Revision Production Status

Blank = Production

ES = Engineering samples

MS = Mechanical samples

Operating Temperature Range Blank = 0°C to 70°C

WT = Standard (–25°C to +85°C)

IT = Extended (–40°C to +85)°C

SLC Enhanced Area

F = 40%

M = 100%

Maximum Boot Size

0 = 1MB

1 = 2MB

2 = 4MB

3 = 8MB

4 = 16MB

Package Codes (Pb-free)

DN = 169 LFBGA 14mm x 18mm x 1.4mm DQ = 100 LFBGA 14mm x 18mm x 1.4mm EA = 153 WFBGA 11.5mm x 13mm x 0.8mm EC = 169 WFBGA 14mm x 18mm x 0.8mm ED = 169 VFBGA 14mm x 18mm x 1.0mm

Reserved for Future Use

Mark Device

J MLC 64Gb, x8, 3.3V (25nm)

L MLC 32Gb, x8, 3.3V (25nm)

M MLC 16Gb, x8, 3.3V (25nm)

Mark (Rev.) Controller ID

T Enhanced

V Combo

Note: 1.Not all combinations are necessarily available. For a list of available devices or for further information on any aspect of these products, please contact your nearest Micron sales office.

General Description

Micron e·MMC is a communication and mass data storage device that includes a Multi-

MediaCard (MMC) interface, a NAND Flash component, and a controller on an ad-

vanced 11-signal bus, which is compliant with the MMC system specification. Its low

cost, small size, Flash technology independence, and high data throughput make

e·MMC ideal for embedded applications like set-top boxes, digital cameras/camcor-

ders, digital TVs, and a variety other consumer products.

The nonvolatile e·MMC draws no power to maintain stored data, delivers high perform-

ance across a wide range of operating temperatures, and resists shock and vibration dis-

ruption.

Signal Descriptions

Table 3: Signal Descriptions

Note: 1.V SS and V SSQ are connected internally.

153-Ball Signal Assignments

Figure 3: 153-Ball FBGA (top view, ball down)

1 2 3 4 5 6 7 8 9 10 11 12 13 14

Notes: 1.Some test pads on the device are not shown. They are not solder balls and are for Mi-

cron internal use only.

2.Some previous versions of the JEDEC product or mechanical specification had defined

reserved for future use (RFU) balls as no connect (NC) balls. NC balls assigned in the pre-

vious specifications could have been connected to ground on the system board. To ena-

ble new feature introduction, some of these balls are assigned as RFU in the v4.4 me-

chanical specification. Any new PCB footprint implementations should use the new ball

assignments and leave the RFU balls floating on the system board.

169-Ball Signal Assignments

Figure 4: 169-Ball FBGA (top view, ball down)

1 2 3 4 5 6 7 8 9 10 11 12 13 14

Notes: 1.Empty balls do not denote actual solder balls; they are position indicators only.

2.Some test pads on the device are not shown. They are not solder balls and are for Mi-

cron internal use only.

3.Some previous versions of the JEDEC product or mechanical specification had defined

reserved for future use (RFU) balls as no connect (NC) balls. NC balls assigned in the pre-vious specifications could have been connected to ground on the system board. To ena-ble new feature introduction, some of these balls are assigned as RFU in the v4.4 me-chanical specification. Any new PCB footprint implementations should use the new ball assignments and leave the RFU balls floating on the system board.

Package Dimensions

Figure 5: 153-Ball WFBGA – 11.5mm x 13.0mm x 0.8mm (Package Code: EA)

Note: 1.Dimensions are in millimeters.

Figure 6: 169-Ball WFBGA – 14.0mm x 18.00mm x 0.8mm (Package Code: EC)

Note: 1.Dimensions are in millimeters.

Figure 7: 169-Ball VFBGA – 14.0mm x 18.00mm x 1.0mm (Package Code: ED)

Note: 1.Dimensions are in millimeters.

Figure 8: 169-Ball LFBGA – 14.0mm x 18.00mm x 1.4mm (Package Code: DN)

Note: 1.Dimensions are in millimeters.

Architecture

Figure 9: e·MMC Functional Block Diagram

V V CC

V CCQ

DAT[7:0]

V SS1

V SSQ1

Note: 1.V SS and V SSQ are internally connected.

MMC Protocol Independent of NAND Flash Technology

The MMC specification defines the communication protocol between a host and a de-

vice. The protocol is independent of the NAND Flash features included in the device.

The device has an intelligent on-board controller that manages the MMC communica-

tion protocol.

The controller also handles block management functions such as logical block alloca-

tion and wear leveling. These management functions require complex algorithms and

depend entirely on NAND Flash technology (generation or memory cell type).

The device handles these management functions internally, making them invisible to

the host processor.

Defect and Error Management

Micron e·MMC incorporates advanced technology for defect and error management. If

a defective block is identified, the device completely replaces the defective block with

one of the spare blocks. This process is invisible to the host and does not affect data

space allocated for the user.

The device also includes a built-in error correction code (ECC) algorithm to ensure that

data integrity is maintained.

To make the best use of these advanced technologies and ensure proper data loading

and storage over the life of the device, the host must exercise the following precautions:

?Check the status after WRITE, READ, and ERASE operations.

?Avoid power-down during WRITE and ERASE operations.

CID Register

The card identification (CID) register is 128 bits wide. It contains the device identifica-

tion information used during the card identification phase as required by e·MMC proto-

col. Each device is created with a unique identification number.

Table 4: CID Register Field Parameters

CSD Register

The card-specific data (CSD) register provides information about accessing the device

contents. The CSD register defines the data format, error correction type, maximum da-

ta access time, and data transfer speed, as well as whether the DS register can be used.

The programmable part of the register (entries marked with W or E in the following ta-

ble) can be changed by the PROGRAM_CSD (CMD27) command.

Table 5: CSD Register Field Parameters

Table 5: CSD Register Field Parameters (Continued)

Notes: 1.R = Read-only

R/W = One-time programmable and readable

R/W/E = Multiple writable with value kept after a power cycle, assertion of the RST_n

signal, and any CMD0 reset, and readable

TBD = To be determined

2.Reserved bits should be read as 0.

ECSD Register

The 512-byte extended card-specific data (ECSD) register defines device properties and

selected modes. The most significant 320 bytes are the properties segment. This seg-

ment defines device capabilities and cannot be modified by the host. The lower 192

bytes are the modes segment. The modes segment defines the configuration in which

the device is working. The host can change the properties of modes segments using the

SWITCH command.

Table 6: ECSD Register Field Parameters

Table 6: ECSD Register Field Parameters (Continued)

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