FPGA可编程逻辑器件芯片EP2S180F1020I4中文规格书

Stratix II Architecture Figure2–55.Output TIming Diagram in DDR Mode

The Stratix II IOE operates in bidirectional DDR mode by combining the

DDR input and DDR output configurations. The negative-edge-clocked

OE register holds the OE signal inactive until the falling edge of the clock.

This is done to meet DDR SDRAM timing requirements.

External RAM Interfacing

In addition to the six I/O registers in each IOE, Stratix II devices also have

dedicated phase-shift circuitry for interfacing with external memory

interfaces. Stratix II devices support DDR and DDR2 SDRAM, QDR II

SRAM, RLDRAM II, and SDR SDRAM memory interfaces. In every

Stratix II device, the I/O banks at the top (banks 3 and 4) and bottom

(banks 7 and 8) of the device support DQ and DQS signals with DQ bus

modes of ×4, ×8/×9, ×16/×18, or ×32/×36. Table2–14 shows the number

of DQ and DQS buses that are supported per device.

Table2–14.DQS & DQ Bus Mode Support(Part 1 of2)Note(1)

Device Package Number of

×4Groups

Number of

×8/×9 Groups

Number of

×16/×18 Groups

Number of

×32/×36 Groups

EP2S15484-pin FineLine BGA8400 672-pin FineLine BGA18840 EP2S30484-pin FineLine BGA8400 672-pin FineLine BGA18840 EP2S60484-pin FineLine BGA8400 672-pin FineLine BGA18840

1,020-pin FineLine BGA361884

I/O Structure

A compensated delay element on each DQS pin automatically aligns input DQS synchronization signals with the data window of their

corresponding DQ data signals. The DQS signals drive a local DQS bus in the top and bottom I/O banks. This DQS bus is an additional resource to the I/O clocks and is used to clock DQ input registers with the DQS signal.

The Stratix II device has two phase-shifting reference circuits, one on the top and one on the bottom of the device. The circuit on the top controls the compensated delay elements for all DQS pins on the top. The circuit on the bottom controls the compensated delay elements for all DQS pins on the bottom.

Each phase-shifting reference circuit is driven by a system reference clock, which must have the same frequency as the DQS signal. Clock pins CLK[15..12]p feed the phase circuitry on the top of the device and clock pins CLK[7..4]p feed the phase circuitry on the bottom of the device. In addition, PLL clock outputs can also feed the phase-shifting reference circuits.

Figure 2–56 illustrates the phase-shift reference circuit control of each DQS delay shift on the top of the device. This same circuit is duplicated on the bottom of the device.

EP2S90

484-pin Hybrid FineLine BGA 8400780-pin FineLine BGA 188401,020-pin FineLine BGA 3618841,508-pin FineLine BGA

361884EP2S130780-pin FineLine BGA

188401,020-pin FineLine BGA 3618841,508-pin FineLine BGA

361884EP2S1801,020-pin FineLine BGA

3618841,508-pin FineLine BGA

36

18

8

4

Notes to Table 2–14:(1)

Check the pin table for each DQS/DQ group in the different modes.

Table 2–14.DQS & DQ Bus Mode Support (Part 2 of 2)Note (1)Device

Package

Number of ×4Groups

Number of ×8/×9 Groups

Number of ×16/×18 Groups Number of ×32/×36 Groups

Document

Revision History

Table2–27 shows the revision history for this chapter.

Table2–27.Document Revision History (Part 1 of2)

Date and

Document

Version

Changes Made Summary of Changes May 2007, v4.3Updated “Clock Control Block” section.—

Updated note in the “Clock Control Block” section.—

Deleted Tables 2-11 and 2-12.—

Updated notes to:

●Figure2–41

●Figure2–42

●Figure2–43

●Figure2–45

—

Updated notes to Table2–18.—

Moved Document Revision History to end of the chapter.—

August 2006,

v4.2

Updated Table2–18 with note.—

April 2006, v4.1●Updated T able2–13.

●Removed Note 2 from T able2–16.

●Updated “On-Chip Termination” section and T able2–19 to

include parallel termination with calibration information.

●Added new “On-Chip Parallel Termination with Calibration”

section.

●Updated Figure2–44.

●Added parallel on-

chip termination

description and

specification.

●Changed RCLK

names to match the

Quartus II software in

T able2–13.

December

2005, v4.0

Updated “Clock Control Block” section.—

July 2005, v3.1●Updated HyperT ransport technology information in Table2–18.

●Updated HyperT ransport technology information in

Figure2–57.

●Added information on the asynchronous clear signal.

—

May 2005, v3.0●Updated “Functional Description” section.

●Updated T able2–3.

●Updated “Clock Control Block” section.

●Updated T ables2–17 through 2–19.

●Updated T ables2–20 through 2–22.

●Updated Figure2–57.

—

March 2005, 2.1●Updated “Functional Description” section.

●Updated T able2–3.

—