RK2808_-A_ DATASHEET brief V1.1

RK2808
Brief Technical Reference Manual
Rev 1.1
RK2808 (-A) Technical Reference Manual Brief
Revision 1.1 Jan 2010
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RK2808
Brief Technical Reference Manual
Rev 1.1
Revision History
Date 2009-09-07 2009-09-09 2010-01-13 2010-03-3 Revision 0.1 0.2 1.0 1.1 Initial Release Add PIN Description Add RK2808-A PIN Description Modify MAX frequency Add note about PIN difference between RK2808 and RK2808-A. Description
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RK2808
Brief Technical Reference Manual
Rev 1.1
TABLE OF CONTENT
Revision History ............................................................................................... 2 TABLE OF CONTENT .......................................................................................... 3 Chapter 1 Introduction ..................................................................................... 4 1.1 Overview .......................................................................................... 4 1.2 RK28 Features................................................................................... 4 1.3 RK1000 Features ............................................................................... 8 1.4 Package ........................................................................................... 9 1.5 Block Diagram ................................................................................... 9 1.6 MCP Diagram .................................................................................. 12 Chapter 2 Pin Description ............................................................................... 13 2.1 PIN Placement................................................................................. 13 2.2 PIN Description................................................................................ 17 2.3 BGA324 package outline ................................................................... 25 Chapter 3 Port Multiplexer.............................................................................. 26 3.1 Overview ........................................................................................ 26 3.2 Detailed description for IO MUX ......................................................... 26 3.3 Detailed description for LCD port........................................................ 30 Chapter 4 Hardware Information.................................................................... 31 4.1 Oscillator Connection........................................................................ 31 4.2 USB PHY Connection ........................................................................ 32 4.3 Power up Sequence for power supply.................................................. 32 4.4 Power on reset Descriptions .............................................................. 32 Chapter 5 Electrical Specification ................................................................... 34 5.1 Recommended Operating Conditions................................................... 34 5.2 Electrical Characteristics ................................................................... 34
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RK2808
Brief Technical Reference Manual
Rev 1.1
Chapter 1 Introduction
1.1 Overview
RK2808 is a highly-integrated, high-performance, low-power digital multimedia processor which is based on Dual Core (DSP+CPU) architecture with hardware accelerator. It is designed for multimedia product applications such as MID, GPS and Mobile AP etc. RK2808 can support decode and encode for various types of video standards such as H.264/RMVB/MPEG-4/AVS/WMV9 by software and dedicated coprocessors. Specially, highest performace for video decode will reach fluent replay for video with H.264 @ 1280x720 formats. By providing a complete set of peripheral interface, RK2808 can support very flexible applications, including SDRAM, Nor Flash, Nand Flash, LCDC , Sensor, USB OTG , SD/MMC, High-speed ADC, TS, I2C, I2S, UART, SPI master, SPI slave, PWM etc. Specially, RK2808 is compatible with multi-format mobile-TV standards such as CMMB,T-DMB with high-performance hardware coprocessor. RK2808-A is a single chip, and RK2808 is MCP package that embed RK1000 analog companion chip, which included Audio CODEC, Video DAC and high-speed ADC functions.
1.2 RK28 Features
System Operation Dual Core Architecture (ARM926EJC + DSP) Support system boot sequentially from ARM to DSP Support address remap function For two cores, all modules have unified address space ARM9 JTAG debug method Selectable booting method Boot from NOR Flash Boot from Embedded ROM (default) Memory Organization Internal memory space for ARM processor Internal 16KB SRAM for ARM9 ICache Internal 16KB SRAM for ARM9 DCache Internal 8KB SRAM for ARM9 ITCM Internal 16KB SRAM for ARM9 DTCM Internal memory space for DSP processor Internal 64KB SRAM for DSP Instruction L1 Memory (Also config as 32KB Memory+32KB ICache by software) Internal 64KB SRAM for DSP Data L1 Memory Internal 64KB SRAM for DSP Instruction L2 Memory Internal 64KB SRAM for DSP Data L2 Memory Embedded 8KB ROM for ARM9 Boot Embedded 2KB SRAM for communication between two cores Embedded 90KB SRAM for share among ARM,DSP Communication between two cores Support share memory and interactive interrupt method to complete communication Processor Interface Unit (PIU) Built-in three Command/reply protocols registers and three Semaphore registers to accessed by two cores Support three semaphore-related interrupts and one command-reply-related interrupt between two cores Clock & Power Management Three on-chip PLLs for ARM9 subsystem, DSP subsystem and Other logic
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Brief Technical Reference Manual
Rev 1.1
Support different DSP Core and internal AHB Bus clock ratio: 1:1, 1:2, 1:3, 1:4, up to 1:16 mode Support different DSP internal AHB Bus and internal APB Bus clock ratio: 1:1, 1:2, 1:3, 1:4, up to 1:16 mode Support different ARM9 core and AHB Bus clock ratio: 1:1, 1:2, 1:3 and 1:4 mode Support different ARM AHB Bus and ARM APB Bus clock ratio: 1:1, 1:2 and 1:4 modes 5 types of work modes by clock gating to save power : Normal mode : Normal operating mode Slow mode : Low frequency clock (24MHz) without PLL Idle mode : The clock for only CPU is stopped , Wake up by any interrupts to CPU from idle mode Sleep mode : The clock for only DSP is stopped , Wake up from sleep mode by some interrupts to DSP or register set from CPU Stop mode : All clocks will be stopped , and SDRAM into Self-refresh, all PLLs into power-down mode, Wake up from stop mode by external pin or RTC alarm interrupt Support power supply shut down for 4 domain separately Memory Interface Static/SDRAM Memory controller Dynamic memory interface support , including SDR-SDRAM and Mobile SDRAM Asynchronous static memory device support including SRAM, ROM and Nor Flash with or without asynchronous page mode Support 1 chip selects for (Mobile) SDRAM and 2 chip selects for static memory Support 32bits data bus (Mobile) SDRAM and 8/16 bits data bus static memory Support industrial standard (Mobile) SDRAM from 16MB to 128 MB devices 4Mbytes access space per static memory support Support (Mobile) SDRAM and Static Memory power-down mode Support (Mobile) SDRAM self-refresh mode Programmable arbitration priority for 5 slave data ports Nand Flash controller Support 4 chip selects for nand flash support 8bits wide data Flexible CPU interface support Embedded 4x512B size buffer to improve performace Support internal DMA transfer from/to flash 512B、2KB、4KB page size support Support hardware ECC SD/MMC controller Two Embedded SD/MMC Controllers, one is 4bit data bus , another is 8bit data bus Compliant with SD Memory/SDIO with 1bit and 4bit data bus Compliant with MMC V3.3 and V4.0 with 1/4/8bit data bus Support combined single 32x32bits FIFO for both transmit and receive operations Support FIFO over-run and under-run prevention by stopping card clock Variable SD/MMC card clock rate 0 – 52 MHz which depends on AHB clock frequency Controllable SD/MMC card clock to save power consumption Support card detection and initialization , and write protection
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Brief Technical Reference Manual Support transfer block size of 1 to 65365Bytes DMA based or Interrupt based operation
Rev 1.1
VIDEO interface Sensor controller Support 24MHz, 48MHz, 27MHz clock input Support CCIR656 PAL/NTSC Support YUYV and UYVY format input Support YUV 4:2:2 and YUV 4:2:0 format output Programmable Hsync and Vsync porality Support 8 MegaPixels LCD controller Embedded DMA function Support one SCALE window and one no SCALE window YUV422/YUV420/RGB565/RGB888 Input are Supported in SCALE window RGB565/RGB888 Input and 4 AREAS are Supported in NO SCALE window Support Virtual Display Build in scaler engine from 1/8 to 8 Support 16 grade alpha blending and transparent operation. Support Blank/Black Function Support LCD Pannel resolution up to 1280x760 Compatible with MCU Pannel Support MCU PANNEL Bypass Mode and SCALE Mode Compatible with RGB Delta/no-Delta Pannel Compatible with RGB Series/Parallel 24bits (max) Output Compatible with CCIR656 output Support Interlace and Progressive Output Support LCDC interface high-z control Support LCDC interface bypass from Host interface DMA Controller Two DMA Controllers in chip DW_DMA Controller integrated inside ARM9 subsystem Three DMA Channels support to use by audio , sd/mmc and system data transfer 8 hardware request handshaking support Support hardware and software trigger DMA transfer mode Build-in 3 data FIFO : 64Bytes/32Bytes/16Bytes Scatter/Gather transfer support LLP transfer support Two masters for on-the-fly support The master interface only support undefined length INCR transfer 3D-DMA Controller(XDMA) integrated inside DSP subsystem This DMA focus on data transfer for video process and mobile TV application 16 configurable DMA channels, 4 channels support 3-dimensional data transfer 8/16/32/64bit data transfer support and configurable burst length (INCR/INCR4/INCR8) Programmable source and destination addresses with a post-modification option Configurable external channel triggering (edge or level) Support chaining-channels ,linked list-transfer and auto-channel initialization operating mode Pause and resume operations supported to save power Eight-stage memory buffer FIFO
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Rev 1.1
Interrupt Controller Two Interrupt Controller in chip DW_INTC integrated inside ARM9 subsystem Support 32 IRQ normal interrupt sources and 4 FIQ fast interrupt sources Vectored interrupts support Software interrupts support Programmable interrupt priorities Programmable High/Low Level sensitive or Negative / Positive edge triggered interrupts ICU (Interrupt Control unit) integrated inside DSP subsystem 48 interrupt sources , each may be linked to different interrupt inputs for DSP core Software triggering to all 48 interrupt sources Configurable source interrupt polarity (low/high) External interrupt source with software configuration to edge/level sensitive USB interface Complies with the OTG Supplement to the USB2.0 Specification Operates in High-Speed and Full-Speed mode Support Session Request Protocol(SRP) and Host Negotiation Protocol(HNP) Support 6 channels in host mode 6 endpoints, 3 in and 3 out Built-in one 1777 x 35bits FIFO Low_speed Peripheral interface Serial Peripheral Interface (SPI) Master Controller Support two slave devices connection Compatible with Motorola SPI , TI Synchronous Serial Protocol or National Semiconductor Microwire interface Dynamic control of serial bit rate of data transfer by programmable sclk_out frequency, which is half of PCLK in max mode FIFO depth for transmit and receive are also 16x16bits Programmable data item size ,from 4 to 16bits DMA based and interrupt based operation Serial Peripheral Interface (SPI) Slave Controller Compatible with Motorola SPI , TI Synchronous Serial Protocol or National Semiconductor Microwire interface Dynamic control of serial bit rate of data transfer by sclk_in from master device FIFO depth for transmit and receive are also 16x16bits Programmable data item size ,from 4 to 16bits DMA based and interrupt based operation UART0 Based on the 16550 industry standard UART0 support modem function and Serial data transfer Programmable serial data baud rate , up to 1.5Mbps DMA based and interrupt based operation FIFO depth for data transfer is 32x8bits UART1 Based on the 16550 industry standard UART1 support IrDA 1.0 SIR mode and Serial data transfer Programmable serial data baud rate , up to 1.5Mbps In IrDA SIR mode, support configurable baud data rate up to 115.2K and a pulse duration as specified in the IrDA physical layer specification DMA based and interrupt based operation FIFO depth for data transfer is 32x8bits
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Brief Technical Reference Manual
Rev 1.1
I2C controller 2 I2C controllers integrated in chip Multi masters operation support Software programmable clock frequency and transfer rate up to 100Kbit/s in standard mode or up to 400Kbit/s in Fast mode Supports 7 bits and 10 bits addressing modes I2S Support mono/stereo audio file Support audio resolution: 8, 16 bits Support audio sample rate from 32KHz to 96 KHz Support I2S, Left-Justified and Right-Justified digital serial data format PWM Built-in three 32 bit timer modulers Programmable counter Chained timer for long period purpose 4-channel 32-bit timer with Pulse Width Modulation (PWM) Programmable duty-cycle, and frequency output General Purpose IO (GPIO) Support 96 individually programmable input/output pins 16 GPIOs with external interrupt capability Timers in CPU system Built-in Three 32 bits timer modules Support for two operation modes : free-running and user-defined count Timers in DSP system Built-in two 32 bits timer modules Support for 5 various counting modes : Single Count mode, Auto-restart mode , Free-running , Event Count mode and Watchdog Timer mode Pulse Width Modulation(PWM) mechanism Three possible input clock signals: internal , external and cascaded Watchdog Timer (WDT) Watchdog function (Generate a system reset or an interrupt) Built-in 32 bits programmable counter Analog IP interface ADC Converter 3-channel single-ended 10-bit 1MSPS Successive Approximation Register (SAR) analog-to-digital converter No off-chip components required DNL less than +/-1 LSB , INL less than +/-1.5 LSB Supply 2.8V to 3.6V for analog interface Operation Temperature Range -10°C to 60°C Operation Voltage Range Core: 1.2V I/O : 3.3V/2.5V/1.8V (2.5V for USB OTG PHY, 1.8V for Mobile SDRAM)
1.3 RK1000 Features
Interface I2C interface, which connect to RK28 I2C0 device. RGB LCD interface, connect to RK28 LCDC port. I2S interface, connect RK28 I2S port. TV-OUT PAL/NTSC-CVBS/YPbPr traditional TV encoder Support ITU-BT656/ ITU-BT601 standard
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Brief Technical Reference Manual Support progressive RGB interface 576p/480p-YPbPr SDTV encoder 720p-YPbPr HDTV encoder 3 channel 10bit Video-DACs CODEC Complete Stero/Mon Microphone interface DAC and On-chip Headphone Driver >20mW output power on 32Ω/3.3v THD+N at 20mW, SNR>95dB with 32Ω load No DC blocking capacitors required(capless mode) Seperately mixed mono output 256 x Fs/384 x Fs Master clock rates, up to 24MHz Audio sample rates: 8 to 96kS/s Less than -80dBc out-of-band Noise High-Speed ADC Two 10-bits ADCs Sampling Rate: 10~60Msps Input: differential, 1.8 V peak-to-peak differential Power Dissipation: 12~60 mW (typical) Dynamic Performance: 60 dB SFDR and 57 dB SINAD Linearity: <1.5 LSB INL <1 LSB DNL, no missing codes User-Programmable Bias Current of Pipelined Stages Operation Temperature Range -10°C to 60°C Operation Voltage Range Core: 1.8V I/O : 3.3V
Rev 1.1
1.4 Package
RK2808-A TFBGA324 (13mmX13mm body size) RK2808 TFBGA324 (13mmX13mm body size) Note: RK2808 and RK2808-A is PIN to PIN compatible except RK1000 PINs.
1.5 RK28 Block Diagram
The following figure shows block diagram of RK28. RK28 can be divided into two sub system: DSP System and CPU System. DSP System XDMA : three-dimensional DMA , used to data transfer for video decoder or other algorithm High-Speed ADC Interface: focus on completing data reveiver from tuner in DVB-T, DAB, T-DMB, GPS application with software method. ICU : Interrupt controller for DSP processor PIU : processor interface unit, used to complete communication between DSP and CPU PMU ： power management unit, used to control clock and reset to save power for modules inside DSP system General reg file : focus on general control on DSP system by software method, composed of some register groups Share Memx : can be accessed by DSP , CPU or Demodulator, which is switched by software programm
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Brief Technical Reference Manual
Rev 1.1
CPU System DW_DMA : used to data transfer for audio and low-speed peripheral SCU : focus on clock gating , clock frequency switch, reset control , power on/off and system mode switch for CPU system to save power PMU : used to complete power on/off switch control for RK2808 INTC : Interrupt controller for CPU processor General reg file: focus on general control on CPU system by software method, composed of some register groups, including IO mux control,IO PAD pull up/down control and other system control signals .
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Brief Technical Reference Manual
Rev 1.1
RK2808 Block Diagram
AHB Bus
XDMA DSP High-Speed ADC interface L1 IMEM (64K) L2 MEM_1 (64K) L1 DMEM (64K) L2 MEM_2 (64K)
APB Bus
DSP System
General Reg file
Interrupt Controller Unit (ICU)
Timer x 2
HardWare Accellerator for Demodulator PMU
GPIO
Share Mem0(20K) Share Mem1(64K)
PIU
USB OTG PHY USB OTG Controller SRAM (2K) Interrupt Controller (INTC) DW_DMA
CPU System
Host interface
AHB Bus Video Interface
Boot ROM(8K) ARM926EJC LCDC
Icache (16K) ITCM(8K)
Dcache(16K) DTCM(16K)
VIP
APB Bus
EXT Storage Memory interface
Nand Flash interface
Low Speed Peripheral interface
SDRAM Controller UART x 2 WDT SCU Mobile SDRAM Controller
SPI Master
PWM x 3
eFuse
I2C x 2
Timer x 3
SAR ADC
Nor Flash interface
I2S
RTC
GPIO x 2 SD/MMC x 2
General Reg file
SPI Slave
PMU
Fig. 1-1 RK28 Block Diagram
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Brief Technical Reference Manual
Rev 1.1
1.6 RK2808 MCP(RK28+RK1000) Diagram
Ext CO D EC I2 S
A U D IO C O D E C
I2 S
I2 C
I2 C 0
HSADC
H S A D C IF
V ID E O E N C O D E R & V ID E O D A C
LCD C
RK1000
R K 2 8 c h ip RK2808 LCD TFT
Fig. 1-2 Rk2808 MCP(RK28+RK1000) Block Diagram
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Brief Technical Reference Manual
Rev 1.1
Chapter 2 Pin Description
2.1 RK2808 PIN Placement
1 A HOST_ D[8] 2 TCK 3 TDI 4 TDO 5 VIP_DI N[6] 6 HOST_ D[0] 7 HOST_ D[3] 8 NPOR 9 GPIO_F [5]/PW M3 HOST_ ADDR[ 1] HOST_ ADDR[ 0] 10 GPIO_E [1]/SPI 1_CLKI N PF7/SP I1_TXD 11 GPIO_E [2]/SPI 1_SS_I N PE3/SP I1_RXD PH6/EX T_IQ_I NDEX 12 TEST 13 HSAD_I _D[6] 14 PB1/SM _CS1/S D0_PC A HSADC _CLKIN / PH7 RECOV ER PE7/UA RT1_SI R_OUT/ I2C1_S CL I2S_CL K GPS_C LK/HSA DC_CL K PB6/SP I0_TXD /SD0_ D6 NC 15 PB2/UA RT0_CT S HOST_ D[12] 16 PB3/UA RT0_RT S HOST_ D[13] 17 HOST_ D[15] 18 PF1/UA RT1_TX /CX_T1 _PWM PF0/UA RT1_R X/CX_T 0_PWM HOST_I NT A
B
HOST_ D[9] LCDC_ HSYNC /MCU_ WE LCDC_ D[17]
OPMOD E[1] LCDC_ DCLK/ MCU_R S LCDC_ VSYNC/ MCU_C S
VIP_DI N[0]
VIP_DI N[2]
VIP_DI N[3]
VIP_DI N[7]
HOST_ D[2] PF6/VI P_CLK OUT
EXTMS DR_SE L VIP_CL KIN
EWAKE UP_ST OP EWAKE UP_PO WER
HSAD_I _D[7] HSAD_I _D[8]/ TS_VAL ID HSAD_I _D[9]/ TS_FAI L PE6/UA RT1_SI R_IN/I 2C1_S DA VDDCO RE4
HOST_ D[14]
B
C
TRST_ N
TMS
HOST_ D[11]
BTMOD E
PWM0/ PF2
I2S_LR CK
I2S_SD O
I2S_SD I
C
D
LCDC_ DE
HOST_ D[10]
VIP_DI N[4]
VIP_DI N[5]
HOST_ D[1]
VIP_HR EF
HOST_ D[7]
HSAD_I _D[0]
HSAD_I _D[2]
HSAD_I _D[4]
I2S_BC K
I2C0_S CL/PE5
I2C0_S DA/PE4
HOST_ RDN
D
E
LCDC_ D[13]
LCDC_ D[14]
LCDC_ D[15]
LCDC_ D[16]
VIP_DI N[1]
VCCIO6
EXTCLK
VIP_VS YNC
HOST_ D[6]
HSAD_I _D[1]
HSAD_I _D[3]
HSAD_I _D[5]
SD1_D 3/PG6
PB0/SP I0_CS1 /SD1_P CA SD1_D 0/PG3 PG1/UA RT0_TX /SD1_ WP XOUT2 4M VDDA_ DSPPLL VSSA_ ARMPLL SD0_D 3/PH4 SD0_C MD/PH 0
HOST_ CSN
HOST_ WRN
E
F
LCDC_ D[21]
LCDC_ D[22]
LCDC_ D[23]
LCDC_ D[12]
RTCK
VDDCO RE6
VDDCO RE5
HOST_ D[4]
HOST_ D[5]
AVDD1 8
ADC_V RP
VSSCO RE4
SD1_C MD/PG 2 PB7/SP I0_RXD /SD0_ D7 XIN24 M
SD1_D 1/PG4 PG0/UA RT0_R X/SD1_ DET PB4/SP I0_CS0 /SD0_ D4 VSSA_ DSPPLL VDDA_ ARMPLL SD0_D ET/PW M1/PF3 SD0_D 0/PH1
SD1_D 2/PG5
F
G
LCDC_ D[8]
LCDC_ D[9]
LCDC_ D[10]
LCDC_ D[11]
OPMOD E[0]
VCCIO1
VCCIO5
VSSCO RE5
ADC0_ VIN
ADC_V CM
ADC1_ VIN
VSSIO4
VCCIO4
SD1_C LK/PG7 PB5/SP I0_CLK T/SD0_ D5 VSSA_ CODEC PLL PF4/PW M2/SD 0_WP SD0_C LK/PH5 SD0_D 1/PH2
G
H
LCDC_ D[4] LCDC_ D[0] SDR_D [0] SDR_D [1] SDR_D [7]
LCDC_ D[5] LCDC_ D[1] SDR_C LK SDR_D [2] SDR_D [8]
LCDC_ D[6] LCDC_ D[2] VDDSD R1 SDR_D [3] SDR_D [9]
LCDC_ D[7] LCDC_ D[3] VSSSD R1 SDR_D [4] SDR_D [11]
VDDCO RE1 LCDC_ D[20] LCDC_ D[19] SDR_D [5] SDR_D [10]
VSSIO1
VSSIO6
VSSIO5
ADC0_ VIP
AVSS1
ADC1_ VIP
ADC_V RN
VSSAO
H
J
VSSCO RE6 LCDC_ D[18] SDR_D [6] VDDSD R2
VSSCO RE1 VSSSD R2 RSTN CLK_SE L
VSSCO RE7 VDD18 AVDD3 3_1 VDAC_ B
VCCIO7
AOM VDAC_ R AVDD3 3_2 AVSS2
VDDAO VDAC_ COMP VDAC_ REXT VDAC_ REF
AOL
AOR
VSSIO3 CODEC _VMID CODEC _REF VCCIO3
PE0 VDDA_ CODEC PLL SD0_D 2/PH3 VSSCO RE3
J
K
VSSIO7
VSSA
VDDA MICBIA S MIC_IN
K
L
AVSS1 VDAC_ G
AIR
L
M
AIL
M
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SDR_D [12] SDR_D [17] SDR_D [21] SDR_D [25] SDR_D [26] SDR_D [28] 1 SDR_D [13] SDR_D [19] SDR_D [23] SDR_D [27] SDR_D [30] SDR_D [29] 2 SDR_D [15] SDR_D [18] SDR_D [22] SDR_B A[0] SDR_B A[1] SDR_D [31] 3
Brief Technical Reference Manual
SDR_D [14] SDR_D [20] SDR_D [24] SDR_A[ 3] SDR_A[ 0] SDR_A[ 1] 4 SDR_D [16] SDR_D QM[0] SDR_D QM[1] SDR_A[ 13] SDR_A[ 2] SDR_A[ 14] 5 VSSCO RE2 SDR_A[ 15] SDR_A[ 6] SDR_A[ 4] SDR_A[ 7] SDR_A[ 5] 6 VDDSD R3 SDR_A[ 9] SDR_A[ 8] SDR_D QM[3] SDR_D QM[2] SDR_A[ 16] 7 VSSSD R3 SDR_A[ 12] SDR_A[ 11] SDR_A[ 10] SDR_A[ 18] SDR_A[ 17] 8 VDDSD R4 SDR_C KE SDR_R ASN SDR_C ASN SDR_W EN SDR_C SN 9 SDR_A[ 19] SDR_A[ 20] RTCVD D33 ST0_W EN ST0_C S0 ST0_O EN 10
Rev 1.1
VSSSD R4 XOUT3 2K XIN32K RTCINT _OUT PWR_G OOD PWR_S TROBE 11 VSSA_ SARAD C USBPH Y_DVD D USBPH Y_AVD D33 VBUS VDDCO RE3 FLASH_ D[5] FLASH_ D[1] VDDA_ SARAD C SARAD C_AIN1 SARAD C_AIN2 15 FLASH_ RDY FLASH_ RDN FLASH_ D[4] FLASH_ D[0] VGATE _EFUSE FSOUR CE_EFU SE 16 FLASH_ WP FLASH_ WE FLASH_ D[7] FLASH_ D[6] FLASH_ D[2] FLASH_ D[3] 17 FLASH_ ALE FLASH_ CLE FLASH_ CS0 FLASH_ CS1 FLASH_ CS3 FLASH_ CS2 18
N
VSSIO2 VDDCO RE2 USBPH Y_DVS S RKELVI N DM
VCCIO2 OTG_D RVVBU S SARAD C_AIN0 USBPH Y_AVS S2 USBPH Y_AVS S1 USBPH Y_AVD D25 14
N
P
P
R
R
T
T
U
ID RTCVD D12 12
U
V
DP 13
V
Note: 1. 2.
The different color means the different function interface. Only the GPIO of port A and E can use as ARM interrupt port.
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Rev 1.1
2.2 RK2808-A PIN Placement
1 2 3 4 5 6 7 8 9 PF5/PW M3/DE M_PW M HOST_ ADDR1 HOST_ ADDR0 HOST_ D7 10 PE1/SP I_CLKI N PF7/SP I_TXD PWM0/ PF2 HSAD_ I_D0 11 PE2/SP I_SS_I N PE3/SP I_RXD PH6/EX T_IQ_I NDEX HSAD_ I_D2 12 13 14 PB1/SM_C S1/SD0_P CA HSADC_C LKIN/ PH7 15 16 17 18 PF1/UA RT1_T X/CX_T 1_PWM PF0/UA RT1_R X/CX_T 0_PWM HOST_ INT HOST_ RDN
A
HOST_ D8
TCK
TDI
TDO
VIP_D6
HOST_ D0
HOST_ D3
NPOR
TEST
HSAD_I_ D6
PB2/UART 0_CTS
PB3/UART 0_RTS
HOST_ D15
A
B
HOST_ D9 LCDC_ HSYNC LCDC_ D17/PC 1 LCDC_ D13/PD 5 LCDC_ D21/PC 5 LCDC_ D8/PD0
OPMOD E1 LCDC_ DCLK LCDC_ VSYNC LCDC_ D14/PD 6 LCDC_ D22/PC 6 LCDC_ D9/PD1
VIP_D0
VIP_D2
VIP_D3
VIP_D7
HOST_ D2 PF6/VI P_CLK OUT HOST_ D1
EXTMS DR_SE L VIP_CL KIN VIP_HR EF
EWAKE UP_ST OP EWAKE UP_PO WER HSAD_ I_D4
HSAD_I_ D7 HSAD_I_ D8/TS_VA LID HSAD_I_ D9/TS_FA IL PE6/UART 1_SIR_IN /I2C1_SD A VDDCORE 4
HOST_D1 2
HOST_D1 3
HOST_ D14 I2S_SD I I2C0_S DA/PE4
B
C
TRST_ N LCDC_ DE LCDC_ D15/PD 7 LCDC_ D23/PC 7 LCDC_ D10/PD 2 LCDC_ D6 LCDC_ D2 VDDSD R1 SDR_D 3 SDR_D 9 SDR_D 15
TMS
HOST_ D11
BTMOD E
RECOVER PE7/UART 1_SIR_OU T/I2C1_S CL I2S_CLK GPS_CLK/ HSADC_C LK PB6/SPI0 _TXD/SD0 _D6
I2S_LRCK
I2S_SDO
C
D
HOST_ D10 LCDC_ D16/PC 0 LCDC_ D12/PD 4 LCDC_ D11/PD 3 LCDC_ D7 LCDC_ D3 VSSSD R1 SDR_D 4 SDR_D 11 SDR_D 14
VIP_D4
VIP_D5
I2S_SCLK
I2C0_SCL /PE5 PB0/SPI0 _CS1/SD1 _PCA SD1_D0/P G3 PG1/UART 0_TX/SD1 _WP
D
E
VIP_D1
VCCIO 6 VDDCO RE6 VCCIO 1
EXTCL K VDDCO RE5 VCCIO 5
VIP_VS YNC HOST_ D4 VSSCO RE5
HOST_ D6 HOST_ D5
HSAD_ I_D1
HSAD_ I_D3
HSAD_ I_D5 VSSCO RE4 VSSIO 4
SD1_D3/P G6 SD1_CMD /PG2 PB7/SPI0 _RXD/SD 0_D7
HOST_ CSN SD1_D 1/PG4 PG0/U ART0_ RX/SD 1_DET PB4/SP I0_CS0 /SD0_ D4 VSSA_ DSPPLL VDDA_ ARMPL L SD0_D ET/PW M1/PF3 SD0_D 0/PH1 FLASH _WP
HOST_ WRN SD1_D 2/PG5 SD1_C LK/PG7 PB5/SP I0_CLK T/SD0_ D5 VSSA_ CODEC PLL PF4/PW M2/SD 0_WP SD0_C LK/PH5 SD0_D 1/PH2 FLASH _ALE
E
F
RTCK
NC
NC
F
G
OPMOD E0
NC
NC
NC
VCCIO4
G
H
LCDC_ D4 LCDC_ D0 SDR_D 0 SDR_D 1 SDR_D 7 SDR_D 12
LCDC_ D5 LCDC_ D1 SDR_C LK SDR_D 2 SDR_D 8 SDR_D 13
VDDCO RE1 LCDC_ D20/PC 4 LCDC_ D19/PC 3 SDR_D 5 SDR_D 10 SDR_D 16
VSSIO 1 VSSCO RE6 LCDC_ D18/PC 2 SDR_D 6 VDDSD R2 VSSCO RE2
VSSIO 6 VSSCO RE1 VSSSD R2
VSSIO 5
NC
NC
NC
NC
NC
NC
XIN24M
XOUT24M
H
J
NC
NC
NC
NC
NC
NC
VSSIO3
PE0
VDDA_DS PPLL VSSA_AR MPLL SD0_D3/P H4 SD0_CMD /PH0 FLASH_R DY
J
K
NC
NC
NC
NC
NC
NC
NC
VDDA_CO DECPLL SD0_D2/P H3 VSSCORE 3 VDDCORE 3
K
L
NC
NC
NC
NC
NC
NC
NC
NC
L
M
NC
NC
NC
NC
NC
NC VSSA_ SARAD C
NC
VCCIO3
M
N
VDDSD R3
VSSSD R3
VDDSD R4
SDR_A 19
VSSSD R4
VSSIO2
VCCIO2
N
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RK2808
Brief Technical Reference Manual
Rev 1.1
USBPH Y_DVD D USBPH Y_AVD D33 VBUS
P
SDR_D 17 SDR_D 21 SDR_D 25 SDR_D 26 SDR_D 28
SDR_D 19 SDR_D 23 SDR_D 27 SDR_D 30 SDR_D 29
SDR_D 18 SDR_D 22 SDR_B A0 SDR_B A1 SDR_D 31
SDR_D 20 SDR_D 24 SDR_A 3 SDR_A 0 SDR_A 1
SDR_D QM0 SDR_D QM1 SDR_A 13 SDR_A 2 SDR_A 14
SDR_A 15 SDR_A 6 SDR_A 4 SDR_A 7 SDR_A 5
SDR_A 9 SDR_A 8 SDR_D QM3 SDR_D QM2 SDR_A 16
SDR_A 12 SDR_A 11 SDR_A 10 SDR_A 18 SDR_A 17
SDR_C KE SDR_R ASN SDR_C ASN SDR_W EN SDR_C SN
SDR_A 20 RTCVD D33 ST0_W EN ST0_C S0 ST0_O EN
XOUT3 2K
VDDCORE 2 USBPHY_ DVSS
OTG_DRV VBUS SARADC_ AIN0 USBPHY_ AVSS2 USBPHY_ AVSS1 USBPHY_ AVDD25
FLASH_D 5 FLASH_D 1 VDDA_SA RADC SARADC_ AIN1 SARADC_ AIN2
FLASH_R DN FLASH_D 4 FLASH_D 0 VGATE_EF USE FSOURCE _EFUSE
FLASH _WRN FLASH _D7 FLASH _D6 FLASH _D2 FLASH _D3
FLASH _CLE FLASH 0_CSN FLASH _CS1/P A5 FLASH _CS3/P A7 FLASH _CS2/P A6 18
P
R
XIN32K
R
T
RTCINT _OUT PWR_G OOD PWR_S TROBE
RKELVIN
T
U
ID
DM
U
V
RTCVD D12
DP
V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Note: 1. 2. 3.
The different color means the different function interface. Only the GPIO of port A and E can use as ARM interrupt port. All of the pins is compatible with Rk2808 except NC pins.
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Brief Technical Reference Manual
Rev 1.1
2.2 PIN Description
The following table shows all of the pins for RK2808. The first column in the pin function description is default function after power on reset, and function in the last two columns will be implemented by software set. The detailed register descriptions are IOMUX_A_CON and IOMUX_B_CON in chapter 34. As for GPIO_n[i] (n = A~H; i = 0~7), we can control Pull up or Pull Down or no resistor for them by software set. The value for Pull up/down type in the following table is default after power on reset. The detailed register descriptions are in chapter 34.
Notes I --- input pins O --- output pins B --- bidirectional pins P --- power supply pins (digital and analog) G --- ground supply pins (digital and analog) A --- Analog IO pins OSC --- oscillator IO pins Table 2-1 RK2808 (RK2808-A)Pin Description
PIN LOCAT ION
PIN NAME
PIN TYPE (DEFA ULT)
PULL UP/DOWN (DEFAULT)
PIN FUNCTION DESCRIPTION (DEFAULT)
PIN FUNCTION DESCRIPTION (FUNCTION MUX1)
PIN FUNCTION DESCRIPTION (FUNCTION MUX2)
GLOBAL SIGNALS C12 EWAKEUP_POWER I PULL DOWN EXTERNAL WAKEUP SIGNAL FROM POWER OFF MODE, HIGH ACTIVE EXTERNAL WAKEUP SIGNAL FROM STOP MODE, HIGH ACTIVE EXT CLOCK INPUT MOBILE SDRAM SELECT 0: SDRAM 1: MOBILE SDRAM 0 : BOOT FROM ROM 1 : BOOT FROM NORFLASH POWER ON RESET, LOW ATIVE 00: ARM9 JTAG 01: DSP JTAG 10: ARM9+DSP JTAG 11: RESERVED TEST MODE SELECT,CONNECT TO GROUND FOR NORMAL OPERATION EFUSE U16 VGATE_EFUSE A N/A GATE POWER SUPPLY OF EFUSE, CONNECT TO VDD FOR READ OPERATION SOURCE POWER SUPPLY OF EFUSE, CONNECT TO GROUND FOR READ OPERATION JTAG F5 A2 A3 A4 C4 C3 RTCK TCK TDI TDO TMS TRST_N O I I O I I N/A PULL UP PULL UP N/A PULL UP PULL DOWN JTAG RTCK JTAG TCK JTAG TDI JTAG TDO JTAG TMS JTAG TRST SDRAM U4 V4 T8 R8 SDR_A[0] SDR_A[1] SDR_A[10] SDR_A[11] O O O O N/A N/A N/A N/A SDRAM/SRAM ADDR BIT0 SDRAM/SRAM ADDR BIT1 SDRAM/SRAM ADDR BIT10 SDRAM/SRAM ADDR BIT11
B12 E7 B8
EWAKEUP_STOP EXTCLK EXTMSDR_SEL
I I I
PULL DOWN PULL DOWN PULL DOWN
C6 A8 G5 B2
BTMODE NPOR OPMODE[0] OPMODE[1]
I I I I
PULL DOWN N/A PULL DOWN PULL DOWN
A12
TEST
I
PULL DOWN
V16
FSOURCE_EFUSE
A
N/A
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RK2808
P8 T5 V5 P6 V7 V8 U8 N10 U5 P10 T4 T6 V6 R6 U6 R7 P7 T3 U3 T9 P9 K2 V9 K1 L1 M5 M4 N1 N2 N4 N3 N5 P1 P3 P2 L2 P4 R1 R3 R2 R4 T1 U1 T2 V1 V2 L3 U2 V3 L4 L5 L6 M1 M2 M3 P5 SDR_A[12] SDR_A[13] SDR_A[14] SDR_A[15] SDR_A[16] SDR_A[17] SDR_A[18] SDR_A[19] SDR_A[2] SDR_A[20] SDR_A[3] SDR_A[4] SDR_A[5] SDR_A[6] SDR_A[7] SDR_A[8] SDR_A[9] SDR_BA[0] SDR_BA[1] SDR_CASN SDR_CKE SDR_CLK SDR_CSN SDR_D[0] SDR_D[1] SDR_D[10] SDR_D[11] SDR_D[12] SDR_D[13] SDR_D[14] SDR_D[15] SDR_D[16] SDR_D[17] SDR_D[18] SDR_D[19] SDR_D[2] SDR_D[20] SDR_D[21] SDR_D[22] SDR_D[23] SDR_D[24] SDR_D[25] SDR_D[26] SDR_D[27] SDR_D[28] SDR_D[29] SDR_D[3] SDR_D[30] SDR_D[31] SDR_D[4] SDR_D[5] SDR_D[6] SDR_D[7] SDR_D[8] SDR_D[9] SDR_DQM[0] O O O O O O O O O O O O O O O O O O O O O O O B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B O
Brief Technical Reference Manual
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A SDRAM/SRAM ADDR BIT12 SDRAM/SRAM ADDR BIT13 SDRAM/SRAM ADDR BIT14 SDRAM/SRAM ADDR BIT15 SDRAM/SRAM ADDR BIT16 SDRAM/SRAM ADDR BIT17 SDRAM/SRAM ADDR BIT18 SDRAM/SRAM ADDR BIT19 SDRAM/SRAM ADDR BIT2 SDRAM/SRAM ADDR BIT20 SDRAM/SRAM ADDR BIT3 SDRAM/SRAM ADDR BIT4 SDRAM/SRAM ADDR BIT5 SDRAM/SRAM ADDR BIT6 SDRAM/SRAM ADDR BIT7 SDRAM/SRAM ADDR BIT8 SDRAM/SRAM ADDR BIT9 SDRAM BAND ADDRESS BIT0 SDRAM BAND ADDRESS BIT1 SDRAM CASN SDRAM CLOCK ENABLE SDRAM CLOCK OUTPUT SDRAM CHIP SELECT SDRAM DATA BIT0 SDRAM DATA BIT1 SDRAM DATA BIT10 SDRAM DATA BIT11 SDRAM DATA BIT12 SDRAM DATA BIT13 SDRAM DATA BIT14 SDRAM DATA BIT15 SDRAM DATA BIT16 SDRAM DATA BIT17 SDRAM DATA BIT18 SDRAM DATA BIT19 SDRAM DATA BIT2 SDRAM DATA BIT20 SDRAM DATA BIT21 SDRAM DATA BIT22 SDRAM DATA BIT23 SDRAM DATA BIT24 SDRAM DATA BIT25 SDRAM DATA BIT26 SDRAM DATA BIT27 SDRAM DATA BIT28 SDRAM DATA BIT29 SDRAM DATA BIT3 SDRAM DATA BIT30 SDRAM DATA BIT31 SDRAM DATA BIT4 SDRAM DATA BIT5 SDRAM DATA BIT6 SDRAM DATA BIT7 SDRAM DATA BIT8 SDRAM DATA BIT9 SDRAM DQM BIT0
Rev 1.1
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RK2808
R5 U7 T7 R9 U9 U10 V10 T10 SDR_DQM[1] SDR_DQM[2] SDR_DQM[3] SDR_RASN SDR_WEN ST0_CS0 ST0_OEN ST0_WEN O O O O O O O O
Brief Technical Reference Manual
N/A N/A N/A N/A N/A N/A N/A N/A SDRAM DQM BIT1 SDRAM DQM BIT2 SDRAM DQM BIT3 SDRAM RASN SDRAM WEN SRAM CEN0 SRAM OEN SRAM WEN NAND
Rev 1.1
N18 P18 T18 V18 U18 T16 R15 U17 V17 R16 P15 T17 R17 P16 N16 N17 P17 R18
FLASH_ALE FLASH_CLE FLASH_CS1 FLASH_CS2 FLASH_CS3 FLASH_D[0] FLASH_D[1] FLASH_D[2] FLASH_D[3] FLASH_D[4] FLASH_D[5] FLASH_D[6] FLASH_D[7] FLASH_RDN FLASH_RDY FLASH_WP FLASH_WE FLASH_CS0
O O B B B B B B B B B B B O I O O O
N/A N/A PULL UP PULL UP PULL UP N/A N/A N/A N/A N/A N/A N/A N/A N/A PULL UP N/A N/A N/A
NAND FLASH ALE NAND FLASH CLE GPIO PORT A BIT5 GPIO PORT A BIT6 GPIO PORT A BIT7 NAND FLASH DATA BIT0 NAND FLASH DATA BIT1 NAND FLASH DATA BIT2 NAND FLASH DATA BIT3 NAND FLASH DATA BIT4 NAND FLASH DATA BIT5 NAND FLASH DATA BIT6 NAND FLASH DATA BIT7 NAND FLASH RDN NAND FLASH READY/BUSY SINGAL INPUT NAND FLASH WRITE PROTECT NAND FLASH WE NAND FLASH CHIP SELECT 0 LCD NAND FLASH CHIP SELECT 1 NAND FLASH CHIP SELECT 2 NAND FLASH CHIP SELECT 3
J1 J2 G3 G4 F4 E1 E2 E3 E4 D1 K6 K5 J3 J5 F1 F2 F3 J4 H1 H2 H3 H4 G1 G2 C2 D3
LCDC_D[0] LCDC_D[1] LCDC_D[10] LCDC_D[11] LCDC_D[12] LCDC_D[13] LCDC_D[14] LCDC_D[15] LCDC_D[16] LCDC_D[17] LCDC_D[18] LCDC_D[19] LCDC_D[2] LCDC_D[20] LCDC_D[21] LCDC_D[22] LCDC_D[23] LCDC_D[3] LCDC_D[4] LCDC_D[5] LCDC_D[6] LCDC_D[7] LCDC_D[8] LCDC_D[9] LCDC_DCLK/MCU_RS LCDC_DE
O O B B B B B B B B B B O B B B B O O O O O B B O B
N/A N/A PULL UP PULL UP PULL UP PULL UP PULL UP PULL UP PULL UP PULL UP PULL UP PULL UP N/A PULL UP PULL UP PULL UP PULL UP N/A N/A N/A N/A N/A PULL UP PULL UP N/A PULL DOWN
LCDC DATA BIT0 LCDC DATA BIT1 GPIO PORT D BIT2 GPIO PORT D BIT3 GPIO PORT D BIT4 GPIO PORT D BIT5 GPIO PORT D BIT6 GPIO PORT D BIT7 GPIO PORT C BIT0 GPIO PORT C BIT1 GPIO PORT C BIT2 GPIO PORT C BIT3 LCDC DATA BIT2 GPIO PORT C BIT4 GPIO PORT C BIT5 GPIO PORT C BIT6 GPIO PORT C BIT7 LCDC DATA BIT3 LCDC DATA BIT4 LCDC DATA BIT5 LCDC DATA BIT6 LCDC DATA BIT7 GPIO PORT D BIT0 GPIO PORT D BIT1 LCDC DOT CLOCK OUTAND RS SIGNAL FOR MCU PANEL GPIO2 BIT26 LCDC DATA ENABLE SIGNAL LCDC DATA BIT8 LCDC DATA BIT9 LCDC DATA BIT20 LCDC DATA BIT21 LCDC DATA BIT22 LCDC DATA BIT23 LCDC DATA BIT10 LCDC DATA BIT11 LCDC DATA BIT12 LCDC DATA BIT13 LCDC DATA BIT14 LCDC DATA BIT15 LCDC DATA BIT16 LCDC DATA BIT17 LCDC DATA BIT18 LCDC DATA BIT19
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RK2808
C1 LCDC_HSYNC/MCU_WE O
Brief Technical Reference Manual
N/A LCDC HORIZONTAL SYNC SIGNAL OUTPUT AND WE SIGNAL FOR MCU PANEL LCDC VERTICAL SYNC SIGNAL OUTPUT AND CS SIGNAL FOR MCU PANEL
Rev 1.1
D2
LCDC_VSYNC/MCU_CS
B
PULL DOWN
GPIO2 BIT25
HOST INTERFACE C9 HOST_ADDR[0] B PULL UP GPIO FOR DSP BIT8 HOST INTERFACE ADDRESS BIT0 HOST INTERFACE ADDRESS BIT1 HOST INTERFACE CHIP SELECT
B9 E17 A17 B7 B1 A6 D7 D4 C5 B15 B16 B17 A7 F8 F9 E9 D9 A1 C18
HOST_ADDR[1] HOST_CSN HOST_D[15] HOST_D[2] HOST_D[9] HOST_D[0] HOST_D[1] HOST_D[10] HOST_D[11] HOST_D[12] HOST_D[13] HOST_D[14] HOST_D[3] HOST_D[4] HOST_D[5] HOST_D[6] HOST_D[7] HOST_D[8] HOST_INT
B B B B B B B B B B B B B B B B B B B
PULL UP PULL UP PULL DOWN PULL UP PULL DOWN PULL UP PULL UP PULL DOWN PULL DOWN PULL DOWN PULL DOWN PULL DOWN PULL UP PULL UP PULL UP PULL UP PULL UP PULL DOWN PULL UP
GPIO FOR DSP BIT9 GPIO FOR DSP BIT10 HOST INTERFACE DATA BIT15 GPIO FOR DSP BIT2 HOST INTERFACE DATA BIT9 GPIO FOR DSP BIT0 GPIO FOR DSP BIT1 HOST INTERFACE BIT10 HOST INTERFACE BIT11 HOST INTERFACE BIT15 HOST INTERFACE BIT13 HOST INTERFACE BIT14 DATA DATA DATA DATA DATA
HOST INTERFACE DATA BIT2 HOST INTERFACE DATA BIT0 HOST INTERFACE DATA BIT1
GPIO FOR DSP BIT3 GPIO FOR DSP BIT4 GPIO FOR DSP BIT5 GPIO FOR DSP BIT6 GPIO FOR DSP BIT7 HOST INTERFACE DATA BIT8 GPIO FOR DSP BIT13
HOST INTERFACE BIT3 HOST INTERFACE BIT4 HOST INTERFACE BIT5 HOST INTERFACE BIT6 HOST INTERFACE BIT7
DATA DATA DATA DATA DATA
HOST INTERFACE INTERRUPT FROM CHIP TO HOST HOST INTERFACE READ VALID SIGNAL HOST INTERFACE WRITE VALID SIGNAL
D18
HOST_RDN
B
PULL UP
GPIO FOR DSP BIT11
E18
HOST_WRN
B
PULL UP
GPIO FOR DSP BIT12 USB
V14 R12 U14 T14 P12 R13 T12 T13 P14 U12 U13 V13
USBPHY_AVDD25 USBPHY_AVDD33 USBPHY_AVSS1 USBPHY_AVSS2 USBPHY_DVDD USBPHY_DVSS VBUS RKELVIN OTG_DRVVBUS ID DM DP
P P G G G G P A O I A A
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
USB ANALOG POWER SUPPLY (2.5V) USB ANALOG POWER SUPPLY (3.3V) USB ANALOG GROUND (0V) USB ANALOG GROUND (0V) USB DIGITAL POWER SUPPLY (1.2V) USB DIGITAL GROUND (0V) USB DEDECT INPUT OR 5V POWER SUPPLY FOR OTG FUNCTION TRANSMITTER RESISTOR TUNE PIN USB DRIVE VBUS POWER CONTROLE SIGNAL USB MINNI-RECEPTABLE IDENTIFIER USB D- SIGNAL USB D+ SIGNAL SRC ADC
R14 U15 V15
SARADC_AIN0 SARADC_AIN1 SARADC_AIN2
A A A
N/A N/A N/A
10BIT ADC CHANNEL0 INPUT 10BIT ADC CHANNEL1 INPUT 10BIT ADC CHANNEL2 INPUT
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