当前位置：搜档网 › Graphene-based nanoelectronics

Graphene-based nanoelectronics

Graphene-based Nanoelectronics

by Dr. Osama M. Nayfeh, Mr. Matthew Chin, Dr. Matthew Ervin,

Dr. James Wilson, Dr. Tony Ivanov, Dr. Robert Proie,

Dr. Barbara M. Nichols, Dr. Frank Crowne, and Dr. Stephen Kilpatrick

PI: Dr. Madan Dubey

Co-PIs: Dr. Raju Nambaru and Dr. Marc Ulrich

ARL-TR-5451 February

2011 Approved for public release; distribution unlimited.

NOTICES

Disclaimers

The findings in this report are not to be construed as an official Department of the Army position unless so designated by other authorized documents.

Citation of manufacturer’s or trade names does not constitute an official endorsement or approval of the use thereof.

Destroy this report when it is no longer needed. Do not return it to the originator.

Army Research Laboratory

Adelphi, MD 20783-1197

2011 ARL-TR-5451 February Graphene-based Nanoelectronics

Dr. Osama M. Nayfeh, Mr. Matthew Chin, Dr. Matthew Ervin,

Dr. James Wilson, Dr. Tony Ivanov, Dr. Robert Proie,

Dr. Barbara M. Nichols, Dr. Frank Crowne, and Dr. Stephen Kilpatrick

Sensors and Electron Devices Directorate, ARL

and

PI: Dr. Madan Dubey

Co-PIs: Dr. Raju Nambaru and Dr. Marc Ulrich

Sensors and Electron Devices Directorate, ARL

Approved for public release; distribution unlimited.

REPORT DOCUMENTATION PAGE Form Approved

OMB No. 0704-0188

Public reporting burden for this collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing the collection information. Send comments regarding this burden estimate or any other aspect of this collection of information, including suggestions for reducing the burden, to Department of Defense, Washington Headquarters Services, Directorate for Information Operations and Reports (0704-0188), 1215 Jefferson Davis Highway, Suite 1204, Arlington, VA 22202-4302. Respondents should be aware that notwithstanding any other provision of law, no person shall be subject to any penalty for failing to comply with a collection of information if it does not display a currently valid OMB control number.

PLEASE DO NOT RETURN YOUR FORM TO THE ABOVE ADDRESS.

1. REPORT DATE (DD-MM-YYYY) February 2011

2. REPORT TYPE

DSI

3. DATES COVERED (From - To)

October 2009 to September 2010

4. TITLE AND SUBTITLE

Graphene-based Nanoelectronics

5a. CONTRACT NUMBER

5b. GRANT NUMBER

5c. PROGRAM ELEMENT NUMBER

6. AUTHOR(S)

Dr. Osama M. Nayfeh, Mr. Matthew Chin, Dr. Matthew Ervin, Dr. James Wilson, Dr. Tony Ivanov, Dr. Robert Proie, Dr. Barbara M. Nichols, Dr. Frank Crowne, and Dr. Stephen Kilpatrick

PI: Dr. Madan Dubey

Co-PIs: Dr. Raju Nambaru and Dr. Marc Ulrich 5d. PROJECT NUMBER 5e. TASK NUMBER

5f. WORK UNIT NUMBER

7. PERFORMING ORGANIZATION NAME(S) AND ADDRESS(ES) U.S. Army Research Laboratory

ATTN: RDRL-SER-L

2800 Powder Mill Road

Adelphi MD 20783-1197 8. PERFORMING ORGANIZATION REPORT NUMBER

ARL-TR-5451

9. SPONSORING/MONITORING AGENCY NAME(S) AND ADDRESS(ES) 10. SPONSOR/MONITOR’S ACRONYM(S)

11. SPONSOR/MONITOR'S REPORT

NUMBER(S)

12. DISTRIBUTION/AVAILABILITY STATEMENT

Approved for public release; distribution unlimited.

13. SUPPLEMENTARY NOTES

14. ABSTRACT

A large program in graphene-based nanoelectronics has been initiated at the U.S. Army Research Laboratory (ARL) under the auspices of the ARL Director’s Strategic Initiative (DSI). An array of capabilities for graphene growth, characterization, device fabrication, and device modeling has been established, and expertise has been gained in all facets of the research. Significant results have been achieved, including the world’s highest reported f T for a graphene field-effect transistor (GFET) fabricated from chemical vapor deposition (CVD)-grown graphene; and a first-generation graphene-based supercapacitor. This research could potentially have enormous benefits for the American Soldier including smaller and more efficient power electronics and communication systems, transparent and flexible electronics, and wearable electronics.

15. SUBJECT TERMS

Graphene, FET, field effect transistor, supercapacitor

16. SECURITY CLASSIFICATION OF: 17. LIMITATION

ABSTRACT

18. NUMBER

PAGES

19a. NAME OF RESPONSIBLE PERSON

Madan Dubey

a. REPORT Unclassified

b. ABSTRACT

Unclassified

c. THIS PAGE

Unclassified

19b. TELEPHONE NUMBER (Include area code)

(301) 394-1186

Standard Form 298 (Rev. 8/98)

Prescribed by ANSI Std. Z39.18

Contents

List of Figures v Acknowledgments vii

1.Introduction 1

2.Graphene Growth and Characterization 4

2.1Chemical Vapor Deposition Furnaces (4)

2.2Growth on Copper (5)

2.3Growth on Nickel (7)

2.4Characterization by Raman Spectroscopy (8)

2.5Graphene Exfoliation (9)

2.5.1Overview and Purpose (9)

2.5.2Process Description (10)

3.Radio Frequency (RF) Top-Gated CVD Graphene Transistors 12

3.1Device Construction (12)

3.2DC and RF Performance (13)

4.Carbon Nanotube/Graphene Supercapacitors 16

4.1Background (16)

4.2Capacitor Evaluation (16)

4.3CNT Solution Comparison (17)

4.4Fabrication Method Comparison (17)

4.5Flexible Capacitors (18)

4.6Graphene Capacitors (19)

4.7Conclusions and Opportunities (19)

5.Simulation and Modeling 20

6.Conclusions 25

6.1Transitions (25)

6.2Future Research (25)

7.References 27 List of Symbols, Abbreviations, and Acronyms 31 Distribution List 33

List of Figures

Figure 1. Graphene is a 2-D building material for graphitic materials of all other dimensionalities. It can be wrapped up into 0-D buckyballs, rolled into 1-D nanotubes, or stacked into 3-D graphite (1). (2)

Figure 2. Four-step process for graphene growth on Cu foils. (6)

Figure 3. Transfer process of graphene grown on Cu foils to desired substrate. (7)

Figure 4. Optical microscopy image of graphene on Ni. The dark irregular patches are extra layers of graphene typically located at Ni grain boundaries (not visible). (8)

Figure 5. Raman spectra from a transferred graphene film: (a) optical image of a transferred graphene film originally grown on copper, and (b) the Raman spectra from five points on the image. The colored crosses on the optical image correspond to the colored Raman

spectra taken at the respective points. (9)

Figure 6. A pictorial of the mechanical exfoliation process. (a) Highly-oriented pyrolytic graphite flakes (“graphenium”) are used as the source material. (b) A special adhesive

film in the form of tape with extremely low residue is used to split the graphite flakes

along their crystal planes. This process is repeated several times until single- or few-

layer graphene flakes are produced. (c) The graphene flakes are then transferred to a Si

substrate with a 300-nm layer of thermally grown SiO2. (d) Optical microscopy is used to locate graphene areas on the substrate, and then Raman spectroscopy and AFM are

used to determine the number of graphene layers and their quality. (10)

Figure 7. Optical micrographs of two areas on 300 nm of SiO2 with graphene and graphite present. The yellow areas indicate the presence of thick, multilayer graphite, while the

blue areas indicate few-layer and even monolayer graphene. (11)

Figure 8. AFM images of mechanically exfoliated graphene at a step junction where the graphene flake transitions between differing numbers of layers. (11)

Figure 9. SEM image of a CVD graphene film between (Ti/Au) source/drain electrodes. (12)

Figure 10. DC measurements (I d vs. V gs) with V ds=5 V of a typical top-gated GFET with a gate length (L gate=3 μm) and gate-source/drain length of 1.5 μm. The device has an ALD-based Al2O3 top-gate dielectric with an evaporated SiO2 interfacial layer. The device has

a peak transconductance of 20 mS/mm, drive current of 0.5 A/mm, and a location of the

DP at ~5 V. (14)

Figure 11. RF measurements (gain (dB) vs. frequency) for a typical top-gated GFET with CVD graphene channel, with a gate-length of 3 μm and measured with increasing values of the gate-source voltage and with a V ds=5 V and a back-bias of 0 V. A measured

(extrinsic) current-gain cut-off frequency (f T) of 1 GHz is observed for these GFET

devices. This is a record frequency performance for CVD material. (15)

Figure 12. Specific capacitance as a function of deposition method. The diamonds are from samples made with the CNT solution merely shaken, while the “x” symbols are used to denote samples made from sonicated CNT solutions. (18)

Figure 13. Dual-gate graphene FET structure (42). (21)

Figure 14. I d versus V ds for simulator model. (22)

Figure 15. s d vs. V ds for simulator model. (22)

Figure 16. |g m| versus V ds for simulator model. (22)

Figure 17. I d versus V ds for V gst = 7.58 V. Red curve – uncorrected model; blue curve – corrected model. (23)

Figure 18. RF equivalent circuit for a double-gate graphene FET. (23)

Figure 19. Graphene-loaded capacitor. (24)

Figure 20. 2nd harmonic surface charge density vs. alternating current (AC) voltage. (24)

Acknowledgments

We gratefully acknowledge the skillful assistance of Greg Meissner in growing graphene in the nickel chemical vapor deposition (CVD) furnace and making optical micrographs of many of the resulting samples. We are also thankful to Carol Johnson, technical editor, Technical Publishing Branch, Adelphi Laboratory Center (ALC), for her skillful editing of the manuscript.

I NTENTIONALLY L EFT B LANK.

1. Introduction

Electronic phenomena in nanoscale structures have generated new challenges and opportunities for enabling new technologies never before realized. Recently, graphene has emerged as a novel material, especially for electronics, that could lead to devices in the quantum domain at room temperature (1–5). More generally, graphene represents a conceptually new class of materials that are only one atom thick (equivalent to 0.36 nm for graphene) (6), and which thus exhibit startlingly different phenomena from their traditional three-dimensional (3-D) analogs and which potentially offer unexplored capabilities for novel electronic devices and applications. Graphene is the name given to a flat monolayer of carbon atoms tightly packed into a two-dimensional

(2-D) honeycomb lattice, first isolated in 2004, and illustrated schematically in figure 1. It is the basic building block for graphitic materials of all other dimensionalities and can be wrapped up into zero-dimensional (0-D) fullerenes, rolled into one-dimensional (1-D) nanotubes, or stacked into 3-D graphite.

200,000 cm2/V-s (7), a high thermal conductivity of ~5 x 103 W/m-K (8), temperature stability to at least 2300 °C (but only ~500 °C in air [9]), extremely high tensile strength measured to be

1 TPa (10), quintessential flexibility, stretchability to 20% (11), a high breakdown current density exceeding 108 A/cm

2 (12), and superior radiation hardness (13). All of these qualities are desired in electronic materials. In addition to these advantageous characteristics, graphene also possesses very unique ambipolar properties (capable of conducting electrons when biased one direction and holes when biased in the other direction) that open up a whole new class of electronic devices.

Graphene lacks a bandgap in its energy band diagram, and therefore, exhibits metallic conductivity even in the limit of nominally zero carrier concentration. At the same time, most electronic applications rely on the presence of a gap between the valence and conduction bands. Several routes have been reported to induce and control such a gap in graphene. Some examples include using the effect of confined geometries such as quantum dots or nanoribbons, doping the

edge states or the bulk of the graphene, applying a transverse electric field to a bilayer of graphene (14), and exploiting the proximity effects from an adjacent substrate or insulator layer. Current research shows that graphene’s atomic interaction with an epitaxial silicon carbide (SiC) substrate can induce a splitting of up to 0.3 eV between the maximum of the valence and minimum of the conduction bands at the Dirac-point (15).

We at the U.S. Army Research Laboratory (ARL) are harnessing the electronic properties of this newly discovered material, finding ways to develop and exploit a new generation of electronic and sensor devices for Army-specific applications. While many in the field are exfoliating micron-sized sections of graphene from chunks of graphite to study its fundamental physics or for measurements of unipolar complementary metal-oxide-semiconductor (CMOS)-like devices to extend Moore’s Law, our approach is to synthesize our graphene using a manufacturable process, i.e., by chemical vapor deposition (CVD), and to study a new class of graphene devices and circuits that harness the unique ambipolar properties of graphene. Such ambipolar devices and circuits hold the promise of more efficient and smaller analog circuits, increased frequency ranges, lower power consumption, and higher data transmission speeds, all in a

transparent/invisible/durable/flexible form factor. This latter attribute could lead to wearable electronics woven into a Soldier’s uniform (so-called electronic textiles or “e-textiles”), for instance for wireless communications or to sense health and medical condition. Medical sensors using graphene-based e-textiles, in turn, could be used to wirelessly transmit information to a central command node, trigger automated drug delivery (e.g., insulin), or be incorporated within “smart bandages,” which could accelerate healing of wounds. Many of the military advantages listed above could be also transitioned to civilian and commercial usages, which could make a large impact on the day-to-day world in which we live.

Further, as more sophisticated electronics are deployed to the battlefield, energy requirements become a greater burden to the Soldier. Exploiting the unique properties of graphene, we are pursuing two avenues for solutions. First, as we have said, we are developing a new class of graphene-based nanoelectronic technology that would potentially replace larger, heavier, and power-hungry components in communications systems and portable electronics. Second, we are developing a new type of energy storage device called a supercapacitor, which uses graphene or carbon nanotubes (CNTs) and an electrolyte to produce ~100 times the specific power of batteries and fuel cells. Supercapacitors are capable of millions of charge/discharge cycles, rapid charge and discharge times, and high efficiencies. This research, in collaboration with Communications-Electronics Research Development and Engineering Center (CERDEC), aims to create a printable capacitor monolithically integrated with printable electronics to produce power for integrated electronic and sensor circuits.

In this first year of research under the ARL Director’s Strategic Initiative (DSI) program, we have focused on developing in-house capabilities and infrastructures for producing electronic-grade graphene, characterizing its properties by a number of metrology tools, fabricating graphene test structures and graphene field-effect transistors (GFETs) incorporating a large

variety of dielectric materials, testing these electronic structures and devices at DC to RF frequencies, exploring the use of graphene in supercapacitor devices for energy storage, and initiating efforts to model and simulate graphene device performance. Accordingly, the rest of this report is divided into the following sections: section 2: Graphene Growth and Characterization; section: Radio Frequency (RF) Top-Gated CVD Field-effect Transistors (FETs); section 4: Carbon Nanotube/Graphene Supercapacitors; section 5: Simulation and Modeling; and section 6: Conclusions.

Early on in our program, we identified two universities that were executing strong programs on graphene and that had established capabilities and directions that were well aligned with our own goals. The first is the Massachusetts Institute of Technology (MIT)―Profs. Palacios (16), Kong (17), Jarillo-Herrero (18), and Dresselhaus (19)), with significant progress in graphene-based ambipolar devices and circuits, as well as in graphene growth by CVD and the production of suitable starting structures for device fabrication. The second is Rice University―Prof. Ajayan (20), who has made exciting progress on some key building blocks for high performance graphene electronics, such as the co-synthesis of graphene with boron nitride (another purely 2-D monolayer and an excellent dielectric material for advanced GFET devices), and the discovery of how to make graphene repetitively reconfigurable between semiconducting and insulating states. Collaborative arrangements have been established with both of these institutions in order to enhance our efforts, and these are reflected in the report.

2. Graphene Growth and Characterization

2.1 Chemical Vapor Deposition Furnaces

The capability to produce graphene thin films in-house at ARL is important to the success of the DSI. Epitaxial graphene growth on SiC has been the primary graphene growth technique for over five years; however, in recent years, CVD of graphene on metal substrates has shown great promise. CVD offers lower processing temperatures and cheaper substrate materials, and is considerably less difficult to set up in a laboratory setting than a high temperature furnace for graphene growth on SiC.

Two CVD furnaces were established for in-house graphene growth: an atmospheric pressure chemical vapor deposition (APCVD) furnace and a low pressure chemical vapor deposition (LPCVD) furnace. APCVD graphene growth was performed in the existing CNT furnace. Growth conditions for CNTs and graphene are very similar. Both use the same process gases: argon (Ar), hydrogen (H2), and methane (CH4). The major differences between CNT and graphene growth are the substrate materials and the gas flows. As reported in the literature, CVD growth of single layer and bilayer graphene takes place at low methane flow rates (typically, 3–10 sccm) (21, 22). In order to accommodate the smaller flow rates, a new methane

mass flow controller (MFC) was purchased and installed. The APCVD furnace was primarily used to grow graphene on nickel (Ni) thin films.

A new LPCVD furnace system was constructed at the Adelphi Laboratory Center (ALC), MD, this year. In hindsight, the purchase of a commercially established growth system may have been a prudent, albeit more costly, approach. It has been shown that single layer graphene, while difficult to produce using APCVD, can be produced under low pressure on copper (Cu) foils (23, 24). The key components to the system are the (1) gas delivery/handling system, (2) furnace, and (3) exhaust system. Located adjacent to the APCVD system, the LPCVD system is plumbed with the same gases as the APCVD system: hydrogen, nitrogen, argon, methane, ethylene, and compressed air. The flammable gas flows are regulated using MFCs, while rotameters are used for the inert gases. The flammable and inert gases are kept in separate manifolds until they are mixed right before entering the furnace. All valves on the system are pneumatically controlled and switched manually by an electronics panel. Once the gases reach the furnace, the gases enter a 2-in quartz tube heated by the furnace. The furnace can reach a maximum temperature of 1200 °C; however, it is typically operated at lower temperatures. The quartz tube and piping are evacuated by a mechanical roughing pump. A baratron gauge downstream of the furnace measures the system pressure, and a butterfly throttle valve can be operated to set and control the pressure. The system can reach pressures as low as 250 mTorr. The LPCVD furnace has primarily been used for graphene growth on Cu foils.

2.2 Growth on Copper

The growth of graphene on Cu foils was demonstrated in the new LPCVD system. Cu foils (Alfa Aesar #13382, 99.8% Cu, 0.025 mm thick) were cut to approximately 1- x 1.5-in strips and cleaned using the following procedure: acetone rinse, water (H2O) rinse, soak in glacial acetic acid for 10 min, followed by a quick rinse in acetone, isopropanol (IPA), and then blow-dried with nitrogen.

Once the foils are loaded onto a boat and inserted in the furnace, a four-step growth process is initiated. There are four distinct steps for the growth process: a ramp-up stage, a 30-min annealing stage, a 40-min growth stage, and a cool down period (figure 2). During the ramp-up stage, the first 25 min of the anneal stage, and the cool down period, the pressure remains at

0.5–0.7 Torr; however, the growth stage pressure was held constant at 1.5 Torr. Hydrogen was flowed at a steady rate throughout the process; methane was only added during the “growth” stage. The gas flow rates for the hydrogen and methane were varied to determine the optimized growth conditions for producing single layer graphene.

Figure 2. Four-step process for graphene growth on Cu foils.

Once deposited, a graphene transfer process was employed to separate the graphene layer from the Cu foil and to place the graphene onto an oxidized silicon (Si) substrate (see figure 3). To begin this process, a protective bilayer of poly(methyl methacrylate) (PMMA) was spun onto one side of the Cu foil and baked on a hot plate. Next, the unprotected backside graphene layer was removed using an oxygen plasma etch. The Cu foil was then etched away by floating the sample with the PMMA-coated side up in Cu etchant for approximately 1 h. Following this, the PMMA/graphene were rinsed with water and placed in a 10% hydrochloric acid/water solution for 1 hr. The samples were then rinsed in water, transferred onto the silicon dioxide (SiO2) substrate, and nitrogen blow-dried. The PMMA bilayer is either removed in an acetone vaporization process or annealed in an atmospheric pressure furnace. It was later found that removal of the PMMA layers could be very challenging. The acetone vaporization procedure can mechanically damage the graphene material, causing it to split. The preferred removal method is thermal annealing; however, there exists a potential to graphitize the PMMA layers

and leave a carbonaceous residue on the surface.

Figure 3. Transfer process of graphene grown on Cu foils to desired substrate.

2.3 Growth on Nickel

More than 100 graphene samples have been grown on Ni thin films using the APCVD furnace described previously. Ni catalyst layers were first created on 4-in thermally oxidized Si wafers (usually 300 nm of SiO2) using electron beam deposition. Generally, these were 300-nm Ni thin films with an underlying 30-nm adhesion layer of chromium (Cr). For a graphene synthesis run, samples approximately 13 mm2 were cleaved from the Ni-coated wafers and soaked in acetone for 10 min, followed by 10 min in IPA and blown dry in N2.

Once samples were arranged on a quartz boat and loaded into the CVD furnace, a four-step procedure was carried out to produce layers of graphene, similar to the process described previously for growing on Cu. In the ramp-up and Ni-anneal stages, a mixture of H2 and Ar was passed through the furnace. The 20-min annealing to remove any Ni oxides and improve the Ni microstructure by enlarging the crystalline grains was generally conducted at 1000 °C. In the third stage, a small amount of CH4 was added to the gas stream, which dissociated in contact with the Ni catalyst. The resulting carbon atoms promptly diffused into the Ni layer, while the H2 returned to the gas phase. Once enough carbon had entered the Ni lattice (generally 10 min), the furnace temperature was slowly decreased in the ramp-down stage, while still maintaining the CH4 flow. As the sample temperature decreased, the solid solubility limit (the maximum atomic fraction allowed by thermodynamics) for carbon in the polycrystalline Ni decreased substantially, and the excess carbon which was no longer allowed in the Ni was expelled to the surface, and self-assembled to form graphene. Multiple layers of graphene are possible by this approach, so the amount of carbon first placed in the Ni thin film must be tightly controlled. Carbon precipitates more readily at the Ni grain boundaries, leading to excess layers of graphene at those locations. The graphene film can be removed from the Ni and transferred to an arbitrary substrate using a process similar to that shown in figure 3.

Figure 4 shows a typical optical microscopy image of graphene on Ni after growth. The puckered surface topology of the Ni grains is quite evident. The dark irregular patches are regions of multilayer graphene (MLG), with the level of darkness corresponding closely to the

number of layers. The remainder of the sample, which has the lightest shading, is largely covered by 1–2 monolayers of graphene as determined by Raman spectroscopy (see figure 4), which is considered best suited for electronic device fabrication. Since one approach to creating an electronic bandgap in graphene is by applying a transverse electric field to a graphene bilayer, and growth of graphene on Ni lends itself to the growth of more than one layer, this synthesis route may be a valuable one for our future research.

Figure 4. Optical microscopy image of graphene on Ni. The dark irregular

patches are extra layers of graphene typically located at Ni grain

boundaries (not visible).

2.4 Characterization by Raman Spectroscopy

Raman spectroscopy has proven to be a powerful yet relatively simple and nondestructive characterization tool for graphene. Raman measurements were performed on a Renishaw inVia microscope system at 514 nm (spot size ~ \1 μm, 1800 lines/mm grating). The characteristic peaks for graphene are the D, G, and 2D, located at ~1350 cm–1, ~1580 cm–1, and ~2700 cm–1, respectively. The G band arises due to the C–C bond in graphitic materials and can be found in all sp2 bonded carbon materials. The 2D band, also known as the G’ band, results from a double resonance or second-order scattering process and is sensitive to the number of graphene layers present. The presence of disorder in the sp2 carbon materials is detected by the D band. The peak position, shape, full-width-at-half-maximum (FWHM), and intensity ratios of the different bands indicate the film quality level as well as the number of graphene layers.

An optical image of a transferred graphene film grown on Cu and the Raman spectra from various points in the image are shown in figure 5. There are several significant features from Raman data that can be discussed. First, the 2D band intensity is much greater than the G band peak for all five points shown. The I2D/I G ratio for the five points averages 2.33. Secondly, the

FWHM values for the 2D band vary between 35 and 38 cm–1. It is typically known that I2D/I G values >2 are indicative of monolayer graphene, and the 2D FWHM of single layer graphene (SLG) has been reported to range between 30 and 35 cm–1. The I D/I G ratio for the points shown ranged between 0.13 and 0.22, considered to indicate a relatively low defect density in the material. These results are in good agreement with previous studies of CVD graphene on Cu (23–25). Additionally, the Raman data shows that there is good uniformity of monolayer graphene across the sample.

crosses on the optical image correspond to the colored Raman spectra taken at the respective points.

2.5 Graphene Exfoliation

2.5.1 Overview and Purpose

Methods for synthesizing graphene are necessary to keep an in-house supply available for device fabrication and material characterization. Based on the technique first developed by Geim and Novoselov (26)in 2004, the process of mechanical exfoliation (also referred to as the “Scotch tape method”) involves the use of an adhesive tape to strip single- and few-layer sheets of graphene from a highly ordered pyrolytic graphite (HOPG) source. The resulting graphene extracted via this method tends to produce, high quality, well-ordered, uniform graphene areas on arbitrary substrates. In the case of bilayer or few-layer graphene, A-B stacking tends to be the typical layer-to-layer alignment.

While ARL has the infrastructure and capability to grow graphene on metal catalysts using APCVD and LPCVD, exfoliated graphene provides a reference material due to the fact that it is the most common method for acquiring graphene and is commonly used in university laboratories. As such, most research groups using graphene provide results based on exfoliated graphene. It also provides a high quality reference material with few defects to compare with the graphene grown using CVD-based processing. If necessary, this material can be used for graphene device fabrication.

2.5.2 Process Description

The process used for mechanical exfoliation at ARL is based on the process developed at MIT by

Prof. Pablo Jarillo-Herrero’s group. Si wafers with 300 nm of thermally grown SiO 2 are cleaned

and prepared as the final substrate for the exfoliated graphene. Specialized graphite flakes

purchased from NGS Naturgraphit GmbH were exfoliated using the 1007R6 adhesive film from

Ultron Systems. A graphite flake was placed on the adhesive film, which was then folded and

pulled apart repeatedly until the graphite flake was thinned down to roughly a few graphene

layers thick. The thin sheets of graphite covering the adhesive film were then gently pressed

against a SiO 2/Si wafer using fluorinated plastic tweezers. Figure 6 provides images of the

process step-by-step while figure 7 depicts optical micrographs of exfoliated graphene. After the

removal of the adhesive film, an optical microscope was used to locate graphene areas on the

sample. Once the graphene areas were located, the quality of the material and the number of

layers were determined using atomic force microscopy (AFM) and Raman spectroscopy.

Figure 8 presents an example of an AFM image of an area of graphene with differing numbers of

layers.

Figure 6. A pictorial of the mechanical exfoliation process. (a) Highly-oriented pyrolytic graphite flakes

(“graphenium”) are used as the source material. (b) A special adhesive film in the form of tape with

extremely low residue is used to split the graphite flakes along their crystal planes. This process is

repeated several times until single- or few-layer graphene flakes are produced. (c) The graphene

flakes are then transferred to a Si substrate with a 300-nm layer of thermally grown SiO 2. (d) Optical

microscopy is used to locate graphene areas on the substrate, and then Raman spectroscopy and AFM

are used to determine the number of graphene layers and their quality.

(b) (d) (c)

Graphene-based nanoelectronics

相关文档

最新文档