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DAC1054CIWM中文资料

TL H 11437DAC1054 Quad 10-Bit Voltage-Output Serial D A Converter with Readback

January1995 DAC1054Quad10-Bit Voltage-Output

Serial D A Converter with Readback

General Description

The DAC1054is a complete quad10-bit voltage-output digi-

tal-to-analog converter that can operate on a single5V sup-

ply It includes on-chip output amplifiers internal voltage ref-

erence and serial microprocessor interface By combining

in one package the reference amplifiers and conversion

circuitry for four D A converters the DAC1054minimizes

wiring and parts count and is hence ideally suited for appli-

cations where cost and board space are of prime concern

The DAC1054also has a data readback function which can

be used by the microprocessor to verify that the desired

input word has been properly latched into the DAC1054’s

data registers The data readback function simplifies the de-

sign and reduces the cost of systems which need to verify

data integrity

The logic comprises a MICROWIRE TM-compatible serial in-

terface and control circuitry The interface allows the user to

write to any one of the input registers or to all four at once

The latching registers are double-buffered consisting of4

separate input registers and4DAC registers Each DAC

lows all4DAC outputs to be updated simultaneously or

individually

The four reference inputs allow the user to configure the

system to have a separate output voltage range for each

DAC The output voltage of each DAC can range between

0 3V and2 8V and is a function of V BIAS V REF and the

input word

Features

Y Single a5V supply operation

Y MICROWIRE serial interface allows easy interface to

many popular microcontrollers including the COPS TM

and HPC TM families of microcontrollers

Y Data readback capability

Y Output data can be formatted to read back MSB or

LSB first

Y Versatile logic allows selective or global update of the

DACs

Y Power fail flag

Y Output amplifiers can drive2k X load

Y Synchronous asynchronous update of the DAC outputs

Key Specifications

Y Guaranteed monotonic over temperature

Y Integral linearity error g LSB max

Y Output settling time3 7m s max

Y Analog output voltage range0 3V to2 8V

Y Supply voltage range4 5V to5 5V

Y Clock frequency for write10MHz max

Y Clock frequency for read back5MHz max

Y Power dissipation(f CLK e10MHz)100mW max

Y On-board reference2 65V g2%max

Applications

Y Automatic test equipment

Y Industrial process controls

Y Automotive controls and diagnostics

Y Instrumentation

Connection Diagram

TL H 11437–1

Top View

Ordering Information

Industrial(b40 C k T A k a85 C)Package

DAC1054CIN N24A Molded DIP

DAC1054CIWM M24B Small Outline

Military(b55 C k T A k a125 C)

DAC1054CMJ 883or

J24A Ceramic DIP

5962-9466201MJA

COPS TM HPC TM and MICROWIRE TM are trademarks of National Semiconductor Corporation

C1995National Semiconductor Corporation RRD-B30M75 Printed in U S A

Absolute Maximum Ratings(Notes1 2)

If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage(AV CC DV CC)7V Supply Voltage Difference(AV CC–DV CC)g5 5V Voltage at Any Pin(Note3)GND b0 3V to

AV CC DV CC a0 3V Input Current at Any Pin(Note3)5mA Package Input Current(Note4)30mA Power Dissipation(Note5)950mW ESD Susceptibility(Note6)

Human Body Model2000V Machine Model200V Soldering Information

N Package(10sec )260 C SO Package

Vapor Phase(60sec )215 C Infrared(15sec )(Note7)220 C Storage Temperature b65 C to a150 C Operating Ratings(Notes1 2)

Supply Voltage4 5V to5 5V Supply Voltage Difference(AV CC b DV CC)g1V Temperature Range T MIN k T A k T MAX DAC1054CIN DAC1054CIWM b40 C k T A k85 C DAC1054CMJ 883b55 C k T A k125 C

Converter Electrical Characteristics

The following specifications apply for AV CC e DV CC e5V V REF e2 65V V BIAS e1 4V R L e2k X(R L is the load resistor on the analog outputs–pins2 13 17 and23)and f CLK e10MHz unless otherwise specified Boldface limits apply for T A e T J from T MIN to T MAX All other limits apply for T A e25 C

Symbol Parameter Conditions Typical Limit Units (Note8)(Note9)(Limits)

STATIC CHARACTERISTICS

n Resolution1010bits Monotonicity(Note10)1010bits

Integral Linearity Error(Note11)

DAC1054CIN DAC1054CIWM g0 75LSB(max)

Differential Linearity Error g1 0LSB(max)

Fullscale Error(Note12)g30mV

Fullscale Error Tempco(Note13)b38ppm C

Zero Error(Note14)g25mV

Zero Error Tempco(Note13)b38ppm C

Power Supply Sensitivity(Note15)b34dB(max) DYNAMIC CHARACTERISTICS

t s a Positive Voltage Output(Note16)

1 83 2m s

Settling Time C L e200pF

t s b Negative Voltage Output(Note16)

2 3

3 7m s

Settling Time C L e200pF

Digital Crosstalk(Note17)15mV p-p

Digital Feedthrough(Note18)15mV p-p

Clock Feedthrough(Note19)20mV p-p

Channel-to-Channel Isolation(Note20)b71dB

Glitch Energy(Note21)7nV b s

Peak Value of Largest Glitch38mV PSRR Power Supply Rejection Ratio(Note22)b49dB

Converter Electrical Characteristics(Continued)

Symbol Parameter Conditions Typical Limit Units (Note3)(Note4)(Limits)

DIGITAL AND DC ELECTRICAL CHARACTERISTICS

V IN(1)Logical‘‘1’’Input Voltage AV CC e DV CC e5 5V2 0V(min) V IN(0)Logical‘‘0’’Input Voltage AV CC e DV CC e4 5V0 8V(max) I IL Digital Input Leakage Current1m A(max) C IN Input Capacitance4pF

C OUT Output Capacitance5pF

V OUT(1)Logical‘‘1’’Output Voltage I SOURCE e0 8mA2 4V(min) V OUT(0)Logical‘‘0’’Output Voltage I SINK e3 2mA0 4V(max) V INT Interrupt Pin Output Voltage10k X Pullup0 4V(max) I S Supply Current Outputs Unloaded1420mA REFERENCE INPUT CHARACTERISTICS

V REF Input Voltage Range0–2 75V

R REF Input Resistance74k X(min)

9k X(max) C REF Input Capacitance Full-Scale Data Input25pF

V BIAS INPUT CHARACTERISTICS

V BIAS V BIAS Input Voltage Range0 3–1 4V Input Leakage1m A

C BIAS Input Capacitance9pF BANDGAP REFERENCE CHARACTERISTICS(C L e220m F)

V REF OUT Output Voltage2 65g2%V

D V REF D T Tempco(Note23)29ppm C

Line Regulation4 5V k V CC k5 5V I L e4mA5mV

D V REF D I L Load Regulation0k I L k4mA10mV

b1k I L k0mA2 5mV

I SC Short Circuit Current V REF OUT e0V12mA AC ELECTRICAL CHARACTERISTICS

t DS Data Setup Time15ns(min) t DH Data Hold Time0ns(min) t CS Control Setup Time15ns(min) t CH Control Hold Time0ns(min) f WMAX Clock Frequency Write10MHz(max) f RMAX Clock Frequency Readback5MHz(max) t H Minimum Clock High Time20ns(min) t L Minimum Clock Low Time20ns(min)

Converter Electrical Characteristics(Continued)

Symbol Parameter Conditions Typical Limit Units (Note3)(Note4)(Limits)

AC ELECTRICAL CHARACTERISTICS(Continued)

t CZ1Output Hi-Z to Valid1f CLK e5MHz70ns(max) t CZ0Output Hi-Z to Valid0f CLK e5MHz70ns(max) t1H CS to Output Hi-Z10k X with60pF f CLK e5MHz150ns(max) t0H CS to Output Hi-Z10k X with60pF f CLK e5MHz130ns(max) Note1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur Operating Ratings indicate conditions for which the device is functional These ratings do not guarantee specific performance limits however For guaranteed specifications and test conditions see the Converter Electrical Characteristics The guaranteed specifications apply only for the test conditions listed Some performance characteristics may degrade when the device is not operated under the listed test conditions

Note2 All voltages are measured with respect to ground unless otherwise specified

Note3 When the input voltage(V IN)at any pin exceeds the power supply rails(V IN k GND or V IN l V a)the absolute value of current at that pin should be limited to5mA or less

Note4 The sum of the currents at all pins that are driven beyond the power supply voltages should not exceed30mA

Note5 The maximum power dissipation must be derated at elevated temperatures and is dictated by T Jmax(maximum junction temperature) H JA (package junction to ambient thermal resistance) and T A(ambient temperature) The maximum allowable power dissipation at any temperature is P Dmax e(T Jmax b T A) H JA or the number given in the Absolute Maximum Ratings whichever is lower The table below details T Jmax and H JA for the various packages and versions of the DAC1054

Part Number T Jmax( C)H JA( C W)

DAC1054CIN12542

DAC1054CIWM12557

Note6 Human body model 100pF discharged through a1 5k X resistor

Note7 See AN450‘‘Surface Mounting Methods and Their Effect on Production Reliability’’of the section titled‘‘Surface Mount’’found in any current Linear Databook for other methods of soldering surface mount devices

Note8 Typicals are at T J e25 C and represent most likely parametric norm

Note9 Limits are guaranteed to National’s AOQL(Average Outgoing Quality Level)

Note10 A monotonicity of10bits for the DAC1054means that the output voltage changes in the same direction(or remains constant)for each increase in the input code

Note11 Integral linearity error is the maximum deviation of the output from the line drawn between zero and full-scale(excluding the effects of zero error and full-scale error)

Note12 Full-scale error is measured as the deviation from the ideal2 800V full-scale output when V REF e2 650V and V BIAS e1 400V

Note13 Full-scale error tempco and zero error tempco are defined by the following equation

Error tempco e Error(T MAX)b Error(T MIN)

V SPAN(

106

T MAX b T MIN(

where Error(T MAX)is the zero error or full-scale error at T MAX(in volts) and Error(T MIN)is the zero error or full-scale error at T MIN(in volts) V SPAN is the output voltage span of the DAC1054 which depends on V BIAS and V REF

Note14 Zero error is measured as the deviation from the ideal0 302V output when V REF e2 650V V BIAS e1 400V and the digital input word is all zeros Note15 Power Supply Sensitivity is the maximum change in the offset error or the full-scale error when the power supply differs from its optimum5V by up to 0 50V(10%) The load resistor R L e2k X

Note16 Positive or negative settling time is defined as the time taken for the output of the DAC to settle to its final full-scale or zero output to within g0 5LSB This time shall be referenced to the50%point of the positive edge of CS which initiates the update of the analog outputs

Note17 Digital crosstalk is the glitch measured on the output of one DAC while applying an all0s to all1s transition at the input of the other DACs

Note18 All DACs have full-scale outputs latched and DI is clocked with no update of the DAC outputs The glitch is then measured on the DAC outputs

Note19 Clock feedthrough is measured for each DAC with its output at full-scale The serial clock is then applied to the DAC at a frequency of10MHz and the glitch on each DAC full-scale output is measured

Note20 Channel-to-channel isolation is a measure of the effect of a change in one DAC’s output on the output of another DAC The V REF of the first DAC is varied between1 4V and2 65V at a frequency of15kHz while the change in full-scale output of the second DAC is measured The first DAC is loaded with all0s Note21 Glitch energy is the difference between the positive and negative glitch areas at the output of the DAC when a1LSB digital input code change is applied to the input The glitch energy will have its largest value at one of the three major transitions The peak value of the maximum glitch is separately specified Note22 Power Supply Rejection Ratio is measured by varying AV CC e DV CC between4 50V and5 50V with a frequency of10kHz and measuring the proportion of this signal imposed on a full-scale output of the DAC under consideration

Note23 The bandgap reference tempco is defined by the largest value from the following equations

Tempco(T MAX)e V REF(T MAX)b V REF(T ROOM)

V REF(T ROOM)(

106

T MAX b T ROOM(or Tempco(T MIN)e

V REF(T MIN)b V REF(T ROOM)

V REF(T ROOM)(

106

T ROOM b T MIN(

where T ROOM e25 C V REF(T MAX)is the reference output at T MAX and similarly for V REF(T MIN)and V REF(T ROOM) Note24 A Military RETS specification is available upon request

Typical Converter Performance Characteristics

Temperature

Zero Error vs vs Temperature

Full-Scale Error vs Temperature

Supply Current vs Temperature Zero Error PSRR vs Temperature Full-Scale Error PSRR Clock Frequency

Supply Current vs Error vs Temperature

Integral Non-Linearity TL H 11437–2

Typical Reference Performance Characteristics

Bandgap Voltage vs Temperature

TL H 11437–3Line Regulation vs Temperature

TL H 11437–4

TRI-STATE Test Circuits and Waveforms

TL H 11437–5

TL H 11437–6

TL H 11437–7

TL H 11437–8

Timing Waveforms

Data Input Timing

TL H 11437–9

Data Output Timing

TL H 11437–10

Timing Diagrams

TL H 11437–11

FIGURE 1 Write to One DAC with Update of Output (AU e 1) 10MHz Maximum CLK Rate

Timing Diagrams(Continued)

TL H 11437–12

DACs are written to MSB first

DAC1is written to first then DACs2 3 and4

FIGURE2 Write to All DACs with Update of Outputs(AU e1) 10MHz Maximum CLK Rate

TL H 11437–13 FIGURE3 Read One DAC DO LSB First DO Changes on Falling Edge of CLK(AU e1) 5MHz Maximum CLK Rate

TL H 11437–14

DAC1is read first then DACs2 3 and4

FIGURE4 Read All DACs DO LSB First DO Changes on Falling Edge of CLK(AU e1) 5MHz Maximum CLK Rate

Block Diagram

TL H 11437–15 Pin Description

V OUT1(2) The voltage output connections of the V OUT2(23) four DACS These provide output

V OUT3(17) voltages in the range0 3V–2 8V

V OUT4(13)

V REF OUT(21)The internal voltage reference output

The output of the reference is2 65V

g2%

V BIAS1(3) The non-inverting inputs of the4output V BIAS2(24) amplifiers These pins set the virtual

V BIAS3(16) ground voltage for the respective DACs V BIAS4(15)The allowed range is0 3V–1 4V AGND(20) The analog and digital ground pins DGND(5)

DV CC(4 6) The digital and analog power supply

AV CC(19)pins The power supply range of the

DAC1054is4 5V–5 5V To guarantee

accuracy it is required that the AV CC

and DV CC pins be bypassed separately

with bypass capacitors of10m F

tantalum in parallel with0 1m F ceramic

AU(11)When this pin is taken low all DAC outputs

will be asynchronously updated CS must

be held high during the update AU must be

held high during Read back

V REF1(1) The voltage reference inputs for the four

V REF2(22) DACs The allowed range is0V–2 75V

V REF3(18)

V REF4(14)

CS(9)The Chip Select control input This input is

active low

CLK(8)The external clock input pin

DI(10)The serial data input The data is clocked in

MSB first Preceding the data byte are4or

6bits of instructions The read back

command requires7bits of instructions

DO(7)The serial data output The data can be

clocked out either MSB or LSB first and on

either the positive or negative edge of the

clock

INT(12)The power interrupt output On an

interruption of the digital power supply this

pin goes low Since this pin has an open

drain output a10k X pull-up resistor must

be connected to the supply

Applications Information

FUNCTIONAL DESCRIPTION

The DAC1054is a monolithic quad 10-bit digital-to-analog converter that is designed to operate on a single 5V supply Each of the four units is comprised of an input register a DAC register a shift register a current output DAC and an output amplifier In addition the DAC1054has an onboard bandgap reference and a logic unit which controls the inter-nal operation of the DAC1054and interfaces it to micro-processors

Each of the four internal 10-bit DACs uses a modified R-2R ladder to effect the digital-to-analog conversion (Figure 5) The resistances corresponding to the 2most significant bits are segmented to reduce glitch energy and to improve matching The bottom of the ladder has been modified so that the voltage across the LSB resistor is much larger than the input offset voltage of the buffer amplifier The input digital code determines the state of the switches in the lad-der network An internal EEPROM which is programmed at the factory is used to correct for linearity errors in the resis-tor ladder of each of the four internal DACs The codes stored in the EEPROM’s memory locations are converted to a current I EEPROM with a small trim DAC The sum of cur-rents I OUT1and I OUT2is fixed and is given by

I OUT1a I OUT2e

V REF b V BIAS

10231024

The current output I OUT2 summed with the correction cur-rent I EEPROM is applied to the internal output amplifier and converted to a voltage The output voltage of each DAC is a function of V BIAS V REF and the digital input word and is given by

V OUT e 2(V REF b V BIAS )

DATA 1024a 2047512V BIAS b 1023

512

V REF The output voltage range for each DAC is 0 3V–2 8V This

range can be achieved by using the internal 2 65V reference and a voltage divider network which provides a V BIAS of 1 40V (Figure 6) In this case the DAC transfer function is

V OUT e 2 5

(DATA)

1024

a 0 30244

The output impedance of any external reference that is used will affect the accuracy of the conversion In order that this error be less than LSB the output impedance of the external reference must be less than 2X

TL H 11437–16

FIGURE 5 Equivalent Circuit of R-2R Ladder and Output Amplifier

TL H 11437–17

FIGURE 6 Generating a V BIAS e 1 40V from the Internal Reference Typical Application

Digital Interface

The DAC1054has two interface modes a WRITE mode and a READ mode The WRITE mode is used to convert a 10-bit digital input word into a voltage The READ mode is used to read back the digital data that was sent to one or all of the DACs The WRITE mode maximum clock rate is 10MHz READ mode is limited to a5MHz maximum clock rate These modes are selected by the appropriate setting of the RD WR bit which is part of the instruction byte The instruction byte precedes the data byte at the DI pin In both modes a high level on the Start Bit(SB)alerts the DAC to respond to the remainder of the input stream

Table I lists the instruction set for the WRITE mode when writing to only a single DAC and Table II lists the instruction set for a global write Bits A0and A1select the DAC to be written to The DACs are always written to MSB first All DACs will be written to sequentially if the global bit(G)is high DAC1is written to first then DACs2 3and4(in that order) For a global write bits A0and A1of the instruction byte are not required(see Figure2timing diagram) If the update bit(U)is high then the DAC output(s)will be updat-ed on the rising edge of CS otherwise the new data byte will be placed only in the input register Chip Select(CS) must remain low for at least one clock cycle after the last data bit has been entered (See Figures1and2)

When the U bit is set low an asynchronous update of all the DAC outputs can be achieved by taking AU low The con-tents of the input registers are loaded into the DAC regis-ters with the update occurring on the falling edge of AU CS must be held high during an asynchronous update

All DAC registers will have their contents reset to all zeros on power up

TABLE I WRITE Mode Instruction Set(Writing to a Single DAC)

SB RD WR G U A1A0

Description

Bit 1Bit 2Bit 3Bit 4Bit 5Bit 6

100000Write DAC1 no update of DAC outputs 100001Write DAC2 no update of DAC outputs 100010Write DAC3 no update of DAC outputs 100011Write DAC4 no update of DAC outputs 100100Write DAC1 update DAC1on CS rising edge 100101Write DAC2 update DAC2on CS rising edge 100110Write DAC3 update DAC3on CS rising edge 100111Write DAC4 update DAC4on CS rising edge

TABLE II WRITE Mode Instruction Set(Writing to all DACs)

SB RD WR G U

Description

Bit 1Bit 2Bit 3Bit 4

1010Write all DACs no update of outputs

1011Write all DACs update all outputs on CS rising edge

Digital Interface(Continued)

Table III lists the instruction set for the READ mode By the appropriate setting of the global(G)and address(A1and A0)bits one can select a specific DAC to be read or one can read all the DACs in succession starting with DAC1 The R F bit determines whether the data changes on the rising or the falling edge of the system clock With the R F bit high DO goes out of TRI-STATE on the rising edge that occurs1 clock cycles after the end of the instruction byte the data will continue to be sequentially clocked out by the following rising clock edges With the R F bit low DO goes out of TRI-STATE on the falling edge that occurs1clock cycle after the end of the instruction byte the data will con-tinue to be sequentially clocked by the next falling clock edges The rising edge of CS returns DO to TRI-STATE Read back with the R F bit set high is not MICROWIRE compatible One can choose to read the data back MSB first or LSB first by setting the M L bit (See Figures3and 4)

TABLE III READ MODE Instruction Set

SB RD WR G R F M L A1A0

Description

Bit 1Bit 2Bit 3Bit 4Bit 5Bit 6Bit 7

1100000Read DAC1 LSB first data changes on the falling edge 1100001Read DAC2 LSB first data changes on the falling edge 1100010Read DAC3 LSB first data changes on the falling edge 1100011Read DAC4 LSB first data changes on the falling edge 1100100Read DAC1 MSB first data changes on the falling edge 1100101Read DAC2 MSB first data changes on the falling edge 1100110Read DAC3 MSB first data changes on the falling edge 1100111Read DAC4 MSB first data changes on the falling edge 1101000Read DAC1 LSB first data changes on the rising edge 1101001Read DAC2 LSB first data changes on the rising edge 1101010Read DAC3 LSB first data changes on the rising edge 1101011Read DAC4 LSB first data changes on the rising edge 1101100Read DAC1 MSB first data changes on the rising edge 1101101Read DAC2 MSB first data changes on the rising edge 1101110Read DAC3 MSB first data changes on the rising edge 1101111Read DAC4 MSB first data changes on the rising edge 1110010Read all DACs LSB first data changes on the falling edge 1110110Read all DACs MSB first data changes on the falling edge 1111010Read all DACs LSB first data changes on the rising edge 1111110Read all DACs MSB first data changes on the rising edge

Power Fail Function

The DAC1054powers up with the INT pin in a Low state To force this output high and reset this flag the CS pin will have to be brought low When this is done the INT output will be pulled high again via an external10k X pull-up resistor Any-time a power failure occurs on the DV CC line the INT will be set low when power is reapplied This feature may be used by the microprocessor to discard data whose integrity is in question

Power Supplies

The DAC1054is designed to operate from a a5V(nominal) supply There are two supply lines AV CC and DV CC These pins allow separate external bypass capacitors for the ana-log and digital portions of the circuit To guarantee accurate conversions the two supply lines should each be bypassed with a0 1m F ceramic capacitor in parallel with a10m F tantalum capacitor

Typical Applications

TL H 11437–18 FIGURE7 Trimming the Offset of a5V Op Amp Whose Output is Biased at2 5V

TL H 11437–19 FIGURE8 Trimming the Offset of a Dual Supply Op Amp(V IN is Ground Referenced)

TL H 11437–20

FIGURE9 Bringing the Output Range Down to Ground

Physical Dimensions inches(millimeters)

Order Number DAC1054CMJ 883or5962-9466201MJA

NS Package Number J24A

Order Number DAC1054CIWM

NS Package Number M24B

D A C 1054Q u a d 10-B i t V o l t a g e -O u t p u t S e r i a l D A C o n v e r t e r w i t h R e a d b a c k

Physical Dimensions inches (millimeters)(Continued)

Lit 02236

Order Number DAC1054CIN NS Package Number N24A

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which (a)are intended for surgical implant support device or system whose failure to perform can into the body or (b)support or sustain life and whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system or to affect its safety or with instructions for use provided in the labeling can effectiveness

be reasonably expected to result in a significant injury to the user

National Semiconductor National Semiconductor National Semiconductor National Semiconductor National Semiconductores National Semiconductor Corporation

GmbH

Japan Ltd

Hong Kong Ltd

Do Brazil Ltda

(Australia)Pty Ltd 2900Semiconductor Drive

Livry-Gargan-Str 10

Sumitomo Chemical

13th Floor Straight Block Rue Deputado Lacorda Franco Building 16

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