stm32f2-usb-storge
UM1653
User manual STM32 Advanced NAND Flash Driver for SLC NAND
Introduction
The NAND driver library for STM32 is a generic library from which STM32 can access
NAND with advanced features like garbage collection, wear leveling, bad block
management, ECC checking etc.
The NAND Flash driver supports dynamic NAND Flash detection based on the Device ID.
The driver automatically detects the mounted SLC NAND Flash and works accordingly
(described in more detail in Section 2.8). This solution runs on the STM32F1, STM32F2 &
STM32F4 series of microcontrollers using the FSMC interface.
The board can run in two modes: USB Mass Storage mode and Standalone mode.
?In USB Mass Storage mode, the NAND Flash works as USB mass storage media.
?In Standalone mode, the .bmp images stored in the ‘pics’ folder of the root directory are read using FatFS file system, and displayed on the onboard TFT LCD.
Six evaluation boards are available for this SLC NAND FLASH Driver:
?STEVAL_CCM006V1: USB mass storage mode demo using STM32F103ZET6
?STEVAL_CCM006V2: Standalone mode demo using STM32F103ZET6
?STEVAL_CCM007V1: USB Mass Storage mode Demo using STM32F205ZET6
?STEVAL_CCM007V2: Standalone mode Demo using STM32F205ZET6
?STEVAL_CCM008V1: USB Mass Storage mode Demo using STM32F405ZGT6
?STEVAL_CCM008V2: Standalone mode Demo using STM32F405ZGT6
NAND is a non-volatile Flash memory device where address lines are multiplexed with data
input/output and commands input. The NAND driver library has the following features:
1.Supports both FAT file system and USB MSC device.
2. Supports SLC NAND with page size of 512 Bytes & 2KBytes.
3. Garbage collection.
4. Wear leveling.
5. Bad block management.
6. ECC check.
This document applies to the following microcontrollers:
?STM32L151xD, STM32L152xD, STM32L1562xD.
?STM32F405/415, STM32F407/417, STM32F427/437, STM32F429/439 lines.
?STM32F2 Series.
?STM32F103xC, STM32F103xD and STM32F103xE, STM32F103xF, STM32F103xG, STM32F101xC, STM32F101xD and STM32F101xE, STM32F101xF, STM32F101xG,
STM32F100xC, STM32F100xD, STM32F100xE.
November 2013DocID025024 Rev 11/45
https://www.sodocs.net/doc/331226266.html,
Contents UM1653
Contents
1STM32 NAND driver blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1STM32 USB peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2USB mass storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3FSMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4NAND architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.5NAND pin mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2NAND driver firmware modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.2Wear leveling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.3ECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.1Hamming code for NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.2Error detection and correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4Bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.5Look up table (LUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.6File system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.7NAND driver files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.7.1nand_drv.c, nand_drv.h functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.7.2fsmc_nand_if.c, fsmc_nand_if.h functions . . . . . . . . . . . . . . . . . . . . . . . 28
2.8Supported NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3NAND evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.1Working with evaluation boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.1.1Running in USB Mass Storage mode (STEVAL-CCM006/7/8V1) . . . . . 36
3.1.2Running in Standalone mode (STEVAL-CCM006/7/8V2) . . . . . . . . . . . 37
3.2Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.3NAND evaluation board images . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2/45DocID025024 Rev 1
UM1653List of tables List of tables
Table 1.Spare area format for small NAND Flash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 2.Spare area format for large NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 3.File system interface functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 4.NAND_Init. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 5.NAND_Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 6.NAND_Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 7.NAND_WriteECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 8.NAND_PostWriteECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 9.NAND_CleanLUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 10.NAND_WearLeveling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 11.SBLK_NAND_WearLeveling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 12.LBLK_NAND_WearLeveling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 13.NAND_GetFreeBlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 14.SBLK_NAND_ReadSpareArea. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 15.LBLK_NAND_ReadSpareArea. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 16.WriteSpareArea . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 17.NAND_Copy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 18.NAND_CopyBack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 19.NAND_Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 20.NAND_PostWrite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 21.SBLK_NAND_PostWrite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 22.LBLK_NAND_PostWrite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 23.NAND_GarbageCollection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 24.NAND_UpdateWearLevelCounter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 25.NAND_ConvertPhyAddress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 26.NAND_BuildLUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 27.SBLK_NAND_BuildLUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 28.LBLK_NAND_BuildLUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 29.GetParity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 30.Swap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 31.WritePage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 32.SBLK_NAND_WritePage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 33.LBLK_NAND_WritePage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 34.ReadPage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 35.SBLK_NAND_ReadPage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 36.LBLK_NAND_ReadPage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 37.BitCount . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 38.FSMC_SelectNANDType. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 39.FSMC_NAND_NON_ONFI_Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 40.FSMC_NAND_Init. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 41.FSMC_NAND_ReadID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 42.FSMC_NAND_WriteSmallPage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 43.FSMC_NAND_ReadSmallPage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 44.FSMC_NAND_WriteSpareArea . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 45.FSMC_NAND_ReadSpareArea . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 46.FSMC_NAND_EraseBlock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 47.FSMC_NAND_Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 48.FSMC_NAND_GetStatus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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List of tables UM1653 Table 49.FSMC_SBLK_NAND_CopyBack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 50.FSMC_LBLK_NAND_CopyBack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 51.FSMC_NAND_ReadStatus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 52.FSMC_NAND_AddressIncrement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 53.FSMC_NAND_ONFI_Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 54.FSMC_SBLK_NAND_SendAddress. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 55.FSMC_LBLK_NAND_SendAddress. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 56.Supported NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 57.NAND Flash driver file code size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 58.Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
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UM1653List of figures List of figures
Figure 1.Application architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2.BOT protocol architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3.NAND block architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 4.Flow of wear leveling mechanism for STEVAL-CCM006V1. . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5.Flow of wear leveling mechanism for STEVAL-CCM007V1/ 008V1. . . . . . . . . . . . . . . . . . 13 Figure 6.Example of decomposition of a data packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7.Flow chart for error detection and correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 8.Flow chart for bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 9.Flow chart for File System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 10.Evaluation board: top side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 11.Evaluation board: bottom side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 12.Demo running in Standalone mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 13.Microcontroller schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure https://www.sodocs.net/doc/331226266.html,B Full Speed schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure https://www.sodocs.net/doc/331226266.html,B High Speed schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 16.Touch Screen schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 17.TFT Connector schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 18.Power schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 19.NAND Flash schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 20.NAND Flash Signals schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 21.JTAG schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 22.Top side of PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 23.Bottom side of PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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STM32 NAND driver blocks UM1653
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1 STM3
2 NAND driver blocks
This document describes how to connect a NAND Flash device to an STM32 family
microcontroller and communicate using FSMC. NAND driver library for STM32 is a generic library where STM32 can access NAND with some advanced features like garbage
collection, wear leveling, bad block management, ECC checking etc. The library supports both FAT file system and USB MSC device.
1.1 STM32 USB peripheral
The STM32F embeds a USB peripheral that supports USB full-speed and high speed.
The development of Endpoint and support suspend / resume are configured by software. The USB device provides a connection between the host and the function implemented by the microcontroller.
Data transfer between the host and the memory system is through a dedicated packet buffer memory accessed directly from the USB device. The size of buffer memory is dependent on the number of endpoints used and the maximum packet size. This dedicated memory is 512 bytes.
UM1653STM32 NAND driver blocks
1.2 USB mass storage
The USB device is provided to the host as a particular class, which determines how the host
cross reacts with the embedded system.
In our case, the USB device must appear in the driver as a Mass Storage Class USB, which
defines that SCSI commands will be used with the protocol “bulk-only transport” (BOT).
Bulk-only-transport (BOT)
A general BOT transaction is based on a simple basic state machine. It begins with ready
state (idle state) and if a CBW is received from the host three cases can be managed:
?DATA-OUT-STAGE: when direction flag is set to 0, Device shall prepare itself to receive an amount of data indicated in dCBWDataTransferLength in the CBW block. At the end
of data transfer a CSW is returned with the remaining data length and the STATUS
field.
?DATA-IN-STAGE: when direction flag is set to 1, Device shall prepare itself to send an amount of data indicated in dCBWDataTransferLength in the CBW block. At the end of
data transfer a CSW is returned with the remaining data length and the STATUS field.
?ZERO DATA: no data stage is needed so CSW block is sent immediately after CBW.
The BOT transport protocol encapsulates SCSI commands and transfers them in three
steps:
1.Send the command block CBW.
2. Transfer data.
3. Return the status of the block CSW.
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Bulk-Only Transport State machine
#define BOT_IDLE 0 //Idle state
#define BOT_DATA_OUT1 //Data Out state
#define BOT_DATA_IN2 //Data In state
#define BOT_DATA_IN_LAST3 //Last Data In Last
#define BOT_CSW_Send4 //Command Status Wrapper
#define BOT_ERROR5 //error state
#define BOT_CBW_SIGNATURE0x43425355 //1st 4 bytes of CBW pkt
#define BOT_CSW_SIGNATURE0x53425355 //1st 4 bytes of CSW pkt
#define BOT_CBW_PACKET_LENGTH 31
#define CSW_DATA_LENGTH13
CSW Status Definitions
#define CSW_CMD_PASSED0x00
#define CSW_CMD_FAILED0x01
#define CSW_PHASE_ERROR0x02
#define SEND_CSW_DISABLE0
#define SEND_CSW_ENABLE1
#define DIR_IN0
#define DIR_OUT1
#define BOTH_DIR2
1.3 FSMC
The FSMC block is able to communicate with the synchronous and asynchronous memory.
Its main purpose is to:
?Translate the AHB protocol transactions of external devices
?Respect the access time of external devices
The FSMC provides a single access to an external device.
The FSMC has four blocks:
?AHB Interface
?Controller NOR Flash / PSRAM
?Controller NAND Flash / PC Card
?Interface to external device
The FSMC generates the appropriate signals to drive the NAND Flash memory.
The FSMC controller consists of two blocks of code error correction hardware. They reduce
the workload on the host processor when processing code error correction by the system
software. These two blocks are identical and are respectively associated with banks 2 and
3. The ECC algorithm used in the FSMC can perform 1- and 2-bit error detection.
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UM1653STM32 NAND driver blocks
1.4 NAND architecture
NAND is a non-volatile Flash memory device where address lines are multiplexed with data
input/output as well as with commands input. ?NAND Flash consists of a number of blocks. Each block consists of a number of pages, typically 32 or 64.
?Pages can be written individually, one at a time. When writing to a page, bits can only be written from 1 to 0.
?
The erase operation is done by block. Erase operation makes all the memory bits of all the pages in the block to logical 1.
The small NAND Flash contains 528-byte pages (512 data area and 16 byte spare area). The page size for 2K NAND is 2112 (2048 data and 64 spare area). The page size for 4K NAND is 4224 (4096 data and 128 spare area). The page size for 8K NAND is 8448 (8192 data and 256 spare area).
The spare area contains information about the page and the code error correction:For small page (512 + 16 Byte) NAND Flash:
For Large page (2048 + 64 Byte) NAND Flash:
Table 1. Spare area format for small NAND Flash
Logical Index
Block Status
Data Status
Wear Leveling counter
ECC
Table 2. Spare area format for large NAND Flash
Block Status
Data Status
Logical Index
Wear Leveling counter
ECC
STM32 NAND driver blocks UM1653
?The Logical Index contains the logical address of the block.
?The Block Status returns the status of the block if it is valid or not.
?The Data Status informs if the page is valid or invalid.
?Wear Leveling Counter is the number of times the block has been erased.
?The ECC is the error correction code calculated for each page.
NAND INTERFACE
?x8 or x16 bus width
?Multiplexed Address/ Data
?Pinout compatibility for all densities
SUPPLY VOLTAGE
? 1.8V device: VCC = 1.65 to 1.95V
? 3.0V device: VCC = 2.7 to 3.6V
PAGE SIZE
?x8 device: (512 + 16 spare) Bytes
?x16 device: (256 + 8 spare) Words
?x8 device: (2048 + 64 spare) Bytes
?x16 device: (1024 + 32 spare) Words
1.5 NAND pin mapping
I/O 8-15 Data Input/Outputs: for x16 devices. The I/O pins are used to input data,
address, command and output data during read operation.
I/O 0-7Data Input/Outputs: Address Inputs, or Command Inputs for x8 and x16 devices.
ALE Address Latch Enable: When active, an address can be written.
CLE Command Latch Enable: This pin should be LOW while writing commands to the command register.
CE/ Chip Enable: The CE input enables the device. Signal is active low. If the signal is inactive the device will be in standby.
RE/Read Enable: The RE input is the serial data out control. Signal is active low to out data.
RB/ Ready/Busy (open-drain output) The RB output provides the status of the device operation. It is an open drain output, hence should be connected to a GPIO with
pull-up.
?LOW: a program, erase or read operation is in process.
?HIGH: the process is complete.
WE/ Write Enable: The WE input controls write operations to I/O port. Commands,
data and address are latched on the rising edge of WE.
WP/ Write Protect: Typically connected to Vcc, but may also be connected to a GPIO. 10/45DocID025024 Rev 1
2 NAND driver firmware modules
The NAND driver library has the following modules:
1.Garbage collection
2. Wear leveling
3. Bad block management
4. ECC check
5. LUT
6. FAT file system
2.1 Garbage
collection
The Garbage Collection software copies the valid data into a new (free) area and erases the
original invalid data.
Garbage Collection is performed when a virtual block is full or the number of free pages in
the whole device is lower than a specified threshold value.
The basic operations involved in Garbage Collection are the following:
1.The virtual blocks meeting the conditions are selected for erasure.
2. The valid physical pages are copied into a free area.
3. The selected physical blocks are erased.
As virtual blocks can contain more than one physical block, the Garbage Collection may
erase more than one physical block.
2.2 Wear
leveling
Wear leveling is a technique to increase the lifetime of NAND Flash memory. The number of
reliable write cycles in NAND Flash is 100,000 erase/write cycles. If some of the blocks are
written repeatedly, wearing of these blocks will happen earlier than other blocks. To balance
the erase cycles over all the blocks, a wear leveling technique is introduced.
All new data is written to the empty blocks. The memory controller selects the new empty
block based on the number of write / erase cycles it has experienced.
After the new data is written, the controller updates the LUT to point to the position of the
selected physical block. The block containing the old data is erased and the number of
write/erase cycles increments.
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The above figure gives an overview of the firmware flow with respect to the way the Wear Leveling Mechanism is implemented.
Let us consider a scenario in which the host is trying to send the data to the controller via USB and write it to the NAND Flash. The corresponding CBW has to be decoded. The function given below is called in such a case, to write to the memory which uses the information provided from the CBW
void SCSI_Write10_Cmd(uint8_t lun, uint32_t LBA, uint32_t BlockNbr) This function has the following arguments, the logical unit number, Logical block address (LBA) and the block number. The LBA passed from the host is sequential and maps to the address of the block in NAND Flash memory which comes out to be sequential.
A structure is used to store the address:
typedef struct
{
uint16_t Zone;
uint16_t Block;
uint16_t Page;
} NAND_ADDRESS;
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NAND_ADDRESS NAND_GetAddress (uint32_t Address)
The above function translates a logical address into a physical one and stores it in a
structure element of type NAND_ADDRESS.
While writing to the NAND, the wear level algorithm should return the block to be written of
which the erase count is least. To maintain the list of USED, FREE and BAD blocks an array
is maintained: LUT[ ].
The previously fetched address for writing, and the free block obtained with least erase
counts are swapped in LUT and updated, this ensures that the write takes place at the block
with least erase count.
uint16_t NAND_GetFreeBlock (void)
The above function is called to get the free block for swap. The function returns the first free
block it finds in the LUT[ ]. This implies that the LUT[ ] should have the free blocks arranged
in the increasing order of erase count. The LUT[ ] is updated by the following function.
uint16_t NAND_BuildLUT (uint8_t ZoneNbr)
The above function arranges the bad block at the bottom of the array and the used and free
blocks are located in the upper part of the array.
uint16_t NAND_WearLeveling (void)
The above function sorts the free blocks in the ascending order based on the wear level
count. Now, the free block used for writing in the NAND would be the one with the least
erase count.
2.3 ECC
Unlike NOR Flash memory that does not require error correction code, NAND memory
needs to ensure data integrity.
The disadvantage of the NAND configuration is that when a cell is read, the sense amplifier
detects a signal much lower than for the NOR configuration because many transistors are in
series. Therefore access to a cell is not straightforward and must necessarily go through all
the cells in series which reduces precision and makes code error correction required.
There are three error correction codes:
?The Hamming code can correct only one bit error.
?The Reed Solomon code can correct more errors.
?The BCH code can correct many errors and is more efficient than Reed Solomon.
2.3.1 Hamming code for NAND Flash
The Hamming code algorithm used by NAND Flash-based applications calculates two
values of ECC for a data packet. Each bit in the values of ECC parity represents half of the
bits of the data packet.
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For one byte
The trick is how the data bits are partitioned for each of the parity calculations. To calculate ECC, the data bits are first divided into halves, quarters, eighths and so on until you reach the bit unit.
After the partition of the data packet, the parity of each group is calculated to generate two values of ECC. The results are concatenated to form the ECC values.
ECC even = 0 ^ 1 ^ 0 ^ 1, 0 ^ 1 ^ 0 ^ 1, 1 ^ 1 ^ 1 ^ 1 = 000
ECC odd = 0 ^ 1 ^ 0 ^ 1, 0 ^ 1 ^ 0 ^ 1, 0 ^ 0 ^ 0 ^ 0 = 000
These ECC bits allow us to identify the error position when the data packet is analyzed at a later date. Data packets require larger number of ECC values. Each data packet of 2n-bit ECC requires a value of n bits.
Based on this calculation, both the data packet and the ECC values are programmed into the NAND Flash memory. Later, when the data packet is read from the NAND, the ECC values are recalculated. Data corruption is indicated when the values of the newly calculated ECC differ from those programmed into the NAND Flash.
Applying “exclusive or” to all four values of ECC (two old and two new), one can determine whether one or more bits have been corrupted. If the result is 000 there is no corruption. If the result is 111 then a single bit is wrong. If two or more bits were damaged, this code allows the detection of two errors and the correction of only one bit.
ECCeven (old) ^ ECCodd (old) ^ ECCeven (new) ^ ECCodd (new)
When the result shows that a bit has been corrupted, the address of this bit can be identified by the application of “exclusive or” on both ECC odd values
ECCodd (old) ^ ECCodd (new)
The erroneous bit position is identified by the position of the 1 in the "exclusive or" value. For a package of several bytes
As the size of data packets increases, the Hamming algorithm becomes more efficient. Each doubling of the data packet requires two additional bits in the ECC. A data packet size of 512 bytes (the size of a page of the NAND memory used) requires 24 bits of ECC. The extension of a 1 byte packet to a 512 byte packet requires only a change to the size of data partitions, the algorithm remains the same.
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2.3.2 Error detection and correction
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2.4 Bad block management
Bad blocks contain one or more invalid bits whose reliability is not guaranteed. They may be
present when the device is shipped, or may develop during the lifetime of the device.
2.5 Look up table (LUT)
The LUT is used to find the Application Block Number corresponding to the Logical address
(SCSI_LBA). All blocks are scanned and User data is read from the Spare area of each
block of NAND Flash to build the LUT.
system
2.6 File
The free file system used in the NAND library is FAT_FS_ELM from ChaN. The NAND file
system interface module “ff_user_interface.c” allows interfacing of file systems with the
NAND driver. In standalone mode it displays the .bmp images stored in the “pics” folder of
NAND Flash. This module should be ported to the selected file system.
Table 3. File system interface functions
Function Description
disk_initialize Initialize disk drive.
disk_read Interface function for a logical page read.
disk_write Interface function for a logical page write.
for testing if unit is ready.
disk_status Interface
function
features.
device-dependent
disk_ioctl Control
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2.7 NAND driver files
2.7.1 nand_drv.c, nand_drv.h functions
Table 4. NAND_Init Function name NAND_Init.
Prototype uint16_t NAND_Init(void)
Behavior description Initializes NAND Interface
Input parameter None
Output parameter Status of NAND Initialization. This parameter can be: –NAND_OK: when the NAND is OK.
–NAND_FAIL: when NAND fails to initialize.
Table 5. NAND_Write
Function name NAND_Write.
Prototype uint16_t NAND_Write(uint32_t Memory_Offset, uint8_t *Writebuff,
uint16_t Transfer_Length)
Behavior description Writes one sector at once
Input parameter Memory_Offset: Memory Offset. Writebuff: Pointer to the data to be written. Transfer_Length: Number of byte to write.
Output parameter Status of NAND Write. This parameter can be:
–NAND_OK: when the NAND Write is successful –NAND_FAIL: when NAND fails to Write.
Table 6. NAND_Read
Function name NAND_Read.
Prototype uint16_t NAND_Read(uint32_t Memory_Offset, uint8_t *Readbuff,
uint16_t Transfer_Length)
Behavior description Reads sectors.
Input parameter Memory_Offset: Memory Offset. Readbuff: Pointer to store the read data. Transfer_Length: Number of byte to read.
Output parameter Status of NAND Read. This parameter can be:
–NAND_OK: when the NAND Read is successful.
–NAND_FAIL: when NAND fails to Read.
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.Table 7. NAND_WriteECC
Function name NAND_WriteECC.
Prototype uint16_t NAND_WriteECC(uint32_t Memory_Offset, uint8_t *Writebuff,
uint16_t NumByte)
Behavior description Writes one sector & copy rest Block during ECC Correctable Error Case.
Input parameter Memory_Offset: Memory Offset. Writebuff: Pointer to the data to be written. Transfer_Length: Number of byte to write.
Output parameter Status of NAND Write. This parameter can be:
–NAND_OK: when the NAND Write is successful –NAND_FAIL: when NAND fails to Write
Table 8. NAND_PostWriteECC
Function name NAND_PostWriteECC.
Prototype uint16_t NAND_PostWriteECC(void)
Behavior description Copies whole block after writing corrected page in ECC Correction. Input parameter None
Output parameter Status of NAND Write.
Table 9. NAND_CleanLUT
Function name NAND_CleanLUT.
Prototype uint16_t NAND_CleanLUT (uint8_t ZoneNum)
Behavior description Rebuilds the Look Up Table.
Input parameter ZoneNbr: Zone Number to Rebuild the Look Up Table.
Output parameter Status of NAND Build look up table. This parameter can be: –NAND_OK: when the NAND Clean is successful.
–NAND_FAIL: when NAND fails to clean look up table.
Table 10. NAND_WearLeveling
Function name NAND_WearLeveling.
Prototype uint16_t NAND_WearLeveling (uint8_t ZoneNumber) Behavior description Builds the Look Up Table According to the Wear Count. Input parameter ZoneNumber: Zone Number.
Output parameter Status of NAND wear Leveling. This parameter can be:
–NAND_OK: when the NAND wear leveling is successful.–NAND_FAIL: when NAND fails to wear leveling.
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