GD32F105xx-Datasheet-Rev1.1
GigaDevice Semiconductor Inc.
GD32F105xx
ARM? Cortex?-M3 32-bit MCU
Datasheet
Table of Contents
List of Figures (3)
List of Tables (4)
1 General description (5)
2 Device overview (6)
2.1 Device information (6)
2.2 Block diagram (8)
2.3 Pinouts and pin assignment (9)
2.4 Memory map (12)
2.5 Clock tree (13)
2.6 Pin definitions (14)
3 Functional description (22)
3.1 ARM? Cortex?-M3 core (22)
3.2 On-chip memory (22)
3.3 Clock, reset and supply management (23)
3.4 Boot modes (23)
3.5 Power saving modes (24)
3.6 Analog to digital converter (ADC) (24)
3.7 Digital to analog converter (DAC) (25)
3.8 DMA (25)
3.9 General-purpose inputs/outputs (GPIOs) (25)
3.10 Timers and PWM generation (26)
3.11 Real time clock (RTC) (27)
3.12 Inter-integrated circuit (I2C) (27)
3.13 Serial peripheral interface (SPI) (28)
3.14 Universal synchronous asynchronous receiver transmitter (USART) (28)
3.15 Inter-IC sound (I2S) (28)
3.16 Universal serial bus on-the-go full-speed (USB OTG FS) (29)
3.17 Controller area network (CAN) (29)
3.18 External memory controller (EXMC) (29)
3.19 Debug mode (30)
3.20 Package and operation temperature (30)
4 Electrical characteristics (31)
4.1 Absolute maximum ratings (31)
4.2 Recommended DC characteristics (31)
4.3 Power consumption (32)
4.4 EMC characteristics (33)
4.5 Power supply supervisor characteristics (33)
4.6 Electrical sensitivity (34)
4.7 External clock characteristics (34)
4.8 Internal clock characteristics (35)
4.9 PLL characteristics (36)
4.10 Memory characteristics (36)
4.11 GPIO characteristics (36)
4.12 ADC characteristics (37)
4.13 DAC characteristics (37)
4.14 I2C characteristics (37)
4.15 SPI characteristics (38)
5 Package information (39)
6 Ordering Information (41)
7 Revision History (42)
List of Figures
Figure 1. GD32F105xx block diagram (8)
Figure 2. GD32F105Zx LQFP144 pinouts (9)
Figure 3. GD32F105Vx LQFP100 pinouts (10)
Figure 4. GD32F105Rx LQFP64 pinouts (11)
Figure 6. GD32F105xx memory map (12)
Figure 7. GD32F105xx clock tree (13)
Figure 8. LQFP package outline (39)
List of Tables
Table 1. GD32F105xx devices features and peripheral list (6)
Table 2. GD32F105xx pin definitions (14)
Table 3. Absolute maximum ratings (31)
Table 4. DC operating conditions (31)
Table 5. Power consumption characteristics (32)
Table 6. EMS characteristics (33)
Table 7. EMI characteristics (33)
Table 8. Power supply supervisor characteristics (33)
Table 9. ESD characteristics (34)
Table 10. Static latch-up characteristics (34)
Table 11. High speed external clock (HSE) generated from a crystal/ceramic characteristics (34)
Table 12. Low speed external clock (LSE) generated from a crystal/ceramic characteristics (35)
Table 13. High speed internal clock (HSI) characteristics (35)
Table 14. Low speed internal clock (LSI) characteristics (35)
Table 15. PLL characteristics (36)
Table 16. Flash memory characteristics (36)
Table 17. I/O port characteristics (36)
Table 18. ADC characteristics (37)
Table 19. DAC characteristics (37)
Table 20. I2C characteristics (37)
Table 21. SPI characteristics (38)
Table 22. LQFP package dimensions (40)
Table 23. Part ordering code for GD32F105xx devices (41)
Table 24. Revision history (42)
1 General description
The GD32F105xx device belongs to the connectivity line of GD32 MCU Family. It is a 32-bit
general-purpose microcontroller based on the ARM? Cortex?-M3 RISC core with enhanced
connectivity performance and best ratio in terms of processing power, reduced power
consumption and peripheral set. The Cortex?-M3 is a next generation processor core which
is tightly coupled with a Nested Vectored Interrupt Controller (NVIC), SysTick timer and
advanced debug support.
The GD32F105xx device incorporates the ARM?Cortex?-M3 32-bit processor core
operating at 108 MHz frequency with Flash accesses zero wait states to obtain maximum
efficiency. It provides up to 1 MB on-chip Flash memory and up to 96 KB SRAM memory. An
extensive range of enhanced I/Os and peripherals connected to two APB buses. The
devices offer up to three 12-bit ADCs, up to two 12-bit DACs, up to ten general-purpose
16-bit timers, two basic timers plus two PWM advanced-control timer, as well as standard
and advanced communication interfaces: up to three SPIs, two I2Cs, three USARTs, two
UARTs, two I2Ss, two CANs, an USB OTG FS.
The device operates from a 2.6 to 3.6 V power supply and available in –40 to +85 °C
temperature range. Several power saving modes provide the flexibility for maximum
optimization between wakeup latency and power consumption, an especially important
consideration in low power applications.
The above features make the GD32F105xx devices suitable for a wide range of applications,
especially in areas such as industrial control, motor drives, power monitor and alarm
systems, consumer and handheld equipment, POS, vehicle GPS, LED display and so on.
2 Device overview 2.1 Device information
2.2 Block diagram
Figure 1. GD32F105xx block diagram
2.3 Pinouts and pin assignment
Figure 2. GD32F105Zx LQFP144 pinouts
PF2PF3PF7PC6PG8PG7PG6PG5PG4PG3PD15PD14PA3
V SS_4
V DD_4
PA4
PA5
PA6
PA7
PC4
PC5
V DD_3
V SS_3
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PF13
PE7
V DD_2V SS_2NC PA13PA12PA11PA10PA9PA8PC9PC8PC7PG14
PG13
PG12
PG10
PG9
PD7
PD6
V BAT
PC14-OSC32_IN PC15-OSC32_OUT
PF4PF0PF1OSC_IN V SS_10PF5V V PF6PG15
V SSA V V V PD13PD12PD11PD10PD9PD8PB15PB14PB13PB12
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC10
PA15
PA14
PF8PF9PF10V SS_6
V DD_6
PE8
V SS_7
V DD_7
V SS_1V DD_1
V DD_8V SS_8PG2V DD_9V SS_9V DD_10
V SS_11
V DD_11
Figure 3. GD32F105Vx LQFP100 pinouts
OSC_IN OSC_OUT
V SSA V REF-PA1PC6PD15PD14PD13PD12PD11PD10PD9PD8PB15PB14PB13PA3
SS_4
V DD_4
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
V DD_3V SS_3PE1PE0
PB9
PB8
BOOT0
PB7PB6
PB5PB4PB3
PE7
PE8
PE9
PE10
PE11
PB11
V SS_1
V DD_2V SS_2NC PA13PA12PA11PA10PA9PA8PC9PC8PC7PD5
PD4
PD3
PD2
PD1
PD0
V BAT
PC13-TAMPER-RTC
PC14-OSC32_IN PC15-OSC32_OUT
NRST V SS_5V DD_5PA0-WKUP
PE2PA2
PB12
V DD_1
PE3PE4PE5PE6PC0
PC1PC2PC3V V DDA
PD6
PD7
Figure 4. GD32F105Rx LQFP64 pinouts
V SSA PA1PA12PA11PA10PA9PA8PC9PC8PC7PC6PB15PB14PB13PA3
V SS_4
V DD_4
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
V DD_3V SS_3PB9PB8
PB7
PB6
BOOT0
PB5PB4
PB3PD2
PC12
PB10
PB11
V SS_1
V DD_2V SS_2PA13PA15
PA14
V BAT
PC13-TAMPER-RTC
PC14-OSC32_IN PC15-OSC32_OUT
NRST PA0-WKUP
PA2
PB12
V DD_1
PC0PC1PC2PC3V DDA
PC10
PC11
PD1 OSC_OUT
PD0-OSC_IN
2.4 Memory map
Figure 5. GD32F105xx memory map
7
6
5
4
3
2
1
0x0810 0000
0x0010 0000
0x0000 0000
0x0800 0000
0x0808 0000
0x 4000 0000
0x 4000 0400
0x 4000 0800
0x 4000 0C00
0x 4000 1000
0x 4000 1400
0x 4000 1800
0x 4000 1C00
0x 4000 2000
0x 4000 2400
0x 4000 2800
0x 4000 2C00
0x 4000 3000
0x 4000 3400
0x 4000 3800
0x 4000 3C00
0x 4000 4000
0x 4000 4400
0x 4000 4800
0x 4000 4C00
0x 4000 5000
0x 4000 5400
0x 4000 5800
0x 4000 5C00
0x 4000 6400
0x 4000 6800
0x 4000 6C00
0x 4000 7000
0x 4000 7400
0x 4000 7800
0x 4001 0000
0x 4001 0400
0x 4001 0800
0x 4001 0C00
0x 4001 1000
0x 4001 1400
0x 4001 1800
0x 4001 1C00
0x 4001 2000
0x 4001 2400
0x 4001 2800
0x 4001 2C00
0x 4001 3000
0x 4001 3400
0x 4001 3800
0x 4001 3C00
0x 4001 4000
0x 4001 4C00
0x 4001 5000
0x 4001 5400
0x 4001 5800
0x 4002 0000
0x 4002 0400
0x 4002 0800
0x 4002 1000
0x 4002 1400
0x 4002 2000
0x 4002 2400
0x 4002 3000
0x 4002 3400
0x 5000 0000
0x 5000 0400
2.5 Clock tree
Figure 6. GD32F105xx clock tree
Legend:
HSE = High speed external clock
HSI = High speed internal clock
LSE = Low speed external clock
LSI = Low speed internal clock
2.6 Pin definitions