MEMORY存储芯片TMS27C256-15JL中文规格书

TPC10 SERIES CMOS FIELD-PROGRAMMABLE GATE ARRAYS

SRFS001 F D3864, DECEMBER 1989 REVISED FEBRUARY 1993

． ． ．．．． Four Arrays With u p to 2000 Usable E q uivalent Gates Tl Action Logie r " System (TI-ALS) So何ware for: -

ViewLogic ? -Ment 。r ?－。rCAD/SDT Ill rM -Cadence ?/Valid ? Reliable Antifuse Interconnect Built-In Clock Distribution Network Silicon-Gate CM 。S Technology

Deskto p TI-ALS Creates Design Files fo『：-I ／。Pin Assignment -Design Validation -Place and Route -Circuit Timing Analysis -Array Antifuse P『ogra『n『ning -Test and Debug 23E G －旨Z 且Z ＠也唱E 翩W Q －I 1/0 and Perlph町a l Circuits I lnterc 。nnect Tracks TPC10 Series FPGA Die A『chitecture descri p tion

The Texas Instruments (Tl ) TPC10 Series comprises fou 「field-programmable gate arrays (FPGAs ). The TPC1010A, TPC1010B, TPC1020A, and TPC1020B FPGAs are fabricated using the Tl silicon-gate CMOS process. The process features polysilicon gate, source, drain elements, and two levels of copper-doped-aluminum metallization to 「educe internal resistance and enhance performance. Typical die architectu 「e is illustrated above.

These field-programmable devices combine gate-array flexibility with desktop programmability. This combination allows the designer to avoid fabrication cycle times and nonrecurring enginee 「ing charges associated with conventional mask-programmed gate arrays. The FPGAs are uni q ue in that the arrays are fabricated, tested, and ship p ed to the user for programming. The FPGA contains user-configurable inputs, outputs, logic modules, and minimum-skew clock driver with ha「dwired distribution network. The FPGA also includes on-chip diagnostic probe capabilities and security fuses to protect the proprietary design.

Table 1. Product Family Profile

DEVICE

TPC1010A TPC1020A TPC1010B TPC1020B Capacity

Gate array equivalent gates

1200 2000 1200 2000 TIL equivalent packages

34 53 34 53 CMOS Process

1.2μm 1.2μm 1.0μm 1.0μm Logic Modules

295 547 295 547 Flip-Fl 。ps (maximum)

130 273 130 273 Antif uses

112,000 186,000 112,000 186,000 H 。

rizontal Tracks

22 22 22 22 Vertical Tracks 13 13 13 13 2-5

TPC10 SERIES CMOS FIELD-PROGRAMMABLE GATE ARRAYS

SRFS001 F -D3864, DECEMBER 1989 -REVISED FEBRUARY 1993

architecture

device organization

Each FPGA consists of a mat『ix of logic modules arranged in rows separated by channels containing inte『connect tracks. The matrix is surrounded with peripheral inputs, outputs, I/Os, and diagnostic circuits. A partial view of the TPC 1 O Series logic modules with examples of interconnections is illustrated in Figure 2.

Figure 2. Partial View of TPC10 Series lnterc 。nnection Capability

logic module

Each core logic module has the equivalent complexity of four 2-input NANO gates. The module shown in Figure 3, is an 8-input, 1-output gate cluster that can implement hardwired p「imitive gates, Booleans, latches, flip-flops, multiplexers, half or full adder slices, or multiplexed-input flip-flops. The TI-ALS libra「y contains a full spectrum of 2-, 3-, and 4-input AND, NANO, OR, and NOR gate macros covering all derivatives of true and/or complement input combinations. Similar modular implementations, covering the spectrum of true and/or complement input combinations, are included for each functional category of macros in the library. Latches and flip-flops are created by connecting two or more logic modules in the appropriate circuit configuration. The macros are captured, simulated, placed, analyzed, and programmed using the TPC10 design libra「y.

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Figure 3. TPC10 Series Logic Module