AD9511BCPZ;AD9511BCPZ-REEL7;中文规格书,Datasheet资料
1.2 GHz Clock Distribution IC,PLL Core,
Dividers, Delay Adjust, Five Outputs
AD9511 Rev. A
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infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: https://www.sodocs.net/doc/357369516.html, Fax: 781.461.3113?2005 Analog Devices, Inc. All rights reserved.
FEATURES
Low phase noise phase-locked loop core
Reference input frequencies to 250 MHz
Programmable dual-modulus prescaler
Programmable charge pump (CP) current
Separate CP supply (VCP S) extends tuning range
Two 1.6 GHz, differential clock inputs
5 programmable dividers, 1 to 32, all integers
Phase select for output-to-output coarse delay adjust
3 independent 1.2 GHz LVPECL outputs
Additive output jitter 225 fs rms
2 independent 800 MHz/250 MHz LVDS/CMOS clock outputs Additive output jitter 275 fs rms
Fine delay adjust on 1 LVDS/CMOS output
Serial control port
Space-saving 48-lead LFCSP
APPLICATIONS
Low jitter, low phase noise clock distribution
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers
High performance instrumentation
Broadband infrastructure
FUNCTIONAL BLOCK DIAGRAM
5
2
8
6
-
1
CLK2
STATUS
CLK2B
OUT0
OUT0B
OUT1
OUT1B
OUT2
OUT2B
OUT3
OUT3B
OUT4
OUT4B CLK1
CLK1B
REFIN
REFINB
FUNCTION
SCLK
SDIO
SDO
CSB
CP
Figure 1.
GENERAL DESCRIPTION
The AD9511 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. The PLL section consists of a programmable reference divider (R); a low noise phase frequency detector (PFD); a precision charge pump (CP); and a programmable feedback divider (N). By connecting an external VCXO or VCO to the CLK2/CLK2B pins, frequencies up to 1.6 GHz may be synchronized to the input reference.
There are five independent clock outputs. Three outputs are LVPECL (1.2 GHz), and two are selectable as either LVDS (800 MHz) or CMOS (250 MHz) levels. Each output has a programmable divider that may be bypassed or set to divide by any integer up to 32. The phase of one clock output relative to another clock output may be varied by means of a divider phase select function that serves as a coarse timing adjustment. One of the LVDS/CMOS outputs features a programmable delay element with full-scale ranges up to 10 ns of delay. This fine tuning delay block has 5-bit resolution, giving 32 possible delays from which to choose for each full-scale setting.
The AD9511 is ideally suited for data converter clocking applications where maximum converter performance is achieved by encode signals with subpicosecond jitter.
The AD9511 is available in a 48-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5.5 V. The temperature range is ?40°C to +85°C.
AD9511
Rev. A | Page 2 of 60
TABLE OF CONTENTS
Specifications.....................................................................................4 PLL Characteristics......................................................................4 Clock Inputs..................................................................................5 Clock Outputs...............................................................................6 Timing Characteristics................................................................7 Clock Output Phase Noise..........................................................9 Clock Output Additive Time Jitter...........................................12 PLL and Distribution Phase Noise and Spurious...................14 Serial Control Port.....................................................................15 FUNCTION Pin.........................................................................15 STATUS Pin................................................................................16 Power............................................................................................16 Timing Diagrams............................................................................17 Absolute Maximum Ratings..........................................................18 Thermal Characteristics............................................................18 ESD Caution................................................................................18 Pin Configuration and Function Descriptions...........................19 Terminology....................................................................................21 Typical Performance Characteristics...........................................22 Typical Modes of Operation..........................................................26 PLL with External VCXO/VCO Followed by Clock
Distribution.................................................................................26 Clock Distribution Only............................................................26 PLL with External VCO and Band-Pass Filter Followed by Clock Distribution......................................................................27 Functional Description..................................................................29 Overall..........................................................................................29 PLL Section.................................................................................29 PLL Reference Input—REFIN..............................................29 VCO/VCXO Clock Input—CLK2........................................29 PLL Reference Divider—R....................................................29 VCO/VCXO Feedback Divider—N (P , A, B) (29)
A and
B Counters...................................................................30 Determining Values for P , A, B, and R................................30 Phase Frequency Detector (PFD) and Charge Pump.......31 Antibacklash Pulse.................................................................31 STATUS Pin............................................................................31 PLL Digital Lock Detect........................................................31 PLL Analog Lock Detect.......................................................32 Loss of Reference....................................................................32 FUNCTION Pin.........................................................................32 RESETB: 58h<6:5> = 00b (Default).....................................32 SYNCB: 58h<6:5> = 01b.......................................................32 PDB: 58h<6:5> = 11b............................................................33 Distribution Section...................................................................33 CLK1 and CLK2 Clock Inputs..................................................33 Dividers........................................................................................33 Setting the Divide Ratio........................................................33 Setting the Duty Cycle...........................................................33 Divider Phase Offset..............................................................37 Delay Block.................................................................................38 Calculating the Delay............................................................38 Outputs........................................................................................38 Power-Down Modes..................................................................39 Chip Power-Down or Sleep Mode—PDB...........................39 PLL Power-Down...................................................................39 Distribution Power-Down....................................................39 Individual Clock Output Power-Down...............................39 Individual Circuit Block Power-Down................................39 Reset Modes................................................................................40 Power-On Reset—Start-Up Conditions when VS
is Applied.................................................................................40 Asynchronous Reset via the FUNCTION Pin...................40 Soft Reset via the Serial Port. (40)
AD9511
Rev. A | Page 3 of 60
Single-Chip Synchronization.....................................................40 SYNCB—Hardware SYNC....................................................40 Soft SYNC—Register 58h<2>...............................................40 Multichip Synchronization.. (40)
Serial Control Port..........................................................................41 Serial Control Port Pin Descriptions........................................41 General Operation of Serial Control Port...............................41 Framing a Communication Cycle with CSB.......................41 Communication Cycle—Instruction Plus Data..................41 Write.........................................................................................41 Read..........................................................................................42 The Instruction Word (16 Bits).................................................42 MSB/LSB First Transfers............................................................42 Register Map and Description.......................................................45 Summary Table............................................................................45 Register Map Description..........................................................47 Power Supply...................................................................................54 Power Management....................................................................54 Applications.....................................................................................55 Using the AD9511 Outputs for ADC Clock Applications....55 CMOS Clock Distribution.........................................................55 LVPECL Clock Distribution......................................................56 LVDS Clock Distribution...........................................................56 Power and Grounding Considerations and Power Supply
Rejection.......................................................................................56 Outline Dimensions........................................................................57 Ordering Guide (57)
REVISION HISTORY
6/05—Rev. 0 to Rev. A
Changes to Features..........................................................................1 Changes to General Description.....................................................1 Changes to Table 1 and Table 2.......................................................5 Changes to Table 4............................................................................7 Changes to Table 5............................................................................9 Changes to Table 6..........................................................................14 Changes to Table 8 and Table 9.....................................................15 Changes to Table 11........................................................................16 Changes to Table 13........................................................................20 Changes to Figure 19 to Figure 23................................................24 Changes to Figure 30 and Figure 31.............................................26 Changes to Figure 32......................................................................27 Changes to Figure 33......................................................................28 Changes to VCO/VCXO Clock Input—CLK2 Section..............29 Changes to PLL Reference Divider—P Section...........................29 Changes to A and B Counters Section.........................................30 Changes to PLL Digital Lock Detect Section..............................31 Changes to PLL Analog Lock Detect Section..............................32 Changes to Loss of Reference Section..........................................32 Changes to FUNCTION Pin Section...........................................32 Changes to RESETB: 58h<6:5> = 00b (Default) Section...........32 Changes to SYNCB: 58h<6:5> = 01b Section..............................32 Changes to CLK1 and CLK2 Clock Inputs Section....................33 Changes to Divider Phase Offset Section....................................37 Changes to Individual Clock Output Power-Down Section.....39 Changes to Individual Circuit Block Power-Down Section......39 Changes to Soft Reset via the Serial Port Section.......................40 Changes to Multichip Synchronization Section..........................40 Changes to Serial Control Port Section.......................................41 Changes to Serial Control Port Pin Descriptions Section.........41 Changes to General Operation of Serial
Control Port Section.......................................................................41 Added Framing a Communication Cycle with CSB Section....41 Added Communication Cycle—Instruction Plus
Data Section.....................................................................................41 Changes to Write Section...............................................................41 Changes to Read Section................................................................42 Changes to Instruction Word (16 Bits) Section..........................42 Changes to Table 20........................................................................42 Changes to MSB/LSB First Transfers Section..............................42 Added Figure 52; Renumbered Sequentially...............................44 Changes to Table 23........................................................................45 Changes to Table 24........................................................................47 Changes to Power Supply (54)
4/05—Revision 0: Initial Version
AD9511
Rev. A | Page 4 of 60
SPECIFICATIONS
Typical (typ) is given for V S = 3.3 V ± 5%; V S ≤ VCP S ≤ 5.5 V , T A = 25°C, R SET = 4.12 kΩ, CPR SET = 5.1 kΩ, unless otherwise noted. Minimum (min) and maximum (max) values are given over full V S and T A (?40°C to +85°C) variation.
PLL CHARACTERISTICS
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments REFERENCE INPUTS (REFIN) Input Frequency 0 250 MHz Input Sensitivity 150 mV p-p Self-Bias Voltage, REFIN 1.45 1.60 1.75 V Self-bias voltage of REFIN 1. Self-Bias Voltage, REFINB 1.40 1.50 1.60 V Self-bias voltage of REFINB 1. Input Resistance, REFIN 4.0 4.9 5.8 kΩ Self-biased 1. Input Resistance, REFINB 4.5 5.4 6.3 kΩ Self-biased 1. Input Capacitance 2 pF PHASE/FREQUENCY DETECTOR (PFD) PFD Input Frequency 100 MHz Antibacklash pulse width 0Dh<1:0> = 00b. PFD Input Frequency 100 MHz Antibacklash pulse width 0Dh<1:0> = 01b. PFD Input Frequency 45 MHz Antibacklash pulse width 0Dh<1:0> = 10b. Antibacklash Pulse Width 1.3 ns 0Dh<1:0> = 00b. (This is the default setting.) Antibacklash Pulse Width 2.9 ns 0Dh<1:0> = 01b. Antibacklash Pulse Width 6.0 ns 0Dh<1:0> = 10b. CHARGE PUMP (CP) I CP Sink/Source Programmable.
High Value 4.8 mA
Low Value 0.60 mA With CPR SET = 5.1 kΩ. Absolute Accuracy 2.5 % V CP = VCP S /2. CPR SET Range 2.7/10 kΩ I CP Three-State Leakage 1 nA Sink-and-Source Current Matching 2 % 0.5 < V CP < VCP S ? 0.5 V. I CP vs. V CP 1.5 % 0.5 < V CP < VCP S ? 0.5 V. I CP vs. Temperature 2 % V CP = VCP S /2 V.
RF CHARACTERISTICS (CLK2)2
Input Frequency 1.6 GHz Frequencies > 1200 MHz (LVPECL) or
800 MHz (LVDS) require a minimum
divide-by-2 (see the Distribution Section).
Input Sensitivity 150 mV p-p Input Common-Mode Voltage, V CM 1.5 1.6 1.7 V Self-biased; enables ac coupling. Input Common-Mode Range, V CMR 1.3 1.8 V With 200 mV p-p signal applied. Input Sensitivity, Single-Ended 150 mV p-p CLK2 ac-coupled; CLK2B capacitively
bypassed to RF ground.
Input Resistance 4.0 4.8 5.6 kΩ Self-biased. Input Capacitance 2 pF CLK2 VS. REFIN DELAY 500 ps Difference at PFD. PRESCALER (PART OF N DIVIDER) See the VCO/VCXO Feedback Divider—N (P, A, B)
section.
Prescaler Input Frequency P = 2 DM (2/3) 600 MHz P = 4 DM (4/5) 1000 MHz P = 8 DM (8/9) 1600 MHz P = 16 DM (16/17) 1600 MHz P = 32 DM (32/33) 1600 MHz CLK2 Input Frequency for PLL 300 MHz A, B counter input frequency.
AD9511
Rev. A | Page 5 of 60
Parameter Min Typ Max Unit Test Conditions/Comments NOISE CHARACTERISTICS
In-Band Noise of the Charge Pump/ Phase Frequency Detector (In-Band Means Within the LBW of the PLL) The synthesizer phase noise floor is
estimated by measuring the in-band phase noise at the output of the VCO and
subtracting 20logN (where N is the N divider value).
@ 50 kHz PFD Frequency ?172 dBc/Hz @ 2 MHz PFD Frequency ?156 dBc/Hz @ 10 MHz PFD Frequency ?149 dBc/Hz @ 50 MHz PFD Frequency ?142 dBc/Hz PLL Figure of Merit ?218 + 10 × log (f PFD ) dBc/Hz Approximation of the PFD/CP phase noise
floor (in the flat region) inside the PLL loop
bandwidth. When running closed loop this phase noise is gained up by 20 × log(N)3.
PLL DIGITAL LOCK DETECT WINDOW 4 Signal available at STATUS pin
when selected by 08h<5:2>.
Required to Lock
(Coincidence of Edges)
Selected by Register ODh. Low Range (ABP 1.3 ns, 2.9 ns Only) 3.5 ns <5> = 1b. High Range (ABP 1.3 ns, 2.9 ns) 7.5 ns <5> = 0b. High Range (ABP 6 ns) 3.5 ns <5> = 0b. To Unlock After Lock (Hysteresis)4 Selected by Register 0Dh. Low Range (ABP 1.3 ns, 2.9 ns Only) 7 ns <5> = 1b. High Range (ABP 1.3 ns, 2.9 ns) 15 ns <5> = 0b. High Range (ABP 6 ns) 11 ns <5> = 0b.
1 REFIN and REFINB self-bias points are offset slightly to avoid chatter on an open input condition.
2
CLK2 is electrically identical to CLK1; the distribution only input can be used as differential or single-ended input (see the Clock Inputs section). 3
Example: ?218 + 10 × log(f PFD ) + 20 × log(N) should give the values for the in-band noise at the VCO output. 4
For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.
CLOCK INPUTS
Table 2.
Parameter
Min Typ Max Unit Test Conditions/Comments CLOCK INPUTS (CLK1, CLK2)1
Input Frequency 0 1.6 GHz Input Sensitivity 1502 mV p-p Jitter performance can be improved with higher slew
rates (greater swing).
Input Level
23V p-p Larger swings turn on the protection diodes and can
degrade jitter performance.
Input Common-Mode Voltage, V CM 1.5 1.6 1.7 V Self-biased; enables ac coupling. Input Common-Mode Range, V CMR 1.3 1.8 V With 200 mV p-p signal applied; dc-coupled. Input Sensitivity, Single-Ended 150 mV p-p CLK2 ac-coupled; CLK2B ac bypassed to RF ground. Input Resistance 4.0 4.8 5.6 kΩ Self-biased. Input Capacitance
2 pF
1 CLK1 and CLK
2 are electrically identical; each can be used as either differential or single-ended input.
2
With a 50 Ω termination, this is ?12.5 dBm. 3
With a 50 Ω termination, this is +10 dBm.
AD9511
Rev. A | Page 6 of 60
CLOCK OUTPUTS
Table 3.
Parameter Min Typ Max Unit Test Conditions/Comments LVPECL CLOCK OUTPUTS Termination = 50 Ω to V S ? 2 V OUT0, OUT1, OUT2; Differential Output level 3Dh (3Eh) (3Fh)<3:2> = 10b Output F requency 1200 MHz See Figure 21
Output High Voltage (V OH ) V S ? 1.22 V S ? 0.98 V S ? 0.93 V Output Low Voltage (V OL ) V S ? 2.10 V S ? 1.80 V S ? 1.67 V Output Differential Voltage (V OD ) 660 810 965 mV LVDS CLOCK OUTPUTS Termination = 100 Ω differential; default OUT3, OUT4; Differential Output level 40h (41h)<2:1> = 01b
3.5 mA termination current
Output F requency 800 MHz See Figure 22
Differential Output Voltage (V OD ) 250 360 450 mV Delta V OD 25 mV Output Offset Voltage (V OS ) 1.125 1.23 1.375 V Delta V OS 25 mV Short-Circuit Current (I SA , I SB ) 14 24 mA Output shorted to GND CMOS CLOCK OUTPUTS OUT3, OUT4 Single-ended measurements;
B outputs: inverted, termination open
Output F requency 250 MHz With 5 pF load each output; see Figure 23
Output Voltage High (V OH ) V S -0.1 V @ 1 mA load Output Voltage Low (V OL ) 0.1 V @ 1 mA load
AD9511
Rev. A | Page 7 of 60
TIMING CHARACTERISTICS
Table 4.
Parameter Min Typ Max Unit Test Conditions/Comments LVPECL
Termination = 50 Ω to V S ? 2 V
Output level 3Dh (3Eh) (3Fh)<3:2> = 10b
Output Rise Time, t RP 130 180 ps 20% to 80%, measured differentially Output Fall Time, t FP
130 180 ps 80% to 20%, measured differentially PROPAGATION DELAY, t PECL , CLK-TO-LVPECL OUT 1
Divide = Bypass 335 490 635 ps Divide = 2 ? 32
375 545 695 ps Variation with Temperature 0.5 ps/°C OUTPUT SKEW, LVPECL OUTPUTS OUT1 to OUT0 on Same Part, t SKP 270 100 140 ps OUT1 to OUT2 on Same Part, t SKP 215 45 80 ps OUT0 to OUT2 on Same Part, t SKP 2
45 65 90 Ps All LVPECL OUT Across Multiple Parts, t SKP_AB 3 275 ps Same LVPECL OUT Across Multiple Parts, t SKP_AB 3 130 ps
LVDS
Termination = 100 Ω differential
Output level 40h (41h) <2:1> = 01b 3.5 mA termination current
Output Rise Time, t RL
200 350 ps 20% to 80%, measured differentially Output Fall Time, t FL
210 350 ps 80% to 20%, measured differentially PROPAGATION DELAY, t LVDS , CLK-TO-LVDS OUT 1
Delay off on OUT4 OUT3 to OUT4 Divide = Bypass 0.99 1.33 1.59 ns Divide = 2 ? 32
1.04 1.38 1.64 ns Variation with Temperature 0.9 ps/°C OUTPUT SKEW, LVDS OUTPUTS Delay off on OUT4 OUT3 to OUT4 on Same Part, t SKV 2
?85 +270 ps All LVDS OUTs Across Multiple Parts, t SKV_AB 3 450 ps Same LVDS OUT Across Multiple Parts, t SKV_AB 3 325 ps CMOS
B outputs are inverted; termination = open Output Rise Time, t R
C 681 865 ps 20% to 80%; C LOA
D = 3 pF Output Fall Time, t FC
646 992 ps 80% to 20%; C LOAD = 3 pF PROPAGATION DELAY, t CMOS , CLK-TO-CMOS OUT 1
Delay off on OUT4 Divide = Bypass 1.02 1.39 1.71 ns Divide = 2 ? 32
1.07 1.44 1.76 ns Variation with Temperature 1 ps/°C OUTPUT SKEW, CMOS OUTPUTS Delay off on OUT4 OUT3 to OUT4 on Same Part, t SKC 2
?140 +145 +300 All CMOS OUT Across Multiple Parts, t SKC_AB 3 650 ps Same CMOS OUT Across Multiple Parts, t SKC_AB 3 500 ps
LVPECL-TO-LVDS OUT Everything the same; different logic type Output Skew, t SKP_V
0.74 0.92 1.14 ns LVPECL to LVDS on same part
LVPECL-TO-CMOS OUT Everything the same; different logic type Output Skew, t SKP_C 0.88 1.14 1.43 ns LVPECL to CMOS on same part LVDS-TO-CMOS OUT Everything the same; different logic type Output Skew, t SKV_C 158 353 506 ps LVDS to CMOS on same part
AD9511
Rev. A | Page 8 of 60
Parameter Min Typ Max Unit Test Conditions/Comments
DELAY ADJUST
OUT4; LVDS and CMOS Shortest Delay Range 4
35h <5:1> 11111b Zero Scale 0.05 0.36 0.68 ns 36h <5:1> 00000b Full Scale
0.72 1.12 1.51 ns 36h <5:1> 11111b Linearity, DNL 0.5 LSB Linearity, INL 0.8 LSB Longest Delay Range 4
35h <5:1> 00000b Zero Scale 0.20 0.57 0.95 ns 36h <5:1> 00000b Full Scale
9.0 10.2 11.6 ns 36h <5:1> 11111b Linearity, DNL 0.3 LSB Linearity, INL
0.6 LSB Delay Variation with Temperature Long Delay Range, 10 ns 5
Zero Scale 0.35 ps/°C F ull Scale
?0.14 ps/°C Short Delay Range, 1 ns 5
Zero Scale 0.51 ps/°C F ull Scale
0.67 ps/°C
1 The measurements are for CLK1. For CLK2, add approximately 25 ps.
2
This is the difference between any two similar delay paths within a single device operating at the same voltage and temperature. 3
This is the difference between any two similar delay paths across multiple devices operating at the same voltage and temperature. 4
Incremental delay; does not include propagation delay. 5
All delays between zero scale and full scale can be estimated by linear interpolation.
AD9511
Rev. A | Page 9 of 60
CLOCK OUTPUT PHASE NOISE
Table 5.
Parameter Min Typ Max Unit Test Conditions/Comments CLK1-TO-LVPECL ADDITIVE PHASE NOISE Distribution Section only; does not
include PLL or external VCO/VCXO
CLK1 = 622.08 MHz, OUT = 622.08 MHz Input slew rate > 1 V/ns Divide Ratio = 1 @ 10 Hz Offset ?125 dBc/Hz @ 100 Hz Offset ?132 dBc/Hz @ 1 kHz Offset ?140 dBc/Hz @ 10 kHz Offset ?148 dBc/Hz @ 100 kHz Offset ?153 dBc/Hz >1 MHz Offset ?154 dBc/Hz CLK1 = 622.08 MHz, OUT = 155.52 MHz Divide Ratio = 4 @ 10 Hz Offset ?128 dBc/Hz @ 100 Hz Offset ?140 dBc/Hz @ 1 kHz Offset ?148 dBc/Hz @ 10 kHz Offset ?155 dBc/Hz @ 100 kHz Offset ?161 dBc/Hz >1 MHz Offset ?161 dBc/Hz CLK1 = 622.08 MHz, OUT = 38.88 MHz Divide Ratio = 16 @ 10 Hz Offset ?135 dBc/Hz @ 100 Hz Offset ?145 dBc/Hz @ 1 kHz Offset ?158 dBc/Hz @ 10 kHz Offset ?165 dBc/Hz @ 100 kHz Offset ?165 dBc/Hz >1 MHz Offset ?166 dBc/Hz CLK1 = 491.52 MHz, OUT = 61.44 MHz Divide Ratio = 8 @ 10 Hz Offset ?131 dBc/Hz @ 100 Hz Offset ?142 dBc/Hz @ 1 kHz Offset ?153 dBc/Hz @ 10 kHz Offset ?160 dBc/Hz @ 100 kHz Offset ?165 dBc/Hz >1 MHz Offset ?165 dBc/Hz CLK1 = 491.52 MHz, OUT = 245.76 MHz Divide Ratio = 2 @ 10 Hz Offset ?125 dBc/Hz @ 100 Hz Offset ?132 dBc/Hz @ 1 kHz Offset ?140 dBc/Hz @ 10 kHz Offset ?151 dBc/Hz @ 100 kHz Offset ?157 dBc/Hz >1 MHz Offset ?158 dBc/Hz CLK1 = 245.76 MHz, OUT = 61.44 MHz Divide Ratio = 4 @ 10 Hz Offset ?138 dBc/Hz @ 100 Hz Offset ?144 dBc/Hz @ 1 kHz Offset ?154 dBc/Hz @ 10 kHz Offset ?163 dBc/Hz @ 100 kHz Offset ?164 dBc/Hz >1 MHz Offset ?165 dBc/Hz
AD9511
Rev. A | Page 10 of 60
Parameter Min Typ Max Unit Test Conditions/Comments CLK1-TO-LVDS ADDITIVE PHASE NOISE Distribution Section only; does not
include PLL or external VCO/VCXO
CLK1 = 622.08 MHz, OUT= 622.08 MHz Divide Ratio = 1 @ 10 Hz Offset ?100 dBc/Hz @ 100 Hz Offset ?110 dBc/Hz @ 1 kHz Offset ?118 dBc/Hz @ 10 kHz Offset ?129 dBc/Hz @ 100 kHz Offset ?135 dBc/Hz @ 1 MHz Offset ?140 dBc/Hz >10 MHz Offset ?148 dBc/Hz CLK1 = 622.08 MHz, OUT = 155.52 MHz Divide Ratio = 4 @ 10 Hz Offset ?112 dBc/Hz @ 100 Hz Offset ?122 dBc/Hz @ 1 kHz Offset ?132 dBc/Hz @ 10 kHz Offset ?142 dBc/Hz @ 100 kHz Offset ?148 dBc/Hz @ 1 MHz Offset ?152 dBc/Hz >10 MHz Offset ?155 dBc/Hz CLK1 = 491.52 MHz, OUT = 245.76 MHz Divide Ratio = 2 @ 10 Hz Offset ?108 dBc/Hz @ 100 Hz Offset ?118 dBc/Hz @ 1 kHz Offset ?128 dBc/Hz @ 10 kHz Offset ?138 dBc/Hz @ 100 kHz Offset ?145 dBc/Hz @ 1 MHz Offset ?148 dBc/Hz >10 MHz Offset ?154 dBc/Hz CLK1 = 491.52 MHz, OUT = 122.88 MHz Divide Ratio = 4 @ 10 Hz Offset ?118 dBc/Hz @ 100 Hz Offset ?129 dBc/Hz @ 1 kHz Offset ?136 dBc/Hz @ 10 kHz Offset ?147 dBc/Hz @ 100 kHz Offset ?153 dBc/Hz @ 1 MHz Offset ?156 dBc/Hz >10 MHz Offset ?158 dBc/Hz CLK1 = 245.76 MHz, OUT = 245.76 MHz Divide Ratio = 1 @ 10 Hz Offset ?108 dBc/Hz @ 100 Hz Offset ?118 dBc/Hz @ 1 kHz Offset ?128 dBc/Hz @ 10 kHz Offset ?138 dBc/Hz @ 100 kHz Offset ?145 dBc/Hz @ 1 MHz Offset ?148 dBc/Hz >10 MHz Offset ?155 dBc/Hz CLK1 = 245.76 MHz, OUT = 122.88 MHz Divide Ratio = 2 @ 10 Hz Offset ?118 dBc/Hz @ 100 Hz Offset ?127 dBc/Hz @ 1 kHz Offset ?137 dBc/Hz @ 10 kHz Offset ?147 dBc/Hz
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AD9511BCPZ AD9511BCPZ-REEL7