A CURRENT LIMITER FOR LDO REGULATORS WITH INTERNAL COMPENSATION FOR PROCESS AND TEMPERATURE

A CURRENT LIMITER FOR LDO REGULATORS WITH INTERNAL COMPENSATION FOR PROCESS AND TEMPERATURE VARIATIONS

Jader A. De Lima & Wallace A. Pimenta

Brazil Semiconductor Technology Center - Freescale Semiconductor

13069-380 Campinas – SP Brazil

A c urrent limiter that sec urely c lamps the LDO output c urrent upon load over-c urrent is presented. Although the approac h relies on absolute values of parameters suc h as resistanc e and MOSFET threshold voltage on subsequent I/V and V/I c onversions of the LDO sensed c urrent, a reference current to the arbitration circuit is derived in such a manner that the dependence of the clamping value I CLP on process and temperature variations is canceled out at good extent. Furthermore, the sense c irc uit uses a p-MOSFET depletion devic e to c omply with very low dropouts. For a

nominal value of 750mA, minimum and maximum simulated

values of I CLP are 570mA and 930mA, respec tively, for a broad biases, proc ess spread and temperatures ranging from -40o C to 150o C. An LDO with 400mA-c

urrent capability and 250mV-dropout embedding the proposed limiter was integrated on a high-voltage pro c ess. Experimental data attest the c lamping func tionality and accuracy of the proposed circuit for low and large dropouts.

I.

INTRODUCTION

Current sensing is an essential feature on smart power designs. Almost all switching and linear DC/DC regulators sense the current delivered to the load for either fast over-current protection or current feedback control [1-5]. Fault protection is commonly available in most of power management chips to date and its accuracy highly praised, mainly in cases where driving capability may reach a few Amperes, or even above. By clamping the delivered current to a safe value, the current limiter embedded on the regulator must promptly act to protect the chip against catastrophic failures hassled by load over-currents. Since the limiter should not interfere with the regulator normal operation, the current clamping value I CLP must precisely fall into an interval whose limits are imposed by the regulator maximum current and the current beyond which thermal dissipation would endanger the power device and/or the chip integrity.

Many voltage-mode current sensing methods on Low Dropout (LDO) regulators employ a sense transistor M SNS placed in parallel with a pass transistor M P , while exhibiting an aspect-ratio significantly smaller than the latter. To some extension, the sensed current I SNS corresponds then to a scaled down version of pass transistor current I P and it is

converted to a voltage V SNS across a sense resistor R SNS in series with M SNS . However, since both M P and M SNS usually operate on triode region to meet a low drop-out condition, the voltage drop V SNS across R SNS mismatches their drain-source voltages, and consequently the ratio I SNS /I P . Moreover, the exactness of the conversion of I SNS into V SNS is limited to the manufacturing tolerances that affect the absolute value of R SNS , not to mention its variation with temperature.

A resistor-less current sensor for DC/DC regulators using an opamp can also be employed. In this case, pass and sense transistors have identical drain and gate voltages, whereas their source voltages are virtually short-circuited. However, for high-accuracy low-dropout applications, this solution heavily relies on amplifiers with offset voltages limited to only a few mV to ensure small deviations on mirrored currents. Such a design task becomes even more complex as the opamp input devices must withstand high voltages and be biased by large currents to attain a broad bandwidth and handle fast arbitrations of current limitation.

Generally, the trimming of the current limitation value has been a feasible solution on commercial chips to improve accuracy against non-idealities and process variation. However, it demands dedicated bit registers and fuse cells, which enlarge the die size. In addition, production test time is stretched, further increasing overall costs.

This paper introduces a sense-resistor current limiter for LDO regulators with internal compensation for process and temperature variations. This approach is devised for a LDO with n-channel pass transistor, which represents a more complex current sensor design with respect to p-channel counterparts. A reference current I REF is internally generated following identical I/V and V/I conversions of the sensed current, so that absolute values of I SNS and I REF are first-order similarly affected by fabrication process and temperature spread. Both currents are then input into an arbitration circuit that flags an over-current whenever I LOAD reaches I TH , where I TH is the threshold for current limitation. Upon flag detection, the current delivered to the load is clamped to I CLP and the system main logic signalized. Since I CLP shows relatively small deviations with process, voltage and temperature (PVT), trimming may not be required, making the proposal attractive for low-cost power-management chips.

978-1-4244-1684-4/08/$25.00 ?2008 IEEE 2238

II. CURRENT LIMITER DESCRIPTION Figure 1 shows the LDO schematic with current limiter. The LDO power input and output voltages are PV IN and V OUT , respectively, and basically consists of an opamp supplied by V SUP , n-MOSFET pass transistor M P , a current sensor made up of M SNS , R SNS and M 1 and a current limiter. Voltage feedback is established by resistors R 1 and R 2. The LDO delivers a current I LOAD to a resistive load R LOAD .

The sense transistor M SNS corresponds to a scaled down version, by a factor N, of M P . Upon low-dropout scenarios, which commonly occur for high current LDO regulators, both M P and M SNS operate on triode region, so that current mirroring between I P and I SNS is affected by different drain-source voltages due to the voltage drop on R SNS . Such a deviation is accounted during design and appears as a spread on the current limitation value with respect to PV IN -V OUT . I SNS biases then R SNS , defining I 1 for a given aspect-ratio of M 1. The use of a depletion-mode p-MOSFET M 1 complies with requirements of low-dropout voltages between PV IN and V OUT . Such a device is usually available in high-voltage integration processes, so that it represents a feasible

alternative for LDO designs in power management chips.

Figure 1. Block diagram of a LDO with current limiter

The proposed current limiter is depicted in Figure 2. It comprises a current subtractor M 1, M 2 and M 3, and a reference-current generator composed by R SNS ’, M 1’, M 6, M 7. A simple digital block with an inverter and a deglitcher completes the limiter. Upon over-current arbitration, FLAG signal is asserted, enabling the system control logic to take

some protective decision, such as to turn the regulator off.

Figure 2. Current limiter schematic

The current I 1 enters into a current subtractor to be compared with a reference current I 2 = M I REF , where M is the mirroring factor between M 2 and M 5. In case of over-current, the resulting current I 3 = I 1 – I 2 (for I

1 I 2) flows through M 3 and is copied to M 4 by a factor S. In turn, I 4 is compared to a current source I B . Under normal operation I LOAD < I TH , so that I 4= 0 and no impact on the LDO occurs. Upon over-current, I

4 I B , the gate voltage of common-drain p-MOSFET M 8 decreases. Because the source of M 8 is connected to the gate of the LDO pass-transistor M P , the driving voltage V GATE is also lowered. As the LDO loses regulation, V OUT is brought down to 0V, clamping I LOAD to I CLP . FLAG is then asserted and after a delay enables the system control logic to take a protective action, such as powering off the LDO to keep power dissipation under safety values. Stability of the current limiter is ensured by capacitor C 1.

II.1 Compensation for Process and Temperature Spread Since I SNS is converted into a voltage drop across R SNS and then re-converted into I 1 by means of M 1, the resulting I 1is affected by the dependence of R SNS and the threshold voltage V TH1 of M 1 on process and temperature variations. If I 2 were a constant current source, a large spread on I 4 due to such spread would happen, causing similar dependence on I CLP . To overcome this limitation, I 2 is generated by a circuit structurally alike the one that imposes I 1. In the compensation-current generator comprised by R SNS ’, M 1’, M 6 and M 7, reference current I REF ’ is first converted into a voltage across R SNS ’ and then re-converted into a current I REF through M 1’. At first order, I REF is thus subjected to similar process variations on I 1.

A relationship between I 1 and I CLP can then be established through R SNS . Upon current limitation, one has I SNS = I CLP /N and V GS1 = R SNS I CLP /N. Clamping is triggered when I 4 = I

B , so that R SNS

can be sized by

I 1 due to process

spread is I 1=R SNS

(R

SNS

V TH1

(

, with

SNS

TH SNS SNS SNS

I V I R R I 11

1

where 1=(W/L)1p C ox . Similarly, adopting ideal matching between M 1 and M 1’ (V TH1 = V TH1’), one has I REF = R SNS ’

(

RE R

S V TH1

(

RE V T

, with

I 1 – I 2 = I 1 – M I REF = 0, a first-order cancellation for process and temperature dependence on I CLP

can be achieved. Straight manipulation yields

2

'REF 21TH 2'REF 2

'

REF 1TH

'

REF 1TH

'

SNS

I 2k

V I 4I V 4I V 2R PV IN 6.0V and 0.7V V OUT 3.6V. Maximum

load current on normal operation is 400mA, whereas nominal I CLP is set to 0.75A. Other parameters are V SUP =

7V, I REF = 26 A and I B = 2.5 A. Both conditions of maximum and minimum dropouts, respectively 5.3V and 250mV, are considered to endorse the good performance of the current limiter at such extremes.

The spread on I TH with bias, external components, fabrication process and temperature variations was also analyzed and represented on the histogram shown in Figure 3. Average value of I TH is 776mA, with standard deviation

( of

I TH 1076mA upon 3-variation. Temperature varies from -40o C to 150o C.

Figure 4 displays the simulated waveforms of the LDO on a stand-alone configuration. PV IN = 1.5V and V OUT = 1.25V, so that a low dropout of 250mV results. An external current source I LOAD_SOURCE

is stepped up to 1A and tries to mirror its value to I LOAD . As it can be seen, I LOAD is clamped to 875mA. Normal operation holds up to I LOAD = 400mA, with V OUT = 1.25V and I 4 0 (50pA). Similarly, Figure 5 illustrates a condition of a large 5.3V dropout, PV IN = 6.0V and V OUT = 0.7V. In this case, clamping occurs at 753mA.

Figure 3. Statistic analysis of threshold current I TH

IV. EXPERIMENTAL RESULTS

As part of a power-management chip, the proposed current limiter as part of an LDO was integrated in accordance with a high-voltage fabrication process oriented to power devices.

Figure 6 displays some LDO waveforms referred to current clamping and flag generation for a low dropout of 250mV, with PV IN

= 1.5V and V OUT = 1.25V. I LOAD is mirrored from an external pulsed current source ramping from 0 up to 1A. As expected, the LDO remains in normal operation with its output regulated for I LOAD equals 400mA. Clamping occurs at I LOAD = 890mA, as well as assertion of FLAG, signalizing the chip control logic to turn the LDO off. Similarly, Figure 7 shows waveforms for a large dropout of 5.3V, with PV IN = 6.0V and V OUT = 0.7V, as current is limited to 737mA. Experimental clamping values were in very close agreement with simulation data.

Figure 4. LDO simulated waveforms (low-dropout)

M

V V

I R

I R V I R k

TH TH SNS SNS SNS

SNS TH SNS SNS 1

11

Figure 5. LDO simulated waveforms (large-dropout)

Experimental data collected from a large number of parts revealed that I TH has fallen into the interval predicted by simulation. Excellent performance of the current limiter was also observed on faulty conditions such as short-circuit between the LDO output voltage and ground terminal, with no meaningful variation on I CLP values.

V.

CONCLUSION

A sense-resistor current limiter for LDO regulators with internal first-order compensation against process and temperature variations with respect to the value of the clamping current I CLP is presented. Such compensation is based on generating a reference current I REF to the arbitration circuit according to similar current-voltage and voltage-current conversion circuits that process the current I SNS sensed from the LDO pass transistor. Furthermore, a p-MOSFET depletion device is used in the current sensor to comply with very low drop-out voltages. Such a device is commonly available in high-voltage fabrication processes, so that the proposed current limiter is a feasible alternative for the design of LDO regulators in many power management chips.

For a nominal value of 750mA, simulation data reveal minimum and maximum I CLP of 570mA and 930mA, respectively, taking into account process and external components tolerances, ±10%-variation on arbitration circuit bias current and temperature interval of -40o C to 150o C. The current limiter functionality is attested by simulated and experimental results for both conditions of low and large dropouts.

Since I CLP features relatively small deviations with process and temperature, trimming of current limitation is not required, making the proposed current limiter attractive

for low-cost power-management chips.

Figure 6. Current limitation waveforms for low dropout

Figure 7. Current limitation waveforms for large dropout

VI.REFERENCES

[1] Mammano, B. – “Current Sensing Solutions for Power Supply Designers”, Unitrode Seminars SEM1200, 1999. [2] Forghani-Zadeh, H. P. and Rincón-Mora, G. A. – “Current-Sensing Techniques for DC-DC Converters”, Proc. of IEEE MWSCAS, pp. 577 – 580, Vol.2, Aug. 2002. [3] Ohme, B. and Larson, M. – “Control Circuit Design for High Temperature Linear Regulators”, Proc. of High Temperature Electronics Conference, pp. 45 – 50, 1998. [4] Kudoh, M., Hoshi, Y., Momota, S., Fujihira, T. and Sakurai, K. – “Current Sensing IGBT for Future Intelligent Power Module”, Proc. of Power Semiconductor Devices and ICs, pp. 303-306, 1996.

[5] Leung, C., Mok, P. and Leung, K. – “A 1.2-V Buck Converter with a Novel On-Chip Low-Voltage Current-Sensing Scheme”, Proc. of IEEE ISCAS, Vol.5, pp.824-827, 2004.

2241

LDO与PWM设计资料整理

1.定义： LDO：LOW DROPOUT VOLTAGE，低压差线性稳压器，仅能在降压中应用。输出电压必需小于输入电压。 PWM：脉冲宽度调制(PWM)，是英文“Pulse Width Modulation”的缩写，是一种模拟控制方式，其根据相应载荷的变化来调制晶体管栅极或基极的偏置，来实现开关稳压电源输出晶体管或晶体管导通时间的改变，这种方式能使电源的输出电压在工作条件变化时保持恒定，是利用微处理器的数字信号对模拟电路进行控制的一种非常有效的技术。 2.LDO与DC/DC优缺点 LDO: 优点：稳定性好，负载响应快。输出纹波小。 缺点：效率低，输入输出的电压差不能太大。负载不能太大，目前最大的LDO为5A（但要保证5A的输出还有很多的限制条件）。 PWM开关电源: 优点：输入电压范围较宽, 高效率，高输出电流，低静态电流。 缺点：负载响应比LDO差，输出纹波比LDO大,成本相对较高。 3.工作原理 LDO:右图为串联线性电源的主要组成部分,其电压调整单元采 用有源器件并串联在输入电源和负载之间,负反馈环路决定调整 单元的导通程度,以维持输出电压稳定。 负反馈环路的核心是一个高增益的运算放大器,称作电压误差放 大器,用它来对输出电压和稳定的基准电压之间作比较,当有误 差存在时,电压误差放大器的增益将误差电压放大很多倍,放大后的误差电压直接控制串联调整单元的导通电阻,从而维持额定的输出电压。电压误差放大器对输出变化的响应速度和输出电压的控制精度取决于误差放大器的反馈环补偿设计。负反馈补偿的大小由分压电阻和接到电压误差放大器负输入端与输出端之间的电阻大小决定。 DC/DC开关电源：开关电源采用功率半导体器件作为开关元件,通过周期性通 断开关,控制开关元件的占空比来调整输出电压。如右图所示,其中DC/DC变 换器进行功率变换,是开关电源的核心部分,反馈回路检测其输出电压,并与 基准电压比较,其误差电压通过误差放大器放大及控制脉宽调制电路,再经 过驱动电路控制半导体开关的通断时间比,从而调整输出电压的大小。 PWM：脉宽调制(PWM)变换器就是重复通断开关,把直流电压变换为高频方波 电压,再经整流平滑变为直流电压输出,PWM变换器由半导体开关、整流二极管、 平滑滤波电抗器与电容器等基本元器件所组成输入输出间需要进行电气隔离 时,可以采用变压器,把高频方波电压通过变压器传送到输出端。 基本的Boost变换器电路结构:相对Buck变换器,仅L、SW、D的位置 做了变换。 （1）开关导通时,电流环仅包括电感、开关管和输入电压源。二极管 是反向阻断的。电感电流以固定斜率线性上升。能量存储在电感铁心 的磁通中。 （2）开关断开时,由于电感中电流不能突变，于是二极管立刻导通。 电感与开关相连端的电压被输出电压钳位（反激电压），其幅值是输出 电压加上二极管的正向导通压降。 基本的Buck变换器电路结构:其特点是功率管之后紧跟LC滤波器,LC滤波器的输入是经过斩波后的电压,LC滤波器的作用为平均占空比调制的脉冲电压。 （1）.开关导通时,输入电压加在LC滤波器的输入端，电感上的电流 以固定斜率线性上升。输入的能量就存储在电感铁心材料的磁通中。 （2）.开关断开时,由于电感上的电流不能突变，电感电流就通过二极 管D续流（续流二极管），实现对原先流过开关管电流的续流，同时电 感中存储的一部分能量向负载释放。续流电流环包括：二极管、电感、 负载。电流波形是一条斜率为负的斜线。当开关再次导通时，二极管迅 速判断，电流从输入电源和开关管流过。

设计LDO需要考虑的7个因素

设计LDO需要考虑的7个因素 统的稳压器显然是不适合市场，因为对于一些特定的应用，输入和输出的压差过低就无法使用，这时 LDO类的电源转换芯片才诞生了，帮助我们很好的解决了这个问题。不过在此提醒大家在设计LDO时主要应考虑以下问题。 1、压差（Uin-Uout） 压差是LDO的重要参数，它表示输入与输出之间的电位差，LDO的压差越小越好。但是当输入电压不能满足“ 压差”的要求时，LDO就无法正常工作。此时误差放大器会进入完全导通状态，使环路的增益变为零，对负载的稳压能力会变得很差，电源抑制比也大幅度降低。 需要注意以下几点： :在LDO的参数表中可以有多个甚至多组压差数据，例如在轻载、中等负载、满载条件下压差的 值、典型值和 值。其中，典型值仅供设计时参考。 有实际意义的应是满载条件下压差的 值，该参数值是在 不利的情况下测得的。设计时应以此为依据，以便留出足够的余量，确保LDO在 坏的情况下也能正常工作。 第二:为可靠起见，有时可按Uin=Uout+△U+lV的关系式来选择 输入电压值。功率按1.5倍以上选择有点浪费（但加上20%-30%的余量一点不为过）。一般LDO的自损功耗为Pd_max=（Uin-Uout） *Iout。 第三:输入一输出压差并非固定值，它随输出电流的增加而增大，随温度升高而增加。 2、 输出电流 输出电流是LDO的一个基本参数。通常，输出电流越大，LDO的价格越高。LDO必须能在 不利的工作条件下给负载提供足够的电流。 3、输入电压 要求输入电压必须大于额定输出电压与输入一输出压差之和，即Uin>Uout+△U。否则LDO将失去稳压功能，输出电压会随输入电压

ldo的设计

第1章绪论 1.1低压差稳压电源在现实生活中的应用 低压差稳压器(LDO)能够在很宽的负载电流和输入电压范围内保持规定的输出电压，而且输入和输出电压之差可以很小。这个电压差被称为压降或裕量要求，在负载电流为2A时可以低至80mV。现在，便携设备需要使用的低压差线性稳压器经常多达20个。最新便携设备中的许多LDO被集成进了多功能电源管理芯片2(PMIC)——这是高度集成的系统，拥有20个或以上的电源域，分别用于音频、电池充电、设备管理、照明、通信和其它功能。 然而，随着便携系统的快速发展，集成式PMIC已经无法满足外设电源要求。在系统开发的后期阶段必须增加专用LDO来给各种选件供电，如相机模块、蓝牙、WiFi和其它连接模块。LDO还能用来辅助降低噪声，解决由电磁干扰(EMI)和印刷电路板(PCB)布线造成的稳压问题，并通过关闭不需要的功能来提高系统效率。 1.2低压差稳压电源的发展现状 LDO发展概况中国集成电（IC)产业经过40余年的发展，已经形成了一个良好的产业基础，并已经进入了一个加速发展的新阶段。借鉴国外先进技术，充分利用国内优惠政策，是当前国内各个IC公司发展的立足点。作为被广泛应用于手机、DVD、数码相机以及Mp3等多种消费类电子产品中的稳压芯片，LDO已引起人们的高度重视。国内早期从事LDO生产的圣邦微电子有限公司生产的SG2001、SG2002及SG2003系列LDO，足以满足当前市场上主流电压、电流的需要；它的SG2004、SG2011以及SG2012系列产品，非常适合于大电流负载应用；而它的SGM2007/2006/2005系列RF LDO更适用于手机电源的应用。尽管是国产芯片，但这些芯片的性能丝毫不逊色于国外同类产品，而价格更适合于当前国内市场。由此看来，国内与国外IC发展的将不会越来越大，每个国人都可以相信，中国不仅可以成为IC产业的新兴地区，更能成为世界IC强国。 1.3低压差稳压电源的发展趋势 目前，低压差线性稳压器正进入一个蓬勃发展的新时期。主要表现为新技术不断涌现，新工艺被普遍采用，新产品层出不穷，其应用领域也日益广泛。低压差线性稳压器的发展趋势： 一、广泛采用新技术，不断开发新产品 目前新型VLDO的调整管大多采用CMOS工艺制成的P沟道MOS场效应管（PMOS),也有的采用N沟道MOS场效应管(NMOS)。其中，NMOS功率场

一种高速高稳定性片上LDO设计

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有关LDO在手机设计中的应用 随着社会的进步，使用者对通讯便利性要求越来越高，使得手机行业在近几年有了飞速的发展。从模拟到数字，从黑白屏到彩屏，从简单的通话功能到网上冲浪、可视对讲、移动电视、GPS定位，新的应用层出不穷。但随着手机系统功能越来越复杂，对供电系统的稳定性、供电电压、效率和成本的要求也越来越高。相应的系统供应商，例如MTK、TI、INFINION、NXP等等也随之更新自己的系统电源管理单元(PMU)，但是，作为系统级芯片的更新，远远慢于产品功能的更新换代。对于一些关键的器件，例如射频模块的供电电源，GPS模块的PLL 供电电源，对于输出纹波，PSRR(电源纹波抑制比)性能的要求很高，这些指标会直接影响手机的信号接收灵敏度以及GPS的信号接收灵敏度。利用PMU供电则会给工程师增加系统设计复杂度。因此，各种LDO在手机中的应用，始终充满 活力。 LDO是利用较低的工作压差，通过负反馈调整输出电压使之保持不变的稳压器件。根据制成工艺的不同，LDO有Bipolar，BiCMOS，CMOS几种类型，性能有所差异，但随着成本压力的增大，CMOS LDO目前成为市场的主流。 LDO从结构上来讲是一个微型的片上反馈系统，它由电压电流调整的的功率MOSFET、肖特基二极管、取样电阻、分压电阻、过流保护、过热保护、精密基准源、放大器、和PG(Power GOOD)等功能电路在一个芯片上集成而成，图1为 CMOS LDO的典型功能图。 对于手机来说，主要分成射频，基带，PMU三大功0能单元。PMU虽然可以满足其中大部分供电的需求，而对于射频部分的供电，摄像头模组的供电，GPS，以及WIFI部分新增的供电需求，由于PMU本身更新的速度，以及考虑成本、散热问题，并不能满足，需要通过额外的电源供应。SGMICRO 的LDO产品本身有着极低的静态电流，极低的噪声，非常高的PSRR，以及很低的Dropout Voltage(输入输出电压差)，可以大部分满足在这些应用条件下的供电要求。 在手机应用中，LDO的PSRR、输出噪声、启动时间这几个参数直接影响手机性能的好坏，需要根据实际应用情况选择合适参数以及考虑布线。在选择外围器件 1. 输出电容的选择影响了LDO的稳定性,瞬态响应性能,以及输出噪声Vrms的 这股气势并没有太大的攻击力，却可以形成很强大的压迫，就像现在的方云，道心圆满，使得方云的神识强大的足以媲美神阶，调动的天地之气，也是异常强 4 防止电流倒灌，静态电流的大小 5. 线路设计要考虑抑制输入电压过冲(稳压管的选用与否) 6. 布线影响散热的效率(Tdie<100℃) 7. 根据系统要求选择合适启动时间

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LDO在手机设计中的应用

LDO在手机设计中的应用 随着社会的进步，使用者对通讯便利性要求越来越高，使得手机行业在近几年有了飞速的发展。从模拟到数字，从黑白屏到彩屏，从简单的通话功能到网上冲浪、可视对讲、移动电视、GPS定位，新的应用层出不穷。但随着手机系统功能越来越复杂，对供电系统的稳定性、供电电压、效率和成本的要求也越来越高。相应的系统供应商，例如MTK、TI、INFINION、NXP 等等也随之更新自己的系统电源管理单元(PMU)，但是，作为系统级芯片的更新，远远慢于产品功能的更新换代。对于一些关键的器件，例如射频模块的供电电源，GPS模块的PLL供电电源，对于输出纹波，PSRR(电源纹波抑制比)性能的要求很高，这些指标会直接影响手机的信号接收灵敏度以及GPS的信号接收灵敏度。利用PMU供电则会给工程师增加系统设计复杂度。因此，各种LDO在手机中的应用，始终充满活力。LDO是利用较低的工作压差，通过负反馈调整输出电压使之保持不变的稳压器件。根据制成工艺的不同，LDO有Bipolar，BiCMOS，CMOS几种类型，性能有所差异，但随着成本压力的增大，CMOS LDO目前成为市场的主流。LDO 从结构上来讲是一个微型的片上反馈系统，它由电压电流调整的的功率MOSFET、肖特基二极管、取样电阻、分压电阻、过流保护、过热保护、精密基准源、放大器、和PG(Power GOOD)等功能电路在一个芯片上集成而成，图1为CMOS LDO的典型功能图。对于手机来说，主要分成射频，基带，PMU三大功能单元。PMU虽然可以满足其中大部分供电的需求，而对于射频部分的供电，摄像头模组的供电，GPS，以及WIFI部分新增的供电需求，由于PMU本身更新的速度，以及考虑成本、散热问题，并不能满足，需要通过额外的电源供应。SGMICRO的LDO 产品本身有着极低的静态电流，极低的噪声，非常高的PSRR，以及很低的Dropout Voltage(输入输出电压差)，可以大部分满足在这些应用条件下的供电要求。在手机应用中，LDO的PSRR、输出噪声、启动时间这几个参数直接影响手机性能的好坏，需要根据实际应用情况选择合适参数以及考虑布线。在选择外围器件方面，则要注意以下七点：1. 输出电容的选择影响了LDO的稳定性,瞬态响应性能,以及输出噪声Vrms的大小2. 输入电容的选择影响瞬态响应性能, EMI和PSRR3. 滤波电容影响了输出纹波、PSRR和瞬态响应性能及启动时间4 防止电流倒灌，静态电流的大小5. 线路设计要考虑抑制输入电压过冲(稳压管的选用与否)6. 布线影响散热的效率(Tdie<100℃)7. 根据系统要求选择合适启动时间图1：CMOS LDO的基本架构及简单应用线路图LDO的以下几个参数在手机设计中特别重要：LDO的稳定性与瞬态响应。由于负载电流动态变化大，要求LDO的稳定性与瞬态响应性能好，否则导致系统工作异常。PSRR参数。PSRR参数直接影响射频模块部分地接收灵敏度。如果用在音频部分，能够抑制手机中的EMI干扰，使声音的表现力更好。LDO的输出噪声。这直接关系到输出电源的干净与否。LDO的启动时间。启动时间跟系统设计的上电时序息息相关，直接影响系统的工作与否。LDO 推荐的PCB设计。在设计过程中，需要将输入电容Cin与输出电容Cout尽量靠近LDO。在LDO的应用中，热设计往往是一个容易忽视的地方，需要考虑不同功率情况下选用合适的封装，常见的有三种，SC70、SOT23和DFN-6。以射频模块部分供电为例，SC70封装，本身允许散热功率通常在0.2W以内：PD=(Vin-Vout)*Iout+Vin*Ignd <0.2WVin=Vbattery=3.6V 以上，Vout通常是2.8V，如果电流超过250mA会导致不稳定,而SOT23的封装允许散热在0.4W 左右，更加适合该部分的应用。如果从芯片尺寸考虑，可以选用DFN封装，可以兼顾散热要求(PD>0.4W)。SG MICRO(圣邦微电子)作为新兴的半导体供应商，也推出了一系列的LDO 产品：通用LDO(三端稳压),射频LDO（PSRR可以达到73DB@1kHZ）,高精度LDO(满负载0~300mA，全温度范围-40~125℃，精度1.6%)。以射频LDO SGM2007为例，输出噪声为30μVrms，输出压差为300mV(全温度范围，全负载0-300mA)，静态功耗低至77μA，关断电流小于10nA，PSRR在1kHz时为73db，216.67Hz为78dB。LDO SGM2007具有过热保护和过流保护功能，启动时间在20μS以内。

设计LDO不得不考虑的因素集锦

设计LDO不得不考虑的因素集锦 传统的稳压器显然是不适合市场，因为对于一些特定的应用，输入和输出的压差过低就无法使用，这时LDO类的电源转换芯片才诞生了，帮助我们很好的解决了这个问题。不过在此潘登提醒大家在设计LDO时主要应考虑以下问题。 1、压差（Uin-Uout） 压差是LDO的重要参数，它表示输入与输出之间的电位差，LDO的压差越小越好。但是当输入电压不能满足“最小压差”的要求时，LDO就无法正常工作。此时误差放大器会进入完全导通状态，使环路的增益变为零，对负载的稳压能力会变得很差，电源抑制比也大幅度降低。 需要注意以下几点： 第一，在LDO的参数表中可以有多个甚至多组压差数据，例如在轻载、中等负载、满载条件下压差的最小值、典型值和最大值。其中，典型值仅供设计时参考。最具有实际意义的应是满载条件下压差的最大值，该参数值是在最不利的情况下测得的。设计时应以此为依据，以便留出足够的余量，确保LDO在最坏的情况下也能正常工作。 第二，为可靠起见，有时可按Uin=Uout+△U+lV的关系式来选择最低输入电压值。功率按1.5倍以上选择有点浪费（但加上加上20%-30%的余量一点不为过）。一般LDO的自损功耗为Pd_max=（Uin-Uout）*Iout。 第三，输入一输出压差并非固定值，它随输出电流的增加而增大，随温度升高而增加。 2、最大输出电流（） 最大输出电流是LDO的一个基本参数。通常，输出电流越大，LDO的价格越高。LDO 必须能在最不利的工作条件下给负载提供足够的电流。 3、输入电压 要求输入电压必须大于额定输出电压与输入一输出压差之和，即Uin>Uout+△U。否则LDO将失去稳压功能，输出电压会随输入电压而改变，此时Uout就等于输入电压减去调整管导通电阻(RON)与负载电流的乘积，即Uout=Uin-RONI0。 4、输出电压 固定输出式LDO的外围电路简单，使用方便，并且能节省外部取样电阻分压器的成本和空间。其输出电压值在出厂时已趋于一致(仅限于通用电压)，输出电压精度一般为±5％，这对于大多数应用已经足够了。新型LDO采用激光修正技术，精度指标可达±1％～±2％。特别需要注意产品说明书所给出精度指标的适用条件，例如是在室温下还是在整个工作温度范围内，是满载条件下还是在中等负载或空载条件下。 可调输出式LDO允许在规定范围内连续调节输出电压。若将输出端与反馈端相连，使输出电压等于内部基准电压，则最低输出电压一般为1．2V左右。