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HD74HC299RPEL中文资料

HD74HC299RPEL中文资料
HD74HC299RPEL中文资料

HD74HC299

8-bit Universal Shift/Storage Register (with 3-state outputs)

REJ03D0609–0200

(Previous ADE-205-488)

Rev.2.00

Jan 31, 2006 Description

The HD74HC299 features multiplexed inputs/outputs to achieve full 8-bit data handling in a single 20-pin package. Due to the large output drive capability and 3-state feature, this device is ideally suited for interfacing with bus lines in a bus oriented system. Two function select inputs and two output control inputs are used to choose the mode of operation as listed in the function table. Synchronous parallel loading is accomplished by taking both function select lines S0 and S1 high. This places the 3-state outputs in a high impedance state, which permits data applied to the

input/output lines to be clocked into the register. Reading out of the register can be done while the outputs are enabled in any mode. A direct overriding clear input is provided to clear the register whether the outputs are enabled or disabled.

Features

? High Speed Operation

? High Output Current: Fanout of 15 LSTTL Loads

? Wide Operating Voltage: V CC = 2 to 6 V

? Low Input Current: 1 μA max

? Low Quiescent Supply Current: I CC (static) = 4 μA max (Ta = 25°C)

? Ordering Information

Part Name Package Type

Package Code

(Previous Code)

Package

Abbreviation

Taping Abbreviation

(Quantity)

HD74HC299FPEL SOP-20 pin (JEITA) PRSP0020DD-B

(FP-20DAV)

FP EL (2,000 pcs/reel)

HD74HC299RPEL SOP-20 pin (JEDEC) PRSP0020DC-A

(FP-20DBV)

RP EL (1,000 pcs/reel)

Note: Please consult the sales office for the above package availability.

Function Table

flop outputs are isolated from the input/output terminals. 2. Q A0 to Q H0; the level of Q A through Q H , respectively, before the indicated steady-state input conditions were

established.

3. Q An to Q Hn ; the level of Q A through Q H , respectively, before the most-recent transition of the clock.

4. ? ; When one or both output controls are high the eight input/output terminals are disabled to the high-

impedance state, however, sequential operation or clearing of the register is not affected.

5. When clear is low, outputs of Q A ’ and Q H ’ are low, in spite of other inputs.

Pin Arrangement

20 19 18 17 16 15 14 13 12 1

2

3 4 5 6 7 8 9

S 0 G 1 G 2 G/Q C E/Q E C/Q C A/Q A Q A Clear

V CC S 1

Q H H/Q H F/Q F D/Q D B/Q B Clock Output controls

Shift left SL SR

S 0

S 1Q H H/Q H D/Q D B/Q B F/Q F SL

CK

G

G/Q G E/Q E A/Q A Q A C/Q C Clear

Logic Diagram

G/Q G F/Q F E/Q E D/Q D C/Q C B/Q B A/Q A Q Q/A

Absolute Maximum Ratings

Item Symbol Ratings Unit

Supply voltage range V CC –0.5 to 7.0 V Input / Output voltage V IN , V OUT –0.5 to V CC +0.5 V Input / Output diode current I IK , I OK ±20 mA Output current I O ±35 mA V CC , GND current I CC or I GND ±75 mA Power dissipation P T 500 mW Storage temperature Tstg –65 to +150 °C Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of

which may be realized at the same time.

Recommended Operating Conditions

Item Symbol Ratings Unit Conditions

Supply voltage V CC 2 to 6 V Input / Output voltage V IN , V OUT 0 to V CC V Operating temperature Ta –40 to 85 °C 0 to 1000 V CC = 2.0 V

0 to 500 V CC = 4.5 V Input rise / fall time *1 t r , t f 0 to 400 ns V CC = 6.0 V Notes: 1. This item guarantees maximum limit when one input switches.

Waveform: Refer to test circuit of switching characteristics.

Ta = 25°C Ta = –40 to+85°C

Item Symbol V CC (V)

Min Typ Max Min Max

Unit Test Conditions

2.0 1.5 — — 1.5 — 4.5

3.15 — — 3.15 — V IH 6.0

4.2 — — 4.2 —

V

2.0 — — 0.5 — 0.5 4.5 — — 1.35 — 1.35 Input voltage

V IL 6.0 — — 1.8 — 1.8

V

2.0 1.9 2.0 — 1.9 — 4.5 4.4 4.5 — 4.4 — 6.0 5.9 6.0 — 5.9 — Vin = V IH or V IL I OH = –20 μA

4.5 4.18 — — 4.13 — I OH = –4 mA 6.0

5.68 — — 5.63 — Q A ’ & Q H ’

Outputs I OH = –5.2 mA

4.5 4.18 — — 4.13 — I OH = –6 mA V OH 6.0

5.68 — — 5.63 —

V A/Q A thru

H/Q H Outputs I OH = –7.8 mA 2.0 — 0.0 0.1 — 0.1 4.5 — 0.0 0.1 — 0.1 6.0 — 0.0 0.1 — 0.1 Vin = V IH or V IL I OL = 20 μA 4.5 — — 0.26 — 0.33 I OH = 4 mA 6.0 — — 0.26 — 0.33 Q A ’ & Q H ’

Outputs I OH = 5.2 mA

4.5 — — 0.26 — 0.33 I OH = 6 mA Output voltage

V OL

6.0 — — 0.26 — 0.33

V A/Q A thru

H/Q H Outputs I OH = 7.8 mA Off-state output

current

I OZ 6.0

— — ±0.5 — ±5.0 μA Vin = V IH or V IL , Vout = V CC or GND

Input current

Iin 6.0 — — ±0.1 — ±1.0 μA Vin = V CC or GND

Quiescent supply current I CC 6.0

— — 4.0 — 40 μA Vin = V CC or GND, Iout = 0 μA

(C L = 50 pF, Input t r = t f = 6 ns)

Ta = 25°C Ta = –40 to +85°C

Item Symbol V CC (V)

Min Typ Max Min Max

Unit Test Conditions

2.0 — — 5 — 4 4.5 — — 25 — 20 Maximum clock

frequency f max

6.0 — — 29 — 23 MHz 2.0 — — 190 — 240 4.5 — — 38 — 48 t PLH t PHL 6.0 — — 32 — 41 ns Clock to Q A ’ or Q H ’ 2.0 — — 220 — 275 4.5 — — 44 — 55 t PHL

6.0 — — 37 — 47 ns Clear to Q A ’ or Q H ’ 2.0 — — 190 — 240 4.5 — — 38 — 48 t PLH t PHL 6.0 — — 32 — 41 ns Clock to Q A – Q H 2.0 — — 220 — 275 4.5 — — 44 — 55 Propagation delay time

t PHL

6.0 — — 37 — 47 ns Clear to Q A – Q H 2.0 — — 160 — 200 4.5 — — 32 — 40 Output enable time

t ZH t ZL 6.0 — — 27 — 34

ns 2.0 — — 160 — 200 4.5 — — 32 — 40 Output disable time t HZ t LZ 6.0 — — 27 — 34

ns 2.0 100 — — 125 — 4.5 20 — — 25 — Setup time

t su

6.0 17 — — 21 —

ns Select 2.0 5 — — 5 — 4.5 5 — — 5 — Hold time t h

6.0 5 — — 5 —

ns Select 2.0 50 — — 65 — 4.5 10 — — 13 — Removal time t rem

6.0 9 — — 11 —

ns Clear 2.0 80 — — 100 — 4.5 16 — — 20 — Pulse width t w

6.0 14 — — 17 —

ns 2.0 — — 60 — 75 4.5 — — 12 — 15 6.0 — — 10 — 13

ns A/Q A thru H/Q H outputs 2.0 — — 75 — 95 4.5 — — 15 — 19 Output rise/fall time

t TLH t THL

6.0 — — 13 — 16 ns Q A ’ & Q H ’ outputs Input capacitance Cin

5

10

10

pF

Test Circuit

Waveforms

50 %

Waveform – 1

50 %

t rem

50 %

50 %

50 %

50 %

90 %t r

10 %

t f

90 %t su

t su

t h 50 %

50 %

Note : 1. Input pulse : PRR ≤ 1 MHz, Zo = 50 ?, t r ≤ 6 ns, t f ≤ 6 ns

A to H enabled

Q A to Q H disabled A to H disabled

Q A to Q H enabled

A to H enabled Q A to Q H disabled

A to H disabled Q A to Q

50 %90 %

10 %

t ZL

t LZ

t ZH

t HZ

Waveform - A

50 %

tf 10 %

90 %50 %

tr 10 %

90 %Waveform – 3

Package Dimensions

10

*3

p

M

x

y

b A

1

1

Detail F

L

L A θ

FP-20DBV

RENESAS Code Previous Code 0.52g

MASS[Typ.]PRSP0020DC-A

11

F

*1

*2

E

Index mark

E

H D

p

c

b NOTE)

1. DIMENSIONS"*1 (Nom)"AND"*2"@ DO NOT INCLUDE MOLD FLASH.

2. DIMENSION"*3"DOES NOT @ INCLUDE TRIM OFFSET.

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