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dw1000数据手册_引脚图_参数

dw1000数据手册_引脚图_参数
dw1000数据手册_引脚图_参数

DW1000

IEEE802.15.4-2011UWBTransceiver

D I G I T A L T R A N S C

E I V E R

Product Overview

The DW1000 is a fully integrated single chip Ultra Wideband (UWB) low-power low-cost transceiver IC compliant to IEEE802.15.4-2011. It can be used in 2-way ranging or TDOA location systems to locate

assets to a precision of 10 cm. It also supports data transfer at rates up to 6.8 Mbps

Key Features Key Benefits

? IEEE802.15.4-2011 UWB ? Supports precision location and

compliant data transfer concurrently ? Supports 6 RF bands from ? Asset location to a precision of

3.5 GHz to 6.5 GHz 10 cm

? Programmable transmitter ? Extended communications

output power range up to 290 m @ 110 kbps ? Fully coherent receiver for 10% PER minimises required

maximum range and accuracy infrastructure in RTLS

? Complies with FCC & ETSI ? High multipath fading immunity

UWB spectral masks ? Supports high tag densities in ? Supply voltage 2.8 V to 3.6 V RTLS

? Low power consumption ? Small PCB footprint allows cost- ? SLEEP mode current 1 μA effective hardware ? DEEP SLEEP mode current 50 implementations

nA ? Long battery life minimises ? Data rates of 110 kbps, 850 system lifetime cost

kbps, 6.8 Mbps

? Maximum packet length of Applications

1023 bytes for high data

throughput applications ? Precision real time location

? Integrated MAC support systems (RTLS) using two-way

features ranging or TDOA schemes in a ? Supports 2-way ranging and variety of markets: -

TDOA o Healthcare ? SPI interface to host processor o Consumer ? 6 mm x 6 mm 48-pin QFN o Industrial

package with 0.4 mm lead pitch o Other

? Small number of external ? Location aware wireless sensor

components networks

ANALOG RECEIVER POWER MANAGEMENT

PLL / CLOCK GENERATOR HOST INTERFACE / SPI TO

HOST

ANALOG TRANSMITTER STATE CONTROLLER

State Ready Immediate 5 μs State Ready

Immediate

5 μs

6 O PERATIONAL S TATES A ND P OWER M ANAGEMENT

6.1 Overview

The DW1000 has a number of basic operating states as follows: -

Table 23: Operating States

For more information on operating states please refer to the user manual [2].

6.2 Operating States and their effect on power consumption

The DW1000 can be configured to return to any one of the states, IDLE, INIT, SLEEP or DEEPSLEEP between

active transmit and receive states. This choice has implications for overall system power consumption and timing, see table below.

Table 24: Operating States and their effect on power consumption

DEVICE STATE

IDLE

INIT SLEEP DEEPSLEEP OFF Host controller Host controller Host controller Entry to State

command or previous operation Host controller command command or previous operation command or previous operation External supplies are off completion completion completion Exit from State Host controller command

Host controller command

Sleep counter timeout

SPICSn held low Or WAKEUP held high for 500 μs

External 3.3 V supply on

Next state Various

IDLE

INIT

INIT

INIT

Current Consumption 18 mA (No DC/DC)

12 mA (with DC/DC) 4 mA

1 μA 50 nA 0 Configuration Maintained Maintained Maintained

Maintained

Not maintained

Time before RX

Time before TX 3 ms 3 ms 3 ms

3 ms 3 ms 3 ms

In the SLEEP, DEEPSLEEP and OFF states, it is necessary to wait for the main on-board crystal oscillator to power up and stabilize before the DW1000 can be used. This introduces a delay of up to 3 ms each time the DW1000 exits SLEEP , DEEPSLEEP and OFF states.

Name

Description OFF The chip is powered down

INIT This is the lowest power state that allows external micro-controller access. In this state the DW1000 host interface clock is running off the 38.4 MHz reference clock. In this mode the SPICLK frequency can be no greater than 3 MHz.

IDLE In this state the internal clock generator is running and ready for use. The analog receiver and transmitter are powered down. Full speed SPI accesses may be used in this state.

DEEPSLEEP This is the lowest power state apart from the OFF state. In this state SPI communication is not

possible. This state

requires an external pin to be driven (can be SPICSn held low or WAKEUP held high) for a minimum of 500 μs to indicate a wake up condition. Once the device has

detected the wake up condition, the EXTON pin will be asserted and internal reference oscillator (38.4 MHz) is enabled. SLEEP In this state the DW1000 will wake up after a programmed sleep count. The low power oscillator is running and the internal sleep counter is active. The sleep counter allows for

periods from approximately 300 ms to 450 hours before the DW1000 wakes up. RX The DW1000 is actively looking for preamble or receiving a packet RX PREAMBLE SNIFF In this state the DW1000 periodically enters the RX state, searches for preamble and if no

preamble is found returns to the IDLE state. If preamble is detected it will stay in the RX state

and demodulate the packet. Can be used to lower overall power consumption. TX The DW1000 is actively transmitting a packet

6.3Transmit and Receive power profiles

1.POWER OFF BETWEEN OPERATIONS Configuration lost Device ready for operation

OSC/PLL

STARTUP TX/RX OPERATION OFF Idd=0

OSC/PLL

STARTUP TX/RX OPERATION OFF Idd=0 5ms approx/

2.DEEP SLEEP BETWEEN OPERATIONS Configuration retained 1mA Device ready for

operation

OSC/PLL

STARTUP TX/RX OPERATION DEEPSLEEP Idd=

100nA

OSC/PLL

STARTUP TX/RX OPERATION DEEPSLEEP Idd = 100 nA

5ms approx/

1mA

3.SLEEP BETWEEN OPERATIONS Configuration retained Device ready for operation

OSC/PLL

STARTUP TX/RX OPERATION SLEEP Idd=2μA

OSC/PLL

STARTUP TX/RX OPERATION SLEEP Idd=2μA

5ms approx/

1mA

4.INIT STATE BETWEEN OPERATIONS Configuration retained Device ready for operation

OSC/PLL

STARTUP TX/RX OPERATION INIT Idd=4mA

PLL

LOCK TX/RX OPERATION INIT Idd=4mA 5μs approx/5mA

Figure30:Sleep options between operations

The tables below show typical configurations of the DW1000and their associated power profiles.

Table25:Operational Modes

Mode Data Rate

PRF

(MHz)

Preamble

(Symbols)

Data

Length

(Bytes)

Packet

Duration

(μs)

Typical Use Case

(Refer to DW1000user manual for further information)

Mode1110kbps161024122084RTLS,TDOA Scheme,Long Range,Low

Density

Mode2 6.8Mbps1612812152RTLS,TDOA Scheme,Short Range,High

Density

Mode3110kbps161024303487RTLS,2-way ranging scheme,Long Range,

Low Density

Mode4 6.8Mbps1612830173RTLS,2-way ranging scheme,Short Range,

High Density

Mode5 6.8Mbps16102410231339Data transfer,Short Range,Long Payload Mode6 6.8Mbps16128127287Data transfer,Short Range,Short Payload Mode7110kbps161024102378099Data transfer,Long Range,Long Payload Mode8110kbps16102412710730Data transfer,Long Range,Short Payload Mode9110kbps641024122084As Mode1using64MHz PRF

Mode10 6.8Mbps6412812152As Mode2using64MHz PRF

Mode11110kbps641024303487As Mode3using64MHz PRF

Mode12 6.8Mbps6412830173As Mode4using64MHz PRF

Mode13 6.8Mbps64102410231339As Mode5using64MHz PRF

Mode14 6.8Mbps64128127287As Mode6using64MHz PRF

Mode15110kbps641024102378099As Mode7using64MHz PRF

Mode16110kbps64102412710730As Mode8using64MHz PRF

Note:Other modes are possible

Table 26: Typical TX Current Consumption

Table 27: Typical RX Current Consumption

T amb = 25 ?C, All supplies centered on typical values. All currents referenced to 3.3 V (VDDLDOA, VDDLDOD supplies fed via a 1.6 V 90% efficient DC/DC converter)

From Table 25, Table 26 and T able 27 above it is clear that there is a trade-off between communications range and power consumption. Lower data rates allow longer range communication but consume more power. Higher data rates consume less power but have a reduced communications range.

For a given payload length, the following table shows two configurations of the DW1000. The first achieves minimum power consumption (not including DEEPSLEEP , SLEEP , INIT & IDLE) and the second achieves longest communication range.

Mode Name

RX I AVG (mA)

Units

Channel 2 Channel 5

Avg Preamble

Data Demod

Avg

Preamble

Data Demod

Mode 1 86113 59 92 118 62 mA Mode 2 115 113 118 122 118 123 mA Mode 3 76 113 59 81 118 62 mA Mode 4 115 113 115 123 118 123 mA Mode 5 118 113 118 126 118 126 mA Mode 6 113 113 113 125 118 126 mA Mode 7 57113 59 65 118 62 mA Mode 8 62113 59 70 118 62 mA Mode 9 90 113 72 94 118 75 mA Mode 10 112 113 118 117 118 123 mA Mode 11 82 113 72 85 118 75 mA Mode 12 112 113 118 118 118 123 mA Mode 13 114 113 118 120 118 123 mA Mode 14 113 113 118 119 118 123 mA Mode 15 72113 72 76 118 75 mA Mode 16

76 113

72

80

118

75

mA

Mode Name

TX I AVG (mA)

Units

Channel 2 Channel 5

Avg Preamble

Data

Avg

Preamble

Data

Mode 1 48 68 35 56 74 42 mA Mode 2 68 68 50 69 74 57 mA Mode 3 44 68 35 50 74 42 mA Mode 4 60 68 51 67 74 58 mA Mode 5 50 68 51 56 74 58 mA Mode 6 56 68 51 62 74 58 mA Mode 7 35 68 35 42 74 42 mA Mode 8 38 68 35 44 74 42 mA Mode 9 61 83 40 67 89 46 mA Mode 10 79 83 52 85 89 59 mA Mode 11 52 83 40 59 89 46 mA Mode 12 75 83 52 82 89 59 mA Mode 13 53 83 52 60 89 59 mA Mode 14 65 83 52 72 89 59 mA Mode 15 40 83 40 46 89 46 mA Mode 16

43 83

40

50

89

46

mA

Table 28: Lowest power and longest range modes of operation

The graph below shows typical range and average transmitter current consumption per frame with the transmitter running at -41.3 dBm/MHz output power and using 0 dBi gain antennas for channel 2.

90

80

70

60

250

200

TX I avg (mA)

50 40

150

100

Range (m)

30

20

10

50

Modes

Figure 31: Typical Range versus TX average current (channel 2)

T amb = 25 ?C, All supplies centered on typical values. All currents referenced to 3.3 V (VDDLDOA, VDDLDOD supplies fed via a 1.6 V 90% efficient DC/DC converter)

TX Iavg (mA) Range

Mode

Data Rate Channel

PRF (MHz) Preamble (Symbols) Data Length (Bytes)

Rx PAC (Symbols)

Notes

(Refer to DW1000 user manual

for further information)

Lowest Power

2 options based on hardware

configuration

6.8 Mbps with gating gain

1

16

64

As short as possible

8

Using “tight” gearing tables and a TCXO as the source of the 38.4 MHz clock at each node 6.8 Mbps with gating gain 16

128

Using “standard” gearing tables and an XTAL as the source of the 38.4 MHz clock at each node

Longest Range

110 Kbps

16 2048

All supported lengths

32

3.5 GHz centre frequency gives best propagation

3mA

100nA

max

6.3.1 Typical transmit profile mA 70 60 50 40

TX power profile for Mode 2 (Returning to DEEPSLEEP state) Date rate 6.8Mb/s; Channel 2; Preamble length 128 symbols; 12 byte frame.

30

20

15mA

65 mA

12 Byte Packet

48 mA

10

5 12mA

max

t

OSC STARTUP

WR TX DATA

TX SHR

TX PHR /

PSDU

DEEPSLEEP

PLL

STARTUP

7μs

~2ms

10μs

135μs

16μs

Power measured over this duration

Figure 32: Typical TX Power Profile

6.3.2 Typical receive profiles

mA

130 120 110

RX power profile for Mode 2 (Returning to DEEPSLEEP) Data rate 6.8Mb/s; Channel 2; Preamble length 128 symbols; 12 byte frame.

100

125 mA

12 Byte Frame

20

12mA

113 mA

118 mA

10

5 0

3mA

100nA

12mA

time

OSC STARTUP

PREAMBLE HUNT

RX SHR

RX PHR/PSDU

HOST RD DATA

DEEPSLEEP

PLL STARTUP

~2ms

7μs

Variable Time

120μs

16μs

56μs

Power measured over this duration

Figure 33: Typical RX Power Profile

mA 130 120 110

RX power profile for Mode 2 with Preamble SNIFF mode

Data rate 6.8Mb/s; Channel 2; Preamble length 128 symbols; 12 byte frame.

100

125 mA

12 Byte

Frame 20

12mA

113 mA

113 mA

113 mA

113 mA

113 mA

118 mA

100nA 10

5 0

3mA

12mA

Max

time

OSC STARTUP

PREAMBLE SNIFF

RX SHR

RX PHR/

PSDU

HOST RD DATA DEEPSLEEP

PLL

STARTUP

~2ms

7μs

Variable Time

120μs

16μs

56μs

Power measured over this

duration

VDDLDOA

VDDBATT

VDDLDOD

VDDAON

VDDPA2 VDDPA1

VDDLNA

VDDIOA

DW1000

VDDIF

VDDREG

VDDDIG

VDDMS

VDDVCO

VDDCLK VDDSYN VDDIO

VDDLDOA

VDDBATT

VDDLDOD

VDDAON

VDDPA1

VDDPA2 VDDLNA

VDDIOA

DW1000

VDDREG VDDIF

VDDDIG

VDDMS

VDDVCO

VDDCLK VDDSYN VDDIO

7 P OWER S UPPLY

7.1 Power Supply Connections

There are a number of different power supply connections to the DW1000.

The chip operates from a nominal 3.3 V supply. Some circuits in the chip are directly connected to the external 3.3 V supply. Other circuits are fed from a number of on-chip low-dropout regulators. The outputs of these LDO regulators are brought out to pins of the chip for decoupling purposes. Refer to Figure 35 for further details.

The majority of the supplies are used in the analog & RF section of the chip where it is important to maintain supply isolation between individual circuits to achieve the required performance.

3.3 V Supply

Internal Switches

Digital IO Ring

On-chip LDO for digital circuits

On-chip LDOs for analog circuits

All other 3V3 circuits

“Always On” Config Store

Rx LNA

Tx PA

To External Decoupling Capacitors

Figure 35: Power Supply Connections

7.2 Use of External DC / DC Converter

The DW1000 supports the use of external switching regulators to reduce overall power consumption from the power source. Using switching regulators can reduce system power consumption. The EXTON pin can be used to further reduce power by disabling the external regulator when the DW1000 is in the SLEEP or DEEPSLEEP states (provided the EXTON turn on time is sufficient).

3.3 V Supply

EXTON

EN

VIN

DC / DC

VOUT

1.8 V

Internal Switches

Digital IO Ring

On-chip LDO for digital circuits

On-chip LDOs for analog circuits

All other 3V3 circuits

“Always On” Config Store

Rx LNA

Tx PA

To External Decoupling Capacitors

Figure 36: Switching Regulator Connection

7.3Powering down the DW1000

The DW1000has a very low DEEPSLEEP current(typ.50nA–see Table3).The recommended practise is to keep the DW1000powered up and use DEEPSLEEP mode when the device is inactive.

In situations where the DW1000must be power-cycled(the3.3V supply in Figure35/Figure36respectively turned off and then back on),it is important to note that when power is removed the supply voltage will decay towards0V at a rate determined by the characteristics of the power source and the amount of decoupling capacitance in the system.

In this scenario,power should only be reapplied to the DW1000when:-

?VDDAON is above2.3V or:

?VDDAON has fallen below100mV

Reapplying power while VDDAON is between100mV and2.3V can lead to the DW1000powering up in an unknown state which can only be recovered by fully powering down the device until the voltage on VDDAON falls below100mV.

100K

V D D B A T

V D D L D O A

48 47 46 45 44 43 42 41 0.1u F

40 39 38 G P I O 0 49

V D D B A T V D D D I G I R Q S P I M I S O T E S T M O D E V D D L D O A

S P I M O S I V D D I O S P I C L K G P I O 1

V S S I O 37

10p F

10p F

11k (1%)

GND

GND

16k 27p

1p 2

0.1u F

V D D D R E G

F O R C E O N

W A K E U P

V D D L N A

270R 820p

R F _N

R F _P

S P I C S n

E X T O N

V D D P A

V D D P A

0.1u F

22 23 17 13

14 0.1u F

N C

N C

18p

V D D L N A V D D P A V D D P A 21 15 16 18 19 20 24

G N D

10000p F

330p F

330p F

0.1u F

0.1u F

0.1u F

0.1u F

0.1u F

0.1u F

0.1u F

4.7u F

47u F

10p F

10p F

8 A PPLICATION I NFORMATION

8.1 Application Circuit Diagram

Optional Use of TCXO

U3

IRQ

VDD_3V3

3V LDO

VCC OUT

optional external pull-down i f SLEEP or D EEPSLEEP modes are used

GND

GND

VDDDIG

GND

SPICLK GND

VDD_TCXO

X2

38.4 MHz TCXO

VCC

OUT

GND

XTAL1

2200pF

(paddle)

0.1uF

GND

SPIMISO SPIMOSI GPIO0 GPIO1 GND

X1

38.4 MHz

GND

1

NC

GPIO2

36

35 GPIO2

optional external pull-ups for SPI GND

GND

2 3 4 NC

XTAL1 XTAL2 GPIO3 GPIO4 GPIO5 34 33 32 GPIO3 GPIO4 GPIO5 mode configuration

0.1uF 0.1uF 5 6 7

VREF VDDMS VDDIF

DW1000

VSSIO VDDIO GPIO6 31 30 29 0.1uF

GND

GPIO6

10k

GND

GND

0.1uF 8 9 10

11

12

CLKTUNE

VDDCLK

VDDSYN VDDVCO

VCOTUNE

SYNC VDDIOA RSTn VDDLDOD VDDAON

28 27 26 25

VDDIOA

VDDLDOD

VDDAON

SYNC RSTn

Don’t D o

10k

VDD_3V3

GND

U1

This!

GND

GND

SPICSn

WAKEUP

GND

T1

12p

RF Traces 100R

EXTON Antenna

GND

RF Trace 50R

RF Traces 100R

U2

12p

VDDDIG

En

Vout

VDDLDOD

0.1 uF

1V8

GND

VDD_3V3

Vin

VDDLDOA

DC-DC Convertor

(optional)

VDD_3V3

VDDPA

VDDPA

VDDLNA

VDDBAT

VDDIOA

VDDAON

VDDLDOD

VDDLDOA

GND

Decoupling: Place capacitors close to pins

Figure 37: DW1000 Application Circuit

8.2 Recommended Components

8.3Application Circuit Layout

8.3.1PCB Stack

The following 4-layer PCB stack up is one suggested stack up which can be used to achieve optimum performance.

Figure38:PCB Layer Stack for4-layer board

8.3.2RF Traces

As with all high frequency designs,particular care should be taken with the routing and matching of the RF sections of the PCB layout.All RF traces should be kept as short as possible and where possible impedance discontinuities should be avoided.Where possible RF traces should cover component land patterns.

Poor RF matching of signals to/from the antenna will degrade system performance.A100?differential impedance should be presented to the RF_P and RF_N pins of DW1000for optimal performance.This can be realised as either100?differential RF traces or as2single-ended50?traces depending on the PCB layout.In most cases a single-ended antenna will be used and a wideband balun will be required to convert from100?differential to50?single-ended.

R F _N

R F _P

G N D

capacitors from the RF_P and RF_N pins are realised as 100 ? differential RF traces referenced to inner layer 1. After the 12 pF capacitors the traces are realized as 50 ? micro-strip traces again referenced to inner layer 1. Using this method, thin traces can be used to connect to DW1000 and then wider traces can be used to connect to the antenna.

GND

T1

12p

RF Traces 100R

Antenna

RF Trace 50R

RF Traces 100R

RF trace - 100 ? differential referenced to inner layer 1. RF trace – 50 Ω single ended referenced to inner

layer 1

12p

2 x 50 ? single-ended RF trace can also be used. Need to ensure the traces are referenced to correct ground layer

Figure 39: DW1000 RF Traces Layout

8.3.3 PLL Loop Filter Layout

The components associated with the loop filters of the on-chip PLLs should be placed as close as possible to the chip connection pins to minimize noise pick-up on these lines.

8.3.4 Decoupling Layout

All decoupling capacitors should be kept as close to their respective pins of the chip as possible to minimize trace inductance and maximize their effectiveness.

8.3.5 Layout Guidance

An application note is available from Decawave together with a set of DXF files to assist customers in reproducing the optimum layout for the DW1000.

PCB land-pattern libraries for the DW1000 are available for the most commonly used CAD packages. Contact Decawave for further information.

9P ACKAGING&O RDERING I NFORMATION

9.1Package Dimensions

Parameter Min Typ Max Units

Unit weight0.105g

Figure40:Device Package mechanical specifications

?Decawave Ltd2015Subject to change without notice Version2.10Page38

9.2Device Package Marking

The diagram below shows the package markings for DW1000.

Figure41:Device Package Markings

Legend:

W228E-1N7digit manufacturing code

LLLLLL6digit lot ID

ZZ2digit lot split number

PH Assembly location

YY2digit year number

WW2digit week number

9.3Tray Information

The general orientation of the48QFN package in the tray is as shown in Figure42.

Figure42:Tray Orientation

9.4 Tape & Reel Information

9.4.1 Important note

The following diagrams and information relate to reel shipments made from 23rd March 2015 onwards. Information relating to reels shipped prior to that date may be obtained from Decawave.

9.4.2 Tape Orientation and Dimensions

The general orientation of the 48QFN package in the tape is as shown in Figure 43.

User Direction of Feed

Figure 43: Tape & Reel orientation

K 0

B 0

T

Expanded Section ‘X - X’

Figure 44: Tape dimensions

9.4.3 Reel Information: 330 mm Reel Base material: High Impact Polystyrene with Integrated Antistatic Additive Surface resistivity: Antistatic with surface resistivity less than 1 x 10e 12 Ohms per square Dimensions

Values Notes Ao 6.3 ± 0.1 All dimensions in mm sprocket hole pitch cumulative tolerance ± 0.20

Material: Conductive Polystyrene Camber not to exceed 1.0 mm in 250 mm Bo 6.3 ± 0.1 Ko 1.1 ± 0.1 P 12.00 ± 0.1 T 0.30 ± 0.05 W 16.00 + 0.30 – 0.10

Figure 45: 330 mm reel dimensions

All dimensions and tolerances are fully compliant with EIA- 481-C and are specified in millimetres.

9.4.4 Reel Information: 180 mm reel

Base material: High impact polystyrene with integrated antistatic additive.

Surface resistivity:

Antistatic with surface resistivity less than 1 x 10e 12 Ohms per square.

Figure 46: 180 mm reel dimensions

Tape Width A Diameter B (min) C D (min) N Hub W1 W2 (max) W3 (min) W4 (max) 16 330 / 380

1.5

13 + 0.5 - 0.2

20.2

100 / 150 +/-1 mm

16.4 + 2.0 – 0.0

22.4

15.9

19.4

Tape Width

A Diameter C D (min) N Hub W1 W2 (max) 16 178 +/- 1.0 13.5 +/- 0.5 20.2 60 + 1.0 – 0.0 17 +/- 0.5 19.5

9.5Reflow profile

The DW1000should be soldered using the reflow profile specified in JEDEC J-STD-020as adapted for the particular PCB onto which the IC is being soldered.

9.6Ordering Information

The standard qualification for the DW1000is industrial temperature range:-40oC to+85oC,packaged in a48-pin QFN package.

Table29:Device ordering information

Ordering Codes:

High Volume

Ordering code Status Package Type Package Qty Note

DW1000-I Active Tray490Available

DW1000-ITR7Active Tape & Reel1000Available

DW1000-ITR13Active Tape & Reel4000Available Samples

Ordering Code Status Package Type Package Qty Note

DW1000-I Active Tray10-490Available

DW1000-ITR7Active Tape & Reel100 – 1000Available

DW1000-ITR13Active Tape & Reel100 – 4000Available

All IC’s are packaged in a48-pin QFN package which is Pb free,RoHS,Green,NiPd lead finish,MSL level3 IC Operation Temperature-40oC to+85oC.

10G LOSSARY

Table30:Glossary of Terms Abbreviation Full Title Explanation

EIRP Equivalent

Isotropically

Radiated Power

The amount of power that a theoretical isotropic antenna(which evenly distributes

power in all directions)would emit to produce the peak power density observed in the

direction of maximum gain of the antenna being used.

ETSI European

Telecommunication

Standards Institute

Regulatory body in the EU charged with the management of the radio spectrum and

the setting of regulations for devices that use it

FCC Federal

Communications

Commission

Regulatory body in the USA charged with the management of the radio spectrum and

the setting of regulations for devices that use it.

FFD Full Function Device Defined in the context of the IEEE802.15.4-2011[1]standard.

GPIO General Purpose

Input/Output Pin of an IC that can be configured as an input or output under software control and has no specifically identified function.

IEEE Institute of Electrical

and Electronic

Engineers

Is the world’s largest technical professional society.It is designed to serve

professionals involved in all aspects of the electrical,electronic and computing fields

and related areas of science and technology.

LIFS Long Inter-Frame

Spacing

Defined in the context of the IEEE802.15.4-2011[1]standard.

LNA Low Noise Amplifier Circuit normally found at the front-end of a radio receiver designed to amplify very low

level signals while keeping any added noise to as low a level as possible

LOS Line of Sight Physical radio channel configuration in which there is a direct line of sight between

the transmitter and the receiver.

Open Drain Open Drain A technique allowing a signal to be driven by more than one device.Generally,each device is permitted to pull the signal to ground but when not doing so it must allow the signal to float.Devices should not drive the signal high so as to prevent contention with devices attempting to pull it low.

NLOS Non Line of Sight Physical radio channel configuration in which there is no direct line of sight between

the transmitter and the receiver.

PGA Programmable Gain

Amplifier Amplifier whose gain can be set/changed via a control mechanism usually by changing register values.

PLL Phase Locked Loop Circuit designed to generate a signal at a particular frequency whose phase is related

to an incoming“reference”signal.

PPM Parts Per Million Used to quantify very small relative proportions.Just as1%is one out of a hundred,

1ppm is one part in a million.

RF Radio Frequency Generally used to refer to signals in the range of3kHz to300GHz.In the context of a radio receiver,the term is generally used to refer to circuits in a receiver before down-conversion takes place and in a transmitter after up-conversion takes place.

RFD Reduced Function

Device

Defined in the context of the IEEE802.15.4-2011[1]standard.

RTLS Real Time Location

System

System intended to provide information on the location of various items in real-time.

SFD Start of Frame

Delimiter

Defined in the context of the IEEE802.15.4-2011[1]standard.

SIFS Short Inter-Frame

Spacing

Defined in the context of the IEEE802.15.4-2011[1]standard.

SPI Serial Peripheral

Interface An industry standard method for interfacing between IC’s using a synchronous serial scheme first introduced by Motorola.

TCXO Temperature

Controlled Crystal

Oscillator

A crystal oscillator whose output frequency is very accurately maintained at its

specified value over its specified temperature range of operation.

TWR Two Way Ranging Method of measuring the physical distance between two radio units by exchanging messages between the units and noting the times of transmission and reception. Refer to Decawave’s website for further information.

TDOA Time Difference of

Arrival Method of deriving information on the location of a transmitter.The time of arrival of a transmission at two physically different locations whose clocks are synchronized is noted and the difference in the arrival times provides information on the location of the transmitter.A number of such TDOA measurements at different locations can be used to uniquely determine the position of the transmitter.Refer to Decawave’s website for further information.

11R EFERENCES

[1]IEEE802.15.4-2011or“IEEE Std802.15.4?‐2011”(Revision of IEEE Std802.15.4-2006).IEEE Standard

for Local and metropolitan area networks–Part15.4:Low-Rate Wireless Personal Area Networks(LR-WPANs).IEEE Computer Society Sponsored by the LAN/MAN Standards Committee.Available from https://www.sodocs.net/doc/422687468.html,/

[2]Decawave DW1000User Manual

[3]

[4]

[5]EIA-481-C Standard

12D OCUMENT H ISTORY

Table31:Document History

13M AJOR C HANGES

Revision2.03

Revision2.04

Revision 2.05

Revision 2.06

Revision 2.07

Revision 2.08

Page

Change Description

All Update of version number to 2.05 2 Update to table of contents 4 Modification of copyright notice to 2015

11 Modifications to Table 6 re Rx sensitivity conditions and Table 7 re recommended TCXO coupling capacitor value

20 Update to Figure 20 and Table 15 to further clarify power up timings 21 addition of Figure 21 to further clarify power up timings 23 Addition to heading of Table 16

34 Addition of clarification re power supplies that should be removed to power down the chip 38 Addition of device weight to Figure 40 44 Addition of v2.05 to revision history table 45

Addition of this table

Page

Change Description

All Update of version number to 2.06 All Various typographical / formatting changes

1 Addition of pin pitch / Update to SLEEP current & DEEPSLEEP current

2 Update to table of contents

10 Addition to table 3 to indicate max digital input voltage

37 Modification to figure 39 to clarify referenced layers for impedance matching purposes

40 – 41 Changes to tape and reel drawings NOTE CHANGE IN QFN ORIENTATION vs. FEED DIRECTION 44 Addition of v2.06 to revision history table 45

Addition of this table

Page

Change Description

All Update of version number to 2.08 All Various typographical / formatting changes 10 Update to typ current values for INIT & IDLE states

35 Figure 37: Addition of decoupling caps on VDDLDOA and VDDLDOD 37 Clarification of reference layers in Figure 38 44 Addition of v2.08 to revision history table 45

Addition of this table

Page

Change Description

All Update of version number to 2.07 All Various typographical / formatting changes

35 – 36 Addition of Abracon parts to “Recommended Components” table 44 Addition of v2.07 to revision history table 45

Addition of this table

Page

Change Description

43 Corrections to v2.03 change table

Addition of v2.04 to revision history table Addition of this table

43

Removal of page breaks in heading numbers 11, 12, 13 and 14

Revision2.09

Revision2.10

14A BOUT D ECAWAVE

Decawave is a pioneering fabless semiconductor company whose flagship product,the DW1000,is a complete, single chip CMOS Ultra-Wideband IC based on the IEEE802.15.4-2011[1]UWB standard.This device is the first in a family of parts that will operate at data rates of110kbps,850kbps,6.8Mbps.

The resulting silicon has a wide range of standards-based applications for both Real Time Location Systems (RTLS)and Ultra Low Power Wireless Transceivers in areas as diverse as manufacturing,healthcare,lighting, security,transport,inventory&supply chain management.

Further Information

For further information on this or any other Decawave product contact a sales representative as follows:-Decawave Ltd

Adelaide Chambers

Peter Street

Dublin8

Ireland

e:

w:

常用芯片引脚图

.v .. .. 常用芯片引脚 74LS00数据手册 74LS01数据手册 74LS02数据手册 74LS03数据手册 74LS04数据手册 74LS05数据手册 74LS06数据手册 74LS07数据手册 74LS08数据手册 74LS09数据手册 74LS10数据手册 74LS11数据手册

第2页 共8页 74LS12数据手册 74LS13数据手册 74LS14数据手册 74LS15数据手册 74LS16数据手册 74LS17数据手册 74LS19数据手册 74LS20数据手册 74LS21数据手册 74LS22数据手册 74LS23数据手册 74LS26数据手册 74LS27数据手册 74LS28数据手册

.v .. .. 74LS30数据手册 74LS32数据手册 74LS33数据手册 74LS37数据手册 74LS38数据手册 74LS40数据手册 74LS42数据手册 [1].要求0—15时,灭灯输入(BI )必须开路或保持高电平,如果不要灭十进制数零,则动态灭灯输入(RBI )必须开路或为高电平。 [2].将一低电平直接输入BI 端,则不管其他输入为何电平,所有的输出端均输出为低电平。 [3].当动态灭灯输入(RBI )和A,B,C,D 输入为低电平而试灯输入为高电平时,所有输出端都为低电平并且动态灭灯输入(RBO )处于第电平(响应条件)。 [4].]当灭灯输入/动态灭灯输出(BI/RBO )开朗路或保持高电平而试 灯输入为低电平时,所有各段输出均为高电平。 表中1=高电平,0=低电平。BI/RBO 是线与逻辑,作灭灯输入(BI )或动态灭灯(RBO )之用,或者兼为二者之用。

9013,9014,8050三极管引脚图与管脚功能

9014,9013,8050三极管引脚图与管脚功能 s9014,s9013,s9015,s9012,s9018系列的晶体小功率三极管,把显示文字平面朝自己,从左向右依次为e发射极 b基极 c集电极;对于中小功率塑料三极管按图使其平面朝向自己,三个引脚朝下放置,则从左到右依次为e b c,s8050,8550,C2078 也是和这个一样的。用下面这个引脚图(管脚图)表示: 三极管引脚图e b c 当前,国内各种晶体三极管有很多种,管脚的排列也不相同,在使用中不确定管脚排列的三极管,必须进行测量确定各管脚正确的位置(下面有用万用表测量三极管的三个极的方法),或查找晶体管使用手册可以查询电子资料与单片机资料,明确三极管的特性及相应的技术参数和资料。 非9014,9013系列三极管管脚识别方法: (a) 判定基极。用万用表R×100或R×1k挡测量管子三个电极中每两个极之间的正、反向电阻值。当用第一根表笔接某一电极,而第二表笔先后接触另外两个电极均测得低阻值时,则第一根表笔所接的那个电极即为基极b。这时,要注意万用表表笔的极性,如果红表笔接的是基极b。黑表笔分别接在其他两极时,测得的阻值都较小,则可判定被测管子为PNP型三极管;如果黑表笔接的是基极b,红表笔分别接触其他两极时,测得的阻值较小,则被测三极管为NPN型管如9013,9014,9018。 (b) 判定三极管集电极c和发射极e。(以PNP型三极管为例)将万用表置于 R×100或R×1K挡,红表笔基极b,用黑表笔分别接触另外两个管脚时,所测得的两个电阻值会是一个大一些,一个小一些。在阻值小的一次测量中,黑表笔所接管脚为集电极;在阻值较大的一次测量中,黑表笔所接管脚为发射极。 D 不拆卸三极管判断其好坏的方法。 在实际应用中、小功率三极管多直接焊接在印刷电路板上,由于元件的安装密度大,拆卸比较麻烦,所以在检测时常常通过用万用表直流电压挡,去测量被测管子各引脚的电压值,来推断其工作是否正常,进而判断三极管的好坏。 如是象9013 ,9014一样NPN的用万用表检测他们的引脚,黑表笔接一个极,用红笔分别接其它两极,两个极都有5K阻值时,黑表笔所接就是B极。这时用黑红两表笔分别接其它两极,用舌尖同时添(其实也可以先用舌头添湿一下手指然后用手指去摸,反正都不卫生)黑表笔所接那个极和B极,表指示阻值小的那个

74LS系列芯片引脚图资料大全

74系列芯片引脚图资料大全 作者:佚名来源:本站原创点击数:57276 更新时间:2007年07月26日【字体:大中小】 为了方便大家我收集了下列74系列芯片的引脚图资料,如还有需要请上电子论坛https://www.sodocs.net/doc/422687468.html,/b bs/ 反相器驱动器LS04 LS05 LS06 LS07 LS125 LS240 LS244 LS245 与门与非门LS00 LS08 LS10 LS11 LS20 LS21 LS27 LS30 LS38 或门或非门与或非门LS02 LS32 LS51 LS64 LS65 异或门比较器LS86 译码器LS138 LS139 寄存器LS74 LS175 LS373

反相器: Vcc 6A 6Y 5A 5Y 4A 4Y 六非门 74LS04 ┌┴—┴—┴—┴—┴—┴—┴┐六非门(OC门) 74LS05 _ │14 13 12 11 10 9 8│六非门(OC高压输出) 74LS06 Y = A )│ │ 1 2 3 4 5 6 7│ └┬—┬—┬—┬—┬—┬—┬┘ 1A 1Y 2A 2Y 3A 3Y GND 驱动器: Vcc 6A 6Y 5A 5Y 4A 4Y ┌┴—┴—┴—┴—┴—┴—┴┐ │14 13 12 11 10 9 8│ Y = A )│六驱动器(OC高压输出) 74LS07 │ 1 2 3 4 5 6 7│ └┬—┬—┬—┬—┬—┬—┬┘ 1A 1Y 2A 2Y 3A 3Y GND Vcc -4C 4A 4Y -3C 3A 3Y ┌┴—┴—┴—┴—┴—┴—┴┐ _ │14 13 12 11 10 9 8│ Y =A+C )│四总线三态门74LS125 │ 1 2 3 4 5 6 7│ └┬—┬—┬—┬—┬—┬—┬┘ -1C 1A 1Y -2C 2A 2Y GND

74系列芯片引脚图

74系列芯片引脚图、功能、名称、资料大全(含74LS、74HC等),特别推荐为了方便大家,我收集了下列74系列芯片的引脚图资料。 说明:本资料分3部分:(一)、TXT文档,(二)、图片,(三)、功能、名称、资料。 (一)、TXT文档 反相器驱动器LS04 LS05 LS06 LS07 LS125 LS240 LS244 LS245 与门与非门LS00 LS08 LS10 LS11 LS20 LS21 LS27 LS30 LS38 或门或非门与或非门 LS02 LS32 LS51 LS64 LS65 异或门比较器LS86 译码器LS138 LS139 寄存器LS74 LS175 LS373

反相器: Vcc 6A 6Y 5A 5Y 4A 4Y 六非门 74LS04 ┌┴—┴—┴—┴—┴—┴—┴┐六非门(OC门) 74LS05 _ │14 13 12 11 10 9 8│六非门(OC高压输出) 74LS06 Y = A )│ │ 1 2 3 4 5 6 7│ └┬—┬—┬—┬—┬—┬—┬┘ 1A 1Y 2A 2Y 3A 3Y GND 驱动器: Vcc 6A 6Y 5A 5Y 4A 4Y ┌┴—┴—┴—┴—┴—┴—┴┐ │14 13 12 11 10 9 8│ Y = A )│六驱动器(OC高压输出) 74LS07 │ 1 2 3 4 5 6 7│ └┬—┬—┬—┬—┬—┬—┬┘

1A 1Y 2A 2Y 3A 3Y GND Vcc -4C 4A 4Y -3C 3A 3Y ┌┴—┴—┴—┴—┴—┴—┴┐ _ │14 13 12 11 10 9 8│ Y =A+C )│四总线三态门 74LS125 │ 1 2 3 4 5 6 7│ └┬—┬—┬—┬—┬—┬—┬┘ -1C 1A 1Y -2C 2A 2Y GND Vcc -G B1 B2 B3 B4 B8 B6 B7 B8 ┌┴—┴—┴—┴—┴—┴—┴—┴—┴—┴┐ 8位总线驱动器 74LS245 │20 19 18 17 16 15 14 13 12 11│ )│ DIR=1 A=>B │ 1 2 3 4 5 6 7 8 9 10│ DIR=0 B=>A └┬—┬—┬—┬—┬—┬—┬—┬—┬—┬┘ DIR A1 A2 A3 A4 A5 A6 A7 A8 GND

8050-8550三极管引脚图与管脚识别

9011,9012,9013,9014,9015,9016,9017,9018,8050,8550 三极管引脚图与管脚识别(含贴片) s9014,s9013,s9015,s9012,s9018系列的晶体小功率三极管,把显示文字平面朝自己,从左向右依次为e发射极 b基极 c集电极;对于中小功率塑料三极管按图使其平面朝向自己,三个引脚朝下放置,则从左到右依次为e b c,s8050,8550,C2078 也是和这个一样的。用下面这个引脚图(管脚图)表示: 三极管引脚图 e b c 当前,国内各种晶体三极管有很多种,管脚的排列也不相同,在使用中不确定管脚排列的三极管,必须进行测量确定各管脚正确的位置(下面有用万用表测量三极管的三个极的方法),或查找晶体管使用手册https://www.sodocs.net/doc/422687468.html,首页可以查询电子资料与单片机资料,明确三极管的特性及相应的技术参数和资料。 非9014,9013系列三极管管脚识别方法: (a) 判定基极。用万用表R×100或R×1k挡测量管子三个电极中每两个极之间的正、反向电阻值。当用第一根表笔接某一电极,而第二表笔先后接触另外两个电极均测得低阻值时,则第一根表笔所接的那个电极即为基极b。这时,要注意万用表表笔的极性,如果红表笔接的是基极b。黑表笔分别接在其他两极时,测得的阻值都较小,则可判定被测管子为PNP型三极管;如果黑表笔接的是基极b,红表笔分别接触其他两极时,测得的阻值较小,则被测三极管为NPN型管如9013,9014,9018。 (b) 判定三极管集电极c和发射极e。(以PNP型三极管为例)将万用表置于R×100 或R×1K挡,红表笔基极b,用黑表笔分别接触另外两个管脚时,所测得的两个电阻值会是一个大一些,一个小一些。在阻值小的一次测量中,黑表笔所接管脚为集电极;在阻值较大的一次测量中,黑表笔所接管脚为发射极。 不拆卸三极管判断其好坏的方法。 在实际应用中、小功率三极管多直接焊接在印刷电路板上,由于元件的安装密度大,拆卸比较麻烦,所以在检测时常常通过用万用表直流电压挡,去测量被测管子各引脚的电压值,来推断其工作是否正常,进而判断三极管的好坏。 如是象9013 ,9014一样NPN的用万用表检测他们的引脚,黑表笔接一个极,用红笔分别接其它两极,两个极都有5K阻值时,黑表笔所接就是B极。这时用黑红两表笔分别接

三极管8550

三极管8550是一种常用的普通三极管。它是一种低电压,大电流,小信号的PNP 型硅三极管。 1PNP型 8550三极管引脚图[1] 8550三极管(TO-92封装)管脚图 1、发射极 2、基极 3、集电极 2.种类及参数 集电极-基极电压Vcbo:-40V 工作温度:-55℃to +150℃ 和8050(NPN)相对 主要用途:开关应用、射频放大 8550三级管参数: 类型:开关型; 极性:PNP; 材料:硅; 最大集电极电流(A):0.5 A; 直流电增益:10 to 60; 功耗:625 mW; 最大集电极发射电压(VCEO):25; 频率:150MHz PE8550 硅NPN 30V 1.5A 1.1W 3DG8550 硅NPN 25V 1.5A FT=190 *K 2SC8550 硅NPN 25V 1.5A FT=190 *K MC8550 硅NPN 25V 700mA 200mW 150MHz CS8550 硅NPN 25V 1.5A FT=190 *K 8050S 8550S S8050 S8550 参数: 耗散功率0.625W(贴片:0.3W) 集电极电流0.5A

集电极--基极电压40V 集电极--发射极击穿电压25V 特征频率fT 最小150MHZ 典型值产家的目录没给出 按三极管后缀号分为B C D档贴片为L H档 放大倍数B85-160 C120-200 D160-300 L100-200 H200-350 C8050 C8550 参数: 耗散功率1W 集电极电流1.5A 集电极--基极电压40V 集电极--发射极击穿电压25V 特征频率fT 最小100MHZ 典型190MHZ 放大倍数:按三极管后缀号分为B C D档 放大倍数B:85-160 C:120-200 D:160-300 8050SS 8550SS 参数: 耗散功率: 1W(TA=25℃) 2W(TC=25℃) 集电极电流1.5A 集电极--基极电压40V 集电极--发射极击穿电压25V 特征频率fT 最小100MHZ 放大倍数:按三极管后缀号分为B C D D3 共4档 放大倍数B:85-160 C:120-200 D:160-300 D3:300-400 引脚排列有EBC、ECB两种 SS8050 SS8550 参数: 耗散功率: 1W(TA=25℃) 2W(TC=25℃) 集电极电流1.5A 集电极--基极电压40V 集电极--发射极击穿电压25V 特征频率fT 最小100MHZ 放大倍数:按三极管后缀号分为B C D 共3档 放大倍数B:85-160 C:120-200 D:160-300 引脚排列多为EBC UTC的S8050 S8550 引脚排列有EBC 8050S 8550S 引脚排列有ECB 这种管子很少见 参数: 耗散功率1W 集电极电流0.7A 集电极--基极电压30V

三极管8050和8550对管的参数

三极管8050和8550对管的参数 图18050和8550三极管TO-92封装外形和引脚排列 图28050和8550三极管SOT-23封装外形和引脚排列 8050和8550三极管在电路应用中经常作为对管来使用,当然很多时候也作为单管应用。8050 为硅材料NPN型三极管;8550 为硅材料PNP型三极管。 8050S 8550S S8050 S8550 参数: 耗散功率0.625W(贴片:0.3W) 集电极电流0.5A 集电极--基极电压40V 集电极--发射极击穿电压25V 特征频率fT 最小150MHZ 典型值产家的目录没给出 按三极管后缀号分为 B C D档贴片为 L H档 放大倍数B85-160 C120-200 D160-300 L100-200 H200-350

C8050 C8550 参数: 耗散功率1W 集电极电流1.5A 集电极--基极电压40V 集电极--发射极击穿电压25V 特征频率fT 最小100MHZ 典型190MHZ 放大倍数:按三极管后缀号分为 B C D档 放大倍数B:85-160 C:120-200 D:160-300 8050SS 8550SS 参数: 耗散功率: 1W(TA=25℃) 2W(TC=25℃) 集电极电流1.5A 集电极--基极电压40V 集电极--发射极击穿电压25V 特征频率fT 最小100MHZ 放大倍数:按三极管后缀号分为 B C D D3 共4档 放大倍数 B:85-160 C:120-200 D:160-300 D3:300-400 引脚排列有EBC ECB两种 SS8050 SS8550 参数: 耗散功率: 1W(TA=25℃) 2W(TC=25℃) 集电极电流1.5A 集电极--基极电压40V 集电极--发射极击穿电压25V 特征频率fT 最小100MHZ 放大倍数:按三极管后缀号分为 B C D 共3档 放大倍数 B:85-160 C:120-200 D:160-300 引脚排列多为EBC UTC的 S8050 S8550 引脚排列有EBC 8050S 8550S 引脚排列有ECB 这种管子很少见 参数: 耗散功率1W 集电极电流0.7A 集电极--基极电压30V 集电极--发射极击穿电压20V 特征频率fT 最小100MHZ 典型产家的目录没给出 放大倍数:按三极管后缀号分为C D E档 C:120-200 D:160-300 E:280-400

常用实验器件引脚图

常用实验器件引脚图 1. 四2输入正与非门74LS00 Y=AB VCC 4B 4Y 3B 3A 3Y 4A 1A 1B 1Y 2A 2B 2Y GND 2. 四2输入正或非门 74LS02 Y=A+B VCC 4Y 4B 4A 3Y 3B 3A 1Y 1A 1B 2Y 2A 2B GND 3. 六反向器 74LS04 Y=A VCC 6A 6Y 5A 5Y 4A 4Y 1A 1Y 2A 2Y 3A 3Y GND

Y=AB VCC 4B 4A 4Y 3B 3A 3Y 1A 1B 1Y 2A 2B 2Y GND 5. 双4输入正与非门 74LS20 Y=ABCD VCC 2D 2C NC 2B 2A 2Y 1A 1B NC 1C 1D 1Y GND 6. 双与或非门74LS51 2Y=(2A2B)+VCC 1B 1C 1D 1E 1F 1Y 1A 2A 2B 2C 2D 2Y GND (2C2D) 1Y=(1A1B1C)+(1D1E1F)

1Y=A VC C 4B 4A 4Y 3B 3A 3Y 1A 1B 1Y 2A 2B 2Y GND ⊕ B=AB+A B 8. 4位二进制计数器 74LS93 输入NC QA QD GND QB QC 输入NC V NC NC A B R 0(1R 0(2

注:A. 对BCD计数,输出QA连接输入B。 B. 对二五混合进制计数,输出QD连接输入A。 C. 输出QA连接输入B。 D. H=高电平L=低电平X=无关

9. 四2-1线数据选择器/多路开关74LS157 V C C G 4A 4B 4Y 3A 3B 3Y S 1A 1B 1Y 2A 2B 2Y GND 10. 74LS181 B0A0S3S2S1S0CN M GND F0F1F2VCC A1CM+4P A=B B1A2B2 A3B3G F3

S8550三极管

JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY CO., LTD ELECTRICAL CHARACTERISTICS (T a =25℃ unless otherwise specified) Parameter Symbol Test conditions M in T yp Max Unit Collector-base breakdown voltage V (BR)CBO I C = -100u A , I E =0 -40 V Collector-emitter breakdown voltage V (BR)CEO I C = -1mA, I B =0 -25 V Emitter-base breakdown voltage V (BR)EBO I E = -100uA, I C =0 -5 V Collector cut-off current I CBO V CB = -40V, I E =0 -0.1 uA Collector cut-off current I CEO V CE = -20V, I B =0 -0.1 uA Emitter cut-off current I EBO V EB = - 3V, I C =0 -0.1 uA h FE(1) V CE = -1V, I C = -50mA 85 400 DC current gain h FE(2) V CE = -1V, I C = -500mA 50 Collector-emitter saturation voltage V CE(sat) I C =-500mA, I B =-50mA -0.6 V Base-emitter saturation voltage V BE(sat) I C =-500mA, I B =-50mA -1.2 V Transition frequency f T V CE =- 6V, I C =-20mA, f =30MHz 150 MHz CLASSIFICATION OF h FE (1) Rank B C D D3 Range 85-160 120-200 160-300 300-400 A,June,2011

9011_9012_9013_9014_8050_8550三极管的参数及区别

9011,9012,9013,9014,8050,8550三极管的参数及区别 9011 NPN 30V 30mA 400mW 150MHz 放大倍数20-80 9012 PNP 50V 500mA 600mW 低频管放大倍数30-90 9013 NPN 20V 625mA 500mW 低频管放大倍数40-110 8050 NPN 25V 700mA 200mW 150MHz 放大倍数30-100 8550 PNP 40V 1500mA 1000mW 200MHz 放大倍数40-140 详情如下: 硅管,NPN,b和e的导通电压0.7V左右。如,9011 9013 9014 9016 锗管,PNP,b和e的导通电压0.3V左右。如,9012 9015 8550 90系列三极管参数 90系列三极管大多是以90字为开头的,但也有以ST90、C或A90、S90、SS90、UTC90开头的,它们的特性及管脚排列都是一样的。 9011 结构:NPN 集电极-发射极电压 30V 集电极-基电压 50V 射极-基极电压 5V 集电极电流 0.03A 耗散功率 0.4W 结温150℃ 特怔频率平均 370MHZ 放大倍数:D28-45 E39-60 F54-80 G72-108 H97-146 I132-198 9012 结构:PNP 集电极-发射极电压 -30V 集电极-基电压 -40V 射极-基极电压 -5V 集电极电流 0.5A 耗散功率 0.625W 结温150℃ 特怔频率最小 150MHZ 放大倍数:D64-91 E78-112 F96-135 G122-166 H144-220 I190-300 9013 结构:NPN 集电极-发射极电压 25V 集电极-基电压 45V 射极-基极电压 5V 集电极电流 0.5A

74系列元件引脚图

反相器驱动器LS04 LS05 LS06 LS07 LS125 LS240 LS244 LS24 5 与门与非门LS00 LS08 LS10 LS11 LS20 LS21 LS27 LS30 LS38 或门或非门与或非门LS02 LS32 LS51 LS64 LS65 异或门比较器LS86 译码器LS138 LS139 寄存器LS74 LS175 LS373 反相器: Vcc 6A 6Y 5A 5Y 4A 4Y 六非门 74LS04 ┌┴—┴—┴—┴—┴—┴—┴┐六非门(OC门) 74LS05 _ │14 13 12 11 10 9 8│六非门(OC高压输出) 74LS06 Y = A )│ │1 2 3 4 5 6 7│ └┬—┬—┬—┬—┬—┬—┬┘ 1A 1Y 2A 2Y 3A 3Y GND 驱动器: Vcc 6A 6Y 5A 5Y 4A 4Y ┌┴—┴—┴—┴—┴—┴—┴┐ │14 13 12 11 10 9 8│ Y = A )│六驱动器(OC高压输出) 74LS07 │1 2 3 4 5 6 7│ └┬—┬—┬—┬—┬—┬—┬┘ 1A 1Y 2A 2Y 3A 3Y GND Vcc -4C 4A 4Y -3C 3A 3Y ┌┴—┴—┴—┴—┴—┴—┴┐ _ │14 13 12 11 10 9 8│

Y =A+C )│四总线三态门74LS125 │1 2 3 4 5 6 7│ └┬—┬—┬—┬—┬—┬—┬┘ -1C 1A 1Y -2C 2A 2Y GND Vcc -G B1 B2 B3 B4 B8 B6 B7 B8 ┌┴—┴—┴—┴—┴—┴—┴—┴—┴—┴┐ 8位总线驱动器74LS245 │20 19 18 17 16 15 14 13 12 11│ )│ DIR=1 A=>B │1 2 3 4 5 6 7 8 9 10│ DIR=0 B=>A └┬—┬—┬—┬—┬—┬—┬—┬—┬—┬┘ DIR A1 A2 A3 A4 A5 A6 A7 A8 GND 页首非门,驱动器与门,与非门或门,或非门异或门,比较器译码器寄存器 正逻辑与门,与非门: Vcc 4B 4A 4Y 3B 3A 3Y ┌┴—┴—┴—┴—┴—┴—┴┐ │14 13 12 11 10 9 8│ Y = AB )│ 2输入四正与门74LS08 │1 2 3 4 5 6 7│ └┬—┬—┬—┬—┬—┬—┬┘ 1A 1B 1Y 2A 2B 2Y GND Vcc 4B 4A 4Y 3B 3A 3Y ┌┴—┴—┴—┴—┴—┴—┴┐ __ │14 13 12 11 10 9 8│ Y = AB )│ 2输入四正与非门74LS00 │1 2 3 4 5 6 7│ └┬—┬—┬—┬—┬—┬—┬┘ 1A 1B 1Y 2A 2B 2Y GND Vcc 1C 1Y 3C 3B 3A 3Y ┌┴—┴—┴—┴—┴—┴—┴┐ ___ │14 13 12 11 10 9 8│ Y = ABC )│ 3输入三正与非门74LS10 │1 2 3 4 5 6 7│ └┬—┬—┬—┬—┬—┬—┬┘ 1A 1B 2A 2B 2C 2Y GND

9014,9013,8050三极管引脚图与管脚识别方法

s9014,s9013,s9015,s9012,s9018系列的晶体小功率三极管,把显示文字平面朝自己,从左向右依次为e发射极 b基极 c集电极;对于中小功率塑料三极管按图使其平面朝向自己,三个引脚朝下放置,则从左到右依次为e b c,s8050,8550,C2078 也是和这个一样的。用下面这个引脚图(管脚图)表示: 三极管引脚图 e b c 当前,国内各种晶体三极管有很多种,管脚的排列也不相同,在使用中不确定管脚排列的三极管,必须进行测量确定各管脚正确的位置(下面有用万用表测量三极管的三个极的方法),或查找晶体管使用手册,明确三极管的特性及相应的技术参数和资料。 非9014,9013系列三极管管脚识别方法: (a) 判定基极。用万用表R×100或R×1k挡测量管子三个电极中每两个极之间的正、反向电阻值。当用第一根表笔接某一电极,而第二表笔先后接触另外两个电极均测得低阻值时,则第一根表笔所接的那个电极即为基极b。这时,要注意万用表表笔的极性,如果红表笔接的是基极b。黑表笔分别接在其他两极时,测得的阻值都较小,则可判定被测管子为PNP型三极管;如果黑表笔接的是基极b,红表笔分别接触其他两极时,测得的阻值较小,则被测三极管为NPN型管如9013,9014,9018。 (b) 判定三极管集电极c和发射极e。(以PNP型三极管为例)将万用表置于R×100或R×1K挡,红表笔基极b,用黑表笔分别接触另外两个管脚时,所测得的两个电阻值会是一个大一些,一个小一些。在阻值小的一次测量中,黑表笔所接管脚为集电极;在阻值较大的一次测量中,黑表笔所接管脚为发射极。 D 不拆卸三极管判断其好坏的方法。 在实际应用中、小功率三极管多直接焊接在印刷电路板上,由于元件的安装密度大,拆卸比较麻烦,所以在检测时常常通过用万用表直流电压挡,去测量被测管子各引脚的电压值,来推断其工作是否正常,进而判断三极管的好坏。 如是象9013 ,9014一样NPN的用万用表检测他们的引脚,黑表笔接一个极,用红笔分别接其它两极,两个极都有5K阻值时,黑表笔所接就是B极。这时用黑红两表笔分别接其它两极,用舌尖同时添(其实也可以先用舌头添湿一下手指然后用手指去摸,反正都不卫生)黑表笔所接那个极和B极,表指示阻值小的那个黑表所接就是C极。(以上所说为用指针表所测,数字表为红笔数字万用表内部的正负级是和指正表相反的。) 9011,9012,9013,9014,8050,8550三极管的主要参数数据 9011 NPN 30V 30mA 400mW 150MHz 放大倍数20-80 9012 PNP 50V 500mA 600mW 低频管放大倍数30-90 9013 NPN 20V 625mA 500mW 低频管放大倍数40-110 9014 NPN 45V 100mA 450mW 150MHz 放大倍数20-90 8050 NPN 25V 700mA 200mW 150MHz 放大倍数30-100 8550 PNP 40V 1500mA 1000mW 200MHz 放大倍数40-140

8550、8050引脚参数

8550、8050引脚参数 https://www.sodocs.net/doc/422687468.html,/piane/blog/item/6a3983b4815bcdc736d3cadb.html 8550是电子电路中常用到的小功率pnp型硅晶体三极管。很多放大电路中都要用到他,下面是引脚资料介绍. <三极管8550管脚图> 1.发射极 2.基极 3.集电极 8550参数: 集电极-基极电压Vcbo:-40V 工作温度:-55℃to +150℃ 和8050(NPN)相对 贴片smt封装的8550三极管引脚图及功能. -------------------------------------------------------------- 8050三极管参数:类型:开关型; 极性:NPN; 材料:硅; 最大集存器电流(A):0.5 A; 直流电增益:10 to 60; 功耗:625 mW; 最大集存器发射电(VCEO):25; 频率:150 KHz

8050引脚图 芯片尺寸:4 英寸(100mm) 芯片代码:C060AJ-00 芯片厚度:240±20μm 管芯尺寸:600×600μm 2 焊位尺寸:B 极130×150μm 2;E 极140×130μm 2电极金属:铝 背面金属:金 典型封装:S8050,H8050 极限值(Ta=25℃)(封装形式:TO-92) Tstg——贮存温度-55~150℃ Tj——结温150℃ PC——集电极耗散功率1W VCBO——集电极—基极电压40V VCEO——集电极—发射极电压25V VEBO——发射极—基极电压6V IC——集电极电流1.2A 电参数(Ta=25℃)(封装形式:TO-92)

常用三极管参数

常用三极管参数 MPSA42 NPN 21E 电话视频放大300V0.5A0.625W MPSA92 PNP 21E 电话视频放大300V0.5A0.625W MPS2222A NPN 21 高频放大75V0.6A0.625W300MHZ 9011 NPN EBC 高频放大50V30mA0.4W150MHz 9012 PNP 贴片低频放大50V0.5A0.625W 9012 PNP 低频放大50V0.5A0.625W 9013 NPN EBC 低频放大50V0.5A0.625W ] 9013 NPN 贴片低频放大50V0.5A0.625W 9014 NPN EBC 低噪放大50V0.1A0.4W150MHZ 9015 PNP EBC 低噪放大50V0.1A0.4W150MHZ 9018 NPN EBC 高频放大30V50MA0.4W1GHZ 8050 NPN EBC 高频放大40V1.5A1W100MHZ 8550 PNP EBC 高频放大40V1.5A1W100MHZ 2N2222 NPN 4A 高频放大60V0.8A0.5W25/200NSβ=45 2N2222A NPN 小铁高频放大75V0.6A0.625W300MHZ 2N2369 NPN 4A 开关40V0.5A0.3W800MHZ 2N2907 NPN 4A 通用60V0.6A0.4W26/70NSβ=200 2N3055 NPN 12 功率放大100V15A115W 2N3440 NPN 6 视放开关450V1A1W15MHZ 2N3773 NPN 12 音频功放开关160V16A150W COP 2N6609 2N3904 NPN 21E 通用60V0.2Aβ=100-400 2N3906 PNP 21E 通用40V0.2Aβ=100-400

常用三极管

一、概述 s9014,s9013,s9015,s9012,s9018系列的晶体小功率三极管,把显示文字平面朝自己,从左向右依次为e发射极 b基极 c集电极;对于中小功率塑料三极管按图使其平面朝向自己,三个引脚朝下放置,则从左到右依次为e b c, s8050,8550,C2078 也是和这个一样的。用下面这个引脚图(管脚图)表示:三极管引脚图 1:e 2:b 3:c 二、三极管管脚判断 当前,国内各种晶体三极管有很多种,管脚的排列也不相同,在使用中不确定管脚排列的三极管,必须进行测量确定各管脚正确的位置(下面有用万用表测量三极管的三个极的方法),或查找晶体管使用手册,明确三极管的特性及相应的技术参数和资料。 非9014,9013系列三极管管脚识别方法: (a)判定基极。用万用表R×100或R×1k挡测量管子三个电极中每两个极之间的正、反向电阻值。当用第一根表笔接某一电极,而第二表笔先后接触另外两个电极均测得低阻值时,则第一根表笔所接的那个电极即为基极b。这时,要注意万用表表笔的极性,如果红表笔接的是基极b。黑表笔分别接在其他两极时,测得的阻值都较小,则可判定被测管子为PNP型三极管;如果黑表笔接的是基极b,红表笔分别接触其他两极时,测得的阻值较小,则被测三极管为NPN型管如9013,9014,9018。 (b)判定三极管集电极c和发射极e。(以PNP型三极管为例)将万用表置于R×100或R×1K挡,红表笔基极b,用黑表笔分别接触另外两个管脚时,所测得

的两个电阻值会是一个大一些,一个小一些。在阻值小的一次测量中,黑表笔所接管脚为集电极;在阻值较大的一次测量中,黑表笔所接管脚为发射极。 三、三极管好坏判断 在实际应用中、小功率三极管多直接焊接在印刷电路板上,由于元件的安装密度大,拆卸比较麻烦,所以在检测时常常通过用万用表直流电压挡,去测量被测管子各引脚的电压值,来推断其工作是否正常,进而判断三极管的好坏。 如是象9013 ,9014一样NPN的用万用表检测他们的引脚,黑表笔接一个极,用红笔分别接其它两极,两个极都有5K阻值时,黑表笔所接就是B极。这时用黑红两表笔分别接其它两极,用舌尖同时添(其实也可以先用舌头添湿一下手指然后用手指去摸,反正都不卫生)黑表笔所接那个极和B极,表指示阻值小的那个黑表所接就是C极。(以上所说为用指针表所测,数字表为红笔数字万用表内部的正负级是和指正表相反的。) 四、主要参数 9011,9012,9013,9014,8050,8550三极管的主要参数数据 9011 NPN 30V 30mA 400mW 150MHz 放大倍数20-80 9012 PNP 50V 500mA 600mW 低频管放大倍数30-90 9013 NPN 20V 625mA 500mW 低频管放大倍数40-110 9014 NPN 45V 100mA 450mW 150MHz 放大倍数20-90 8050 NPN 25V 700mA 200mW 150MHz 放大倍数30-100 8550 PNP 40V 1500mA 1000mW 200MHz 放大倍数40-140。 详情如下: 90系列三极管参数 90系列三极管大多是以90字为开头的,但也有以ST90、C或A90、S90、SS90、UTC90开头的,它们的特性及管脚排列都是一样的。

代换相应的8050或8550三极管

代换相应的8050或8550三极管 (a) 判定基极。用万用表R×100或R×1k挡测量管子三个电极中每两个极之间的正、反向电阻值。当用第一根表笔接某一电极,而第二表笔先后接触另外两个电极均测得低阻值时,则第一根表笔所接的那个电极即为基极b。这时,要注意万用表表笔的极性,如果红表如果黑表笔接的是基极b,红表笔分别接触其他两极时,测得的阻值较小,则被测三极管为NPN 型管如9013,9014,9018。 (b) 判定三极管集电极c和发射极e。(以PNP型三极管为例)将万用表置于R×100或R×1K挡,红表笔基极b,用黑表笔分别接触另外两个管脚时,所测得的两个电阻值会是一个大一些,一个小一些。在阻值小的一次测量中,黑表笔所接管脚为集电极;在阻值较大的一次测量中,黑表笔所接管脚为发射极。 D 不拆卸三极管判断其好坏的方法。 在实际应用中、小功率三极管多直接焊接在印刷电路板上,由于元件的安装密度大,拆卸比较麻烦,所以在检测时常常通过用万用表直流电压挡,去测量被测管子各引脚的电压值,来推断其工作是否正常,进而判断三极管的好坏。 如是象9013 ,9014一样NPN的用万用表检测他们的引脚,黑表笔接一个极,用红笔分别接其它两极,两个极都有5K阻值时,黑表笔所接就是B极。这时用黑红两表笔分别接其它两极,用舌尖同时添(其实也可以先用舌头添湿一下手指然后用手指去摸,反正都不卫生)黑表笔所接那个极和B极,表指示阻值小的那个黑表所接就是C极。(以上所说为用指针表所测,数字表为红笔数字万用表内部的正负级是和指正表相反的。)9011,9012,9013,9014,8050,8550三极管的主要参数数据 9011 NPN 30V 30mA 400mW 150MHz 放大倍数20-80 9012 PNP 50V 500mA 600mW 低频管放大倍数30-90 9013 NPN 20V 625mA 500mW 低频管放大倍数40-110 9014 NPN 45V 100mA 450mW 150MHz 放大倍数20-90 8050 NPN 25V 700mA 200mW 150MHz 放大倍数30-100 8550 PNP 40V 1500mA 1000mW 200MHz 放大倍数40-140。 详情如下: 90系列三极管参数 90系列三极管大多是以90字为开头的,但也有以ST90、C或A90、S90、SS90、UTC90开头的,它们的特性及管脚排列都是一样的。 9011 结构:NPN 集电极-发射极电压30V 集电极-基电压50V 射极-基极电压5V 集电极电流0.03A 耗散功率0.4W 结温150℃ 特怔频率平均370MHZ

常用芯片引脚图

. . 常用芯片引脚 74LS00数据手册 74LS01数据手册 74LS02数据手册 74LS03数据手册 74LS04数据手册 74LS05数据手册 74LS06数据手册 74LS07数据手册 74LS08数据手册 74LS09数据手册 74LS10数据手册 74LS11数据手册

第2页 共8页 74LS12数据手册 74LS13数据手册 74LS14数据手册 74LS15数据手册 74LS16数据手册 74LS17数据手册 74LS19数据手册 74LS20数据手册 74LS21数据手册 74LS22数据手册 74LS23数据手册 74LS26数据手册 74LS27数据手册 74LS28数据手册

. . 74LS30 数据手册 74LS32数据手册 74LS33 数据手册 74LS37 数据手册 74LS38数据手册 74LS40 数据手册 74LS42数据手册 [1].要求0—15时,灭灯输入(BI )必须开路或保持高电平,如果不要灭十进制数零,则动态灭灯输入(RBI )必须开路或为高电平。 [2].将一低电平直接输入BI 端,则不管其他输入为何电平,所有的输出端均输出为低电平。 [3].当动态灭灯输入(RBI )和A,B,C,D 输入为低电平而试灯输入为高电平时,所有输出端都为低电平并且动态灭灯输入(RBO )处于第电平(响应条件)。 [4].]当灭灯输入/动态灭灯输出(BI/RBO )开朗路或保持高电平而试灯 输入为低电平时,所有各段输出均为高电平。 表中1=高电平,0=低电平。BI/RBO 是线与逻辑,作灭灯输入(BI )或动态灭灯(RBO )之用,或者兼为二者之用。

简析8050三极管引脚图

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常用IC引脚图

附录五、常用IC引脚图 1、STC89C51单片机 2、8255并行I/O接口 T2/P1.0 -- 1 40 -- VCC PA3-- 1 40 --PA4 T2EX/P1.1-- 2 39 -- P0.0/AD0 PA2-- 2 39 --PA5 P1.2 -- 3 38 -- P0.1/AD1 PA1-- 3 38 --PA6 P1.3 -- 4 37 -- P0.2/AD2 PA0-- 4 37 --PA7 P1.4 -- 5 36 -- P0.3/AD3 RD -- 5 36 --WR P1.5 -- 6 35 -- P0.4/AD4 CS -- 6 35 --RESET P1.6-- 7 34 -- P0.5/AD5 GND-- 7 34 --D0 P1.7 -- 8 33 -- P0.6/AD6 A1 -- 8 33 --D1 RST -- 9 32 -- P0.7/AD7 A0 -- 9 32 --D2 RXD/P3.0-- 10 31 –EA(EA)PC7 -- 10 31 --D3 TXD/P3.1-- 11 30 --ALE/PROG PC6 -- 11 30 --D4 INT0/P3.2-- 12 29 --PSEN PC5 -- 12 29 --D5 INT1/P3.3-- 13 28 -- P2.7/A15 PC4 -- 13 28 --D6 T0/P3.4 -- 14 27 -- P2.6/A14 PC0 -- 14 27 --D7 T1/P3.5 -- 15 26 -- P2.5/A13 PC1 -- 15 26 --VCC WR/P3.6 -- 16 25 -- P2.4/A12 PC2 -- 16 25 --PB7 RD/P3.7 -- 17 24 -- P2.3/A11 PC -- 17 24 --PB6 XTAL2 -- 18 23 -- P2.2/A10 PB0 -- 18 23 --PB5 XTAL1 -- 19 22 -- P2.1/A9 PB1 -- 19 22 --PB4 VSS -- 20 21 -- P2.0/A8 PB2 -- 20 21 --PB3 注:STC89C51芯片的第31脚在用外接存储器时接低(地)电位,而在使用片内存储器时接高电位。 3、74LS373 八D锁存器 4、LED七段码显示器(共阴极型、单字) CE - 1 20 –VCC g f G a b 1Q - 2 19 –8Q 1D - 3 18 –8D a 2D -- 4 17 –7D f b 2Q -- 5 16 –7Q g 3Q -- 6 15 –6Q e c

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