_______________General Description
The MAX199 multi-range, 12-bit data-acquisition system (DAS) requires only a single +5V supply for operation,and converts analog signals up to ±4V at its inputs. This system provides eight analog input channels that are independently software programmable for a variety of ranges: ±V REF , ±V REF/2, 0V to V REF , or 0V to V REF/2.This increases effective dynamic range to 14 bits, and provides the user flexibility to interface 4mA-to-20mA,±12V, and ±15V powered sensors to a single +5V sys-tem. In addition, the converter is fault-protected to ±16.5V; a fault condition on any channel will not affect the conversion result of the selected channel. Other fea-tures include a 5MHz bandwidth track/hold, 100ksps throughput rate, internal/external clock, internal/external acquisition control, 8+4 parallel interface, and operation with an internal 4.096V or external reference.
A hardware SHDN pin and two programmable power-down modes (STBYPD, FULLPD) provide low-current shutdown between conversions. In STBYPD mode, the reference buffer remains active, eliminating start-up delays.
The MAX199 employs a standard microprocessor (μP)interface. Its three-state data I/O interface is configured to operate with 8-bit data buses, and data-access and bus-release timing specifications are compatible with most popular μPs. All logic inputs and outputs are TTL/CMOS compatible.
The MAX199 is available in 28-pin DIP, wide SO, SSOP,and ceramic SB packages.
For a different combination of input ranges (±10V, ±5V,0V to 10V, 0V to 5V), see the MAX197 data sheet. For 12-bit bus interfaces, see the MAX196/MAX198 data sheet.
________________________Applications
Industrial-Control Systems Robotics
Data-Acquisition Systems Automatic Testing Systems Medical Instruments Telecommunications
____________________________Features
o 12-Bit Resolution, 1/2LSB Linearity o Single +5V Operation
o Software-Selectable Input Ranges:
±V REF , ±V REF/2, 0V to V REF , 0V to V REF/2o Internal 4.096V or External Reference
o Fault-Protected Input Multiplexer (±16.5V)o 8 Analog Input Channels
o 6μs Conversion Time, 100ksps Sampling Rate o Internal or External Acquisition Control o Two Power-Down Modes o Internal or External Clock
MAX199
Multi-Range (±4V , ±2V , +4V , +2V),
+5V Supply, 12-Bit DAS with 8+4 Bus Interface
________________________________________________________________Maxim Integrated Products
1
__________________Pin Configuration
Call toll free 1-800-722-8266 for free samples or literature.
19-0401; Rev 0; 6/95
Functional Diagram appears at end of data sheet.*Dice are specified at T A = +25°C, DC parameters only.
M A X 199
Multi-Range (±4V , ±2V , +4V , +2V),
+5V Supply, 12-Bit DAS with 8+4 Bus Interface 2_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(V DD = 5V ±5%; unipolar/bipolar range; external reference mode, V REF = 4.096V; 4.7μF at REF pin; external clock, f CLK = 2.0MHz with 50% duty cycle; T A = T MIN to T MAX , unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
V DD to AGND............................................................-0.3V to +7V AGND to DGND.....................................................-0.3V to +0.3V REF to AGND..............................................-0.3V to (V DD + 0.3V)REFADJ to AGND.......................................-0.3V to (V DD + 0.3V)Digital Inputs to DGND...............................-0.3V to (V DD + 0.3V)Digital Outputs to DGND............................-0.3V to (V DD + 0.3V)CH0–CH7 to AGND ..........................................................±16.5V Continuous Power Dissipation (T A = +70°C)
Narrow Plastic DIP (derate 14.29mW/°C above +70°C)....1143mW
Wide SO (derate 12.50mW/°C above +70°C)..............1000mW SSOP (derate 9.52mW/°C above +70°C)......................762mW Narrow Ceramic SB (derate 20.00mW/°C above +70°C)..1600mW Operating Temperature Ranges
MAX199_C_ _.......................................................0°C to +70°C MAX199_E_ _.....................................................-40°C to +85°C MAX199_M_ _..................................................-55°C to +125°C Storage Temperature Range.............................-65°C to +150°C Lead Temperature (soldering, 10sec).............................+300°C
MAX199
Multi-Range (±4V , ±2V , +4V , +2V),
+5V Supply, 12-Bit DAS with 8+4 Bus Interface
_______________________________________________________________________________________3
ELECTRICAL CHARACTERISTICS (continued)
(V DD = 5V ±5%; unipolar/bipolar range; external reference mode, V REF = 4.096V; 4.7μF at REF pin; external clock, f CLK = 2.0MHz with 50% duty cycle; T A = T MIN to T MAX , unless otherwise noted.)
M A X 199
Multi-Range (±4V , ±2V , +4V , +2V),
+5V Supply, 12-Bit DAS with 8+4 Bus Interface 4_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V DD = 5V ±5%; unipolar/bipolar range; external reference mode, V REF = 4.096V; 4.7μF at REF pin; external clock, f CLK = 2.0MHz with 50% duty cycle; T A = T MIN to T MAX , unless otherwise noted.)
MAX199
Multi-Range (±4V , ±2V , +4V , +2V),
+5V Supply, 12-Bit DAS with 8+4 Bus Interface
_______________________________________________________________________________________5
Note 1:Accuracy specifications tested at V DD = 5.0V. Performance at power-supply tolerance limits guaranteed by Power-Supply Rejection test. Tested for the ±4.096V input range.
Note 2:External reference: V REF = 4.096V, offset error nulled, ideal last code transition = FS - 3/2LSB.Note 3:Ground “on” channel; sine wave applied to all “off” channels.
Note 4:Maximum full-power input frequency for 1LSB error with 10ns jitter = 3kHz.Note 5:Guaranteed by design. Not tested.Note 6:Use static loads only.
Note 7:Tested using internal reference.
Note 8:PSRR measured at full-scale. V DD = 4.75V to 5.25V.
Note 9:External acquisition timing: starts at rising edge of WR with control bit ACQMOD = low; ends at rising edge of WR with ACQMOD = high.
Note 10:Not subject to production testing. Provided for design guidance only.
Note 11:All input control signals specified with t R = t F = 5ns from a voltage level of 0.8V to 2.4V.
Note 12:t DO and t DO1are measured with the load circuits of Figure 2 and defined as the time required for an output to cross 0.8V or 2.4V.
Note 13:
t TR is defined as the time required for the data lines to change by 0.5V.
TIMING CHARACTERISTICS
(V DD = 5V ±5%; unipolar/bipolar range; external reference mode, V REF = 4.096V; 4.7μF at REF pin; external clock, f CLK = 2.0MHz with 50% duty cycle; T A = T MIN to T MAX , unless otherwise noted.)
M A X 199
Multi-Range (±4V , ±2V , +4V , +2V),
+5V Supply, 12-Bit DAS with 8+4 Bus Interface 6_______________________________________________________________________________________
__________________________________________Typical Operating Characteristics
(T A = +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY
vs. DIGITAL CODE
DIGITAL CODE
I N T E G R A L N O N L I N E A R I T Y (L S B )
0-120
050
25
FFT PLOT
-100-60-40-20
FREQUENCY (kHz)
-80f TONE = 10kHz f SAMPLE = 100kHz
10.0
1
10
100
EFFECTIVE NUMBER OF BITS vs. INPUT FREQUENCY
10.5
INPUT FREQUENCY (kHz)
E F F E C T I V E N U M B E R O F B I T S
11.0
11.5
12.0
4.100
4.080
-55
-3545105125
TEMPERATURE (°C)
V R E F (V )
-15
52565854.0954.090
4.085
REFERENCE OUTPUT VOLTAGE (V REF )
vs. TEMPERATURE
0.330.27
-70-5050110130
TEMPERATURE (°C)
C H A N N E L -T O -C H A N N E L G A I N -E R R O R M A T C H I N G (L S B )
-30-10103070900.320.300.290.28
0.31CHANNEL-TO-CHANNEL
GAIN-ERROR MATCHING vs. TEMPERATURE
M A X 199-7
M A X 199-5-70-5050110130
TEMPERATURE (°C)
P S R R (L S B )
-30-10103070900.20.4
-0.2-0.4
-0.6
POWER-SUPPLY REJECTION RATIO
vs. TEMPERATURE M A X 199-6
0.10
-70-5050110130
TEMPERATURE (°C)
C H A N N E L -T O -C H A N N E L O F F S E T -E R R O R M A T C H I N G (L S B )
-30-10103070900.20
0.16
0.140.12
0.18CHANNEL-TO-CHANNEL
OFFSET-ERROR MATCHING vs. TEMPERATURE
MAX199
Multi-Range (±4V , ±2V , +4V , +2V),
+5V Supply, 12-Bit DAS with 8+4 Bus Interface
_______________________________________________________________________________________
7
______________________________________________________________Pin Description
Figure 1. Reference-Adjust Circuit Figure 2. Load Circuits for Enable Time
M A X 199
Multi-Range (±4V , ±2V , +4V , +2V),
+5V Supply, 12-Bit DAS with 8+4 Bus Interface 8
_______________Detailed Description
Converter Operation
The MAX199, a multi-range, fault-tolerant ADC, uses successive approximation and internal input track/hold (T/H) circuitry to convert an analog signal to a 12-bit digital output. The parallel-output format provides easy interface to microprocessors (μPs). Figure 3 shows the MAX199 in its simplest operational configuration.
Analog-Input Track/Hold
In the internal acquisition control mode (control bit D5ing edge, and enters its hold mode when the internally timed (6 clock cycles) acquisition interval ends. In bipo-lar mode, a low-impedance input source, which settles in less than 1.5μs, is required to maintain conversion accuracy at the maximum conversion rate.
When configured for unipolar mode, the input does not need to be driven from a low-impedance source. The acquisition time (t AZ ) is a function of the source output resistance (R S ), the channel input resistance (R IN ), and the T/H capacitance.
Acquisition time is calculated by:
For 0V to V REF : t AZ = 9 x (R S + R IN ) x 16pF For 0V to V REF/2: t AZ = 9 x (R S + R IN ) x 32pF
where R IN = 7k ?, and t AZ is never less than 2μs (0V to V REF range) or 3μs (0V to V REF/2range).
In the external acquisition control mode (D5 = 1), the T/H enters its tracking mode on the first WR rising edge and enters its hold mode when it detects the second WR rising edge with D5 = 0. See the External Acquisition section.
Input Bandwidth
The ADC’s input tracking circuitry has a 5MHz small-signal bandwidth. When using the internal acquisition mode with an external clock frequency of 2MHz, a 100ksps throughput rate can be achieved. It is possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using undersampling techniques. To avoid high-frequency signals being aliased into the fre-quency band of interest, anti-alias filtering is recom-mended (MAX274/MAX275 continuous-time filters).
Input Range and Protection
Figure 4 shows the equivalent input circuit. The MAX199can be programmed for input ranges of ±V REF , ±V REF/2,0V to V REF , or 0V to V REF/2by setting the appropriate control bits (D3, D4) in the control byte (see Tables 1 and 2). When an external reference is applied at REFADJ, the voltage at REF is given by V REF = 1.6384 x V REFADJ (2.4V < V REF < 4.18V).
The input channels are overvoltage protected to ±16.5V. This protection is active even if the device is in power-down mode.
Even with V DD = 0V, the input resistive network provides current-limiting that adequately protects the device.
Digital Interface
Input data (control byte) and output data are multiplexed on a three-state parallel interface. This parallel I/O can easily be interfaced with a μP. CS, WR, and RD control the write and read operations. CS is the standard chip-select signal, which enables a μP to address the MAX199as an I/O port. When high, it disables the WR and RD inputs and forces the interface into a high-Z state.
Input Format
The control byte is latched into the device, on pins D7–D0, during a write cycle. Table 1 shows the control-byte format.
Output Data Format
The output data format is binary in unipolar mode and twos-complement binary in bipolar mode. When read-ing the output data, CS and RD must be low. When HBEN is low, the lower eight bits are read. When HBEN is high, the upper four MSBs are available and the out-put data bits D4–D7 are either set low (in unipolar mode) or set to the value of the MSB (in bipolar mode)(Table 5).
MAX199
Multi-Range (±4V , ±2V , +4V , +2V),
+5V Supply, 12-Bit DAS with 8+4 Bus Interface
Table 1. Control-Byte Format
D7 (MSB)D6D5D4D3D2D1D0 (LSB)PD1PD0ACQMOD
RNG
BIP
A2
A1
A0
Table 3. Clock and Power-Down Selection
PD1PD0DEVICE MODE
00Normal Operation / External Clock Mode 01Normal Operation / Internal Clock Mode 10Standby Power-Down (STBYPD); clock mode is unaffected
1
1
Full Power-Down (FULLPD); clock mode is unaffected
Table 2. Range and Polarity Selection
BIP RNG INPUT RANGE (V)
000 to V REF/2010 to V REF 10±V REF/21
1
±V REF
Table 4. Channel Selection
BIT NAME DESCRIPTION
7, 6PD1, PD0These two bits select the clock and power-down modes (Table 3).
5ACQMOD 0 = internally controlled acquisition (6 clock cycles), 1 = externally controlled acquisition 4RNG Selects the full-scale voltage magnitude at the input (Table 2).3BIP Selects unipolar or bipolar conversion mode (Table 2).
2, 1, 0
A2, A1, A0
These are address bits for the input mux to select the “on” channel (Table 4).
M A X 199
How to Start a Conversion
Conversions are initiated with a write operation, which selects the mux channel and configures the MAX199 for either unipolar or bipolar input range. A write pulse (WR + CS) can either start an acquisition interval or initiate a combined acquisition plus conversion. The sampling interval occurs at the end of the acquisition interval.The ACQMOD bit in the input control byte offers two options for acquiring the signal: internal or external.The conversion period lasts for 12 clock cycles in either internal or external clock or acquisition mode.
Writing a new control byte during the conversion cycle will abort the conversion in progress and start a new acquisition interval.
Internal Acquisition
Select internal acquisition by writing the control byte with the ACQMOD bit cleared (ACQMOD = 0). This causes the write pulse to initiate an acquisition interval whose duration is internally timed. Conversion starts when this six-clock-cycle acquisition interval (3μs with f CLK = 2MHz) ends. See Figure 5.
External Acquisition
Use the external acquisition timing mode for precise con-trol of the sampling aperture and/or independent control of acquisition and conversion times. The user controls acqui-sition and start-of-conversion with two separate write puls-es. The first pulse, written with ACQMOD = 1, starts an acquisition interval of indeterminate length. The second write pulse, written with ACQMOD = 0, terminates acquisi-tion and starts conversion on WR’s rising edge (Figure 6).However, if the second control byte contains ACQMOD =1, an indefinite acquisition interval is restarted.
The address bits for the input mux must have the same values on the first and second write pulses. Power-down mode bits (PD0, PD1) can assume new values on the second write pulse (see Power-Down Mode ).Multi-Range (±4V , ±2V , +4V , +2V),
+5V Supply, 12-Bit DAS with 8+4 Bus Interface 10
______________________________________________________________________________________
分销商库存信息:
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