Xilinx UG388 Spartan-6 FPGA Memory Controller User Guide

Spartan-6 FPGA Memory Controller

User Guide

UG388 (v2.3) August 9, 2010

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Revision History

The following table shows the revision history for this document.

Date Version Revision

05/28/09 1.0Initial Xilinx release.

08/18/09 1.1?Removed references to MCB per-bit deskew calibration.

?Chapter1:

?Added XC6SLX75 and XC6SLX75T devices and CPG196, CSG484, and FG(G)900

packages to Table1-2, page13.

?Chapter2:

?In Figure2-2, page18, changed Configuration 5 to 128-bit bidirectional.

?Added note regarding board design requirements under Table2-9, page30.

?Chapter3:

?Updated first paragraph in Supported Memory Devices, page35.

?Added note to Clocking, page37.

?Added subsection Additional Board Design Requirements, page42.

?Chapter4:

?Moved Note 1 from Figure4-1, page46 to below the figure.

?Added Note 2 about calibration logic.

?Appendix A:

?Updated JEDEC specification links in Memory Standards, page65.

Spartan-6 FPGA Memory Controller https://www.sodocs.net/doc/4911949096.html, UG388 (v2.3) August 9, 2010

12/02/09 2.0?Moved Chapter 3, “Getting Started,” and Chapter 6, “Debugging MCB Designs,” and

to UG416, Spartan-6 FPGA Memory Interface Solutions User Guide.

?Changed introduction in About This Guide, page7.

?Chapter1:

?Revised Note 1 in Table1-1, page12 to refer to the data sheet for specific values.

?Added Note 2 to Table1-2, page13.

?Chapter2:

?In Table2-3, changed the description and values of the

C_MC_CALIBRATION_MODE attribute on page25.

?Appended two sentences to exception (a) on page30.

?Chapter3:

?Replaced text regarding the speed of the calibration clock, calib_clk, on page39.

?Chapter4:

?Rephrased Note 1 under Figure4-1, page46.

?In the third paragraph after the Notes on page46, removed the sentence about

calibration logic.

?Added note after first paragraph of Calibration, page47.

?Removed portion of sentence about calibration logic in first paragraph of Phase 2:

DQS Centering, page48.

?Added paragraph above Figure4-13, page59.

?Added note on page62 before Table4-5.

01/05/10 2.0.1Revised document hyperlinks.

03/04/10 2.1Chapter1: In the Features and Benefits section, added bullet for input termination

automatic calibration to section. In Table1-1, added parameters in Data Rate Minimum

column and updated table note 2. In Table1-2, revised table note 1.

Chapter2: In Table2-2, added “THREEQUARTERS” as a possible value for the Memory

Drive Strength attribute, and modified the description for Memory Burst Length

attribute, indicating that DDR3 is always set to 8. In the Clock, Reset, and Calibration

Signals section, added calibration to the heading name, introductory text, and caption of

Table2-4. In Table2-4, changed the signal name BUFPLL to BUFPLL_MCB, changed the

signal name sys_rst to async_rst, and added signals mcb_drp_clk and calib_done. In the

Memory Device Interface section, modified descriptive text related to RZG and ZIO pins.

Added clarifying text in Note (page30) relating to unused pins from an active MCB

reverting to general-purpose I/O. In Table2-9, modified descriptions for the rzq and zio

signals.

Chapter3: In Table3-1, removed memory devices MT41K128M8xx-25 and

MT41K256M4xx-25. In the Clocking section, added text related to MIG/EDK generation

of clocking infrastructure. Clarified text related to location of externally driven PLL.

Revised text related to calibration clock. In Figure3-3, changed signal name from

calib_clk to mcb_drp_clk. Changed the end of the first sentence after Figure3-3.

Changed the first sentence about the calibration related clock on page39. Under

Figure3-4, added clarifying text related to using bank1 MCB pins as BPI pins. In the

Additional Board Design Requirements section on page43, clarified requirements for

pull-down resistors on the RESET, CKE, and ODT signals. Added Simultaneous

Switching Output Considerations section.

Chapter4: In the Phase 1: Input Termination section, added clarifying text related to

input termination of the RZQ and ZIO pins. In the Addressing section, added clarifying

text related to offsetting the starting address location using the write data mask inputs.

Added the Read Latency and Suspend sections.

Appendix A: Updated JEDEC URLs.

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06/14/10 2.2XCN10024, MCB Performance and JTAG Revision Code for Spartan-6 LX16 and LX45 FPGAs,

addresses these changes:

Chapter1: Added an important note about Standard and Extended performance modes.

Chapter2: In Table2-4, included the BUFPLL_MCB block name in the pll_lock

description and changed the clock frequency example in the sysclk_2x description.

Chapter3: In Clocking, removed LOCKED and pll_lock from the PLL block and MIG

Wrapper blocks, respectively, and changed the clock frequency examples in the second

and fourth paragraphs under Figure3-3 on page38.

08/09/10 2.3Chapter1: In Table1-1, changed the minimum data rate value for LPDDR and indicated

that -3N speed-grade devices do not support the MCB in table note 1. Added table note

to Table1-3.

Chapter2: In Table2-4, added italicized sentence to the calib_done signal description. In

Table2-5, Table2-6, and Table2-7, added sentence about reset being required to recover

to the pX_cmd_error, pX_wr_error, and pX_rd_error descriptions, respectively.

Chapter3: Added BUFG in Figure3-3. Added sentences about preferred PLL location to

the end of the first paragraph under Figure3-3. Added sentences about driving MCBs

on both sides of the device to the end of the second paragraph under Figure3-3. Added

Modifying the Clock Setup section. Added fourth bullet about V REF to Additional Board

Design Requirements.

Chapter4: In the second to the last paragraph of Phase 1: Input Termination, replaced

sentence about V REF source still being provided for different I/O standards when a

calibrated input termination is desired with sentence about LPDDR memory not

requiring V REF. Added sentence about resulting input termination to the last paragraph

of Phase 1: Input Termination on page47.

Appendix A: Removed obsolete link.

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Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Preface: About This Guide

Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Additional Support Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Chapter 1: Memory Controller Block Overview

Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Features and Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Device Family Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Supported Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Software and Tool Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Chapter 2: MCB Functional Description

Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Port Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Selecting a Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Programmability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Interface Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

User (Fabric Side) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Clock, Reset, and Calibration Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Command Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Write Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Read Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Self-Refresh Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Memory Device Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Chapter 3: Designing with the MCB

Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

CORE Generator Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Supported Memory Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Modifying the Clock Setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table of Contents

Migration and Banking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

PCB Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

General Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Data, Data Mask, and Data Strobe Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Address, Control, and Clock Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Additional Board Design Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Simultaneous Switching Output Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Chapter4: MCB Operation

Startup Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Phase 1: Input Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Phase 2: DQS Centering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Phase 3: Continuous DQS Tuning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Command Path Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Write Path Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Read Path Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Memory Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Simple Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Simple Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Read Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Self Refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Suspend Mode without DRAM Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Suspend Mode with DRAM Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Additional Suspend Mode Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Byte Address to Memory Address Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Transaction Ordering and Coherency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Appendix A: References

Memory Standards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

PCB Layout and Signal Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

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UG388 (v2.3) August 9, 2010

Preface About This Guide

This document describes the Spartan?-6 FPGA memory controller block (MCB). Complete

and up-to-date documentation of the Spartan-6 family of FPGAs is available on the Xilinx

website at https://www.sodocs.net/doc/4911949096.html,/products/spartan6/index.htm.

To implement an MCB based memory interface, one of the two supported design tool

flows must be followed:

1.Memory Interface Generator (MIG)

For traditional (non-embedded) FPGA designs, refer to UG416, Spartan-6 FPGA

Memory Interface Solutions User Guide for information on implementing an MCB based

memory interface using the MIG tool within the CORE Generator? software. This

document also contains information on debugging MCB interfaces.

2.Embedded Development Kit (EDK)

For embedded designs, refer to DS643, Multi-Port Memory Controller (MPMC) for

details on how the MCB is used to implement the MPMC within the EDK

environment.

Guide Contents

This manual contains the following chapters:

?Chapter1, Memory Controller Block Overview, introduces the Spartan-6 FPGA MCB.

?Chapter2, MCB Functional Description, describes the architecture, signal interface,

and possible configurations of the MCB.

?Chapter3, Designing with the MCB, provides details on how to incorporate the MCB

into a Spartan-6 design, with specifics on how to customize the block for a given

application.

?Chapter4, MCB Operation, explains how the MCB functions in various operational

modes: startup, calibration, refresh, precharge, standard read/write transactions, etc.

?Appendix A, References, contains links to additional documentation relevant to

memory interface design.

Additional Documentation

The following documents are also available for download at

https://www.sodocs.net/doc/4911949096.html,/products/spartan6/index.htm.

?Spartan-6 Family Overview

This overview outlines the features and product selection of the Spartan-6 family. Spartan-6 FPGA Memory Controller https://www.sodocs.net/doc/4911949096.html,7 UG388 (v2.3) August 9, 2010

https://www.sodocs.net/doc/4911949096.html,

Spartan-6 FPGA Memory Controller

UG388 (v2.3) August 9, 2010

Preface:About This Guide

?Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

This data sheet contains the DC and Switching Characteristic specifications for the Spartan-6 family.

?Spartan-6 FPGA Packaging and Pinouts Product Specification

This specification includes the tables for device/package combinations and maximum I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and thermal specifications.

?Spartan-6 FPGA Configuration User Guide

This all-encompassing configuration guide includes chapters on configuration interfaces (serial and parallel), multi-bitstream management, bitstream encryption, boundary-scan and JTAG configuration, and reconfiguration techniques.

?Spartan-6 FPGA SelectIO Resources User Guide

This guide describes the SelectIO? resources available in all Spartan-6 devices.?

Spartan-6 F PGA

Clocking Resources User Guide

This guide describes the clocking resources available in all Spartan-6 devices, including the DCMs and the PLLs.

?Spartan-6 FPGA Block RAM Resources User Guide

This guide describes the Spartan-6 device block RAM capabilities.

?

Spartan-6 FPGA Configurable Logic Block User Guide

This guide describes the capabilities of the configurable logic blocks (CLBs) available in all Spartan-6 devices.

?Spartan-6 FPGA GTP Transceivers User Guide

This guide describes the GTP transceivers available in Spartan-6 LXT FPGAs.?

Spartan-6 FPGA DSP48A1 Slice User Guide

This guide describes the architecture of the DSP48A1 slice in Spartan-6 FPGAs and provides configuration examples.

?Spartan-6 FPGA PCB and Pin Planning Design Guide

This guide provides information on PCB design for Spartan-6 devices, with a focus on strategies for making design decisions at the PCB and interface level.

?Spartan-6 FPGA Power Management User Guide

This guide provides information on the various hardware methods of power management in Spartan-6 devices, primarily focusing on the suspend mode.

Additional Support Resources

To find additional documentation, see the Xilinx website at:

https://www.sodocs.net/doc/4911949096.html,/support/documentation/index.htm .

To search the Answer Database of silicon, software, and IP questions and answers, or to create a technical support WebCase, see the Xilinx website at:

https://www.sodocs.net/doc/4911949096.html,/support .

Chapter1 Memory Controller Block Overview

Scope

This chapter provides an overview of the Spartan?-6 FPGA memory controller block

(MCB). It contains these sections:

?Introduction

?Features and Benefits

?Block Diagram

?Performance

?Device Family Support

?Supported Memory Configurations

?Software and Tool Support

Introduction

The MCB is a dedicated embedded block multi-port memory controller that greatly

simplifies the task of interfacing Spartan-6 devices to the most popular memory standards.

The MCB provides significantly higher performance, reduced power consumption, and

faster development times than equivalent IP implementations. The embedded block

implementation of the MCB conserves valuable FPGA resources and allows the user to

focus on the more unique features of the FPGA design.

Features and Benefits

The key features and benefits of the Spartan-6 FPGA memory controller block are:

?DDR, DDR2, DDR3, and LPDDR (Mobile DDR) memory standards support

?Up to 800Mb/s (400MHz double data rate) performance

?Up to four MCB cores in a single Spartan-6 device. Each MCB core supports:

?4-bit, 8-bit, or 16-bit single component memory interface

?Memory densities up to 4Gb

?Up to 12.8Gb/s aggregate bandwidth

?Configurable dedicated multi-port user interface to FPGA logic

? 1 to 6 ports per MCB depending on configuration

?32-, 64-, or 128-bit data bus options

?Bidirectional (R/W) or unidirectional (W only or R only) port options

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Chapter 1:Memory Controller Block Overview

?Memory Bank Management

?Up to eight memory banks open simultaneously for greater controller efficiency ?Embedded controller and physical interface (PHY), providing:

?Predictable timing

?Low power

?Guaranteed performance

?Predefined pinouts (I/O locations) for each MCB

?Simplified board design

?Predefined I/Os not used in an MCB interface become general-purpose I/Os (see

page30 for details).

?Common memory device options and attributes support

?Programmable drive strength

?On-Die Termination (ODT)

?CAS latency

?Self refresh (including partial array)

?Refresh interval

?Write recovery time

?Automatic delay calibration of memory strobe and read data inputs

?Adjusts DQS (strobe) to DQ (data) timing relationship for optimal read

performance

?Optional automatic calibration of FPGA on-chip input termination for optimal signal

integrity

?Supported by Xilinx? CORE Generator? and Embedded Development Kit (EDK)

design tools

?Memory Interface Generator (MIG) tool within the CORE Generator software

simplifies the MCB design flow

?Embedded designs can also access the MCB via the multi-port memory controller

(MPMC) IP in the EDK tool

Block Diagram

The block diagram in Figure1-1 shows the major architectural components of the MCB

core. Throughout this document, the MCB is described as provided to the user by the

memory IP tools within the CORE Generator software or EDK environment. These tools

typically produce top-level “wrapper” files that incorporate the embedded block memory

controller primitive and any necessary soft logic and port mapping required to deliver the

complete solution. For example, in Figure1-1, the physical interface of the MCB uses the

capabilities of the general I/O block (IOB) to implement the external interface to the

memory. General I/O clock network resources are also used.

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Block Diagram

Figure 1-1:Spartan-6 FPGA Memory Controller Block (IP Wrapper View)

The single data rate (SDR) user interface to the MCB inside the FPGA can be configured for

one to six ports, with each port consisting of a command interface and a read and/or write

data interface. The two 32-bit bidirectional and four 32-bit unidirectional hardware-based

ports inside the MCB can be grouped to create five different port configurations.

Other major components of the MCB include:

?Arbiter

Determines which port currently has priority for accessing the memory device.

?Controller

Primary control block that converts the simple requests made at the user interface into

the necessary instructions and sequences required to communicate with the memory.

?Datapath

Handles the flow of write and read data between the memory device and the user

logic.

?Physical Interface (PHY)

Converts the controller instructions into the actual timing relationships and DDR

signaling necessary to communicate with the memory device.

?Calibration Logic

Calibrates the PHY for optimal performance and reliability.

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Chapter 1:Memory Controller Block Overview

Performance

The dedicated MCB cores in Spartan-6 devices enable significantly higher performance levels than equivalent IP solutions implemented in the FPGA logic. Because memory bandwidth is often the bottleneck in overall system performance, the MCB cores were specifically engineered for users looking to maximize memory performance in a low-cost, low-power FPGA device.

Each MCB core supports the memory interface data rates and total memory bandwidth specifications shown in Table 1-1. Peak bandwidth for a single MCB memory interface is calculated for the three supported interface widths.

Note:The MCB supports Standard and Extended performance modes depending on the selected

V CCINT operating conditions. Peak data rates shown in T able 1-1 represent maximum performance when using the V CCINT range in Extended performance mode. Refer to T able 2 (Recommended Operating Conditions) and the Performance Characteristics section in DS162, Spartan-6 FPGA Data Sheet: DC and Switching Characteristics for V CCINT operating conditions and performance specifications for Standard and Extended modes.

Table 1-1:Memory Interface Data Rates and Peak Bandwidth for Each MCB

Memory Type

Data Rate:

Mb/s DDR (MHz Clock)Peak Bandwidth per MCB Interface (Gb/s)

Minimum

Maximum (1)4-Bit 8-Bit 16-Bit DDR 167 Mb/s (2)(83.3MHz)400 Mb/s (200MHz) 1.6Gb/s 3.2Gb/s 6.4Gb/s DDR2250Mb/s (2)(125MHz)800Mb/s (400MHz) 3.2Gb/s 6.4Gb/s 12.8Gb/s DDR3606Mb/s (2)(303MHz)800Mb/s (400MHz) 3.2Gb/s 6.4Gb/s 12.8Gb/s LPDDR

60Mb/s (2)(30MHz)

400Mb/s (200MHz)

1.6Gb/s

3.2Gb/s

6.4Gb/s

Notes:

1.The maximum MCB data rate shown does not apply to all speed grades. Refer to DS162, Spartan-6 FPGA Data Sheet: DC and Switching Characteristics , for performance by speed grade. The -3N speed-grade devices do not support the MCB.

2.The minimum frequency requirement of the MCB is dictated by the minimum frequency specification for the memory standard. See Memory Standards in Appendix A for links to the relevant JEDEC specifications.

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Device Family Support

Device Family Support

The number of MCBs available in a given Spartan-6 device is determined by the density range that the device falls within. The smallest device (XC6SLX4) contains no MCBs, mid-range density devices contain two MCBs, and the largest devices contain four MCBs. Table 1-2 shows the number of MCBs supported in each device/package combination.Note:The MCB is designed to interface to a single x4, x8, or x16 memory component. Multiple

component interfaces to a single MCB (for example, two x8 memories interfacing to an MCB in x16mode) are not supported.

Table 1-2:

MCB Support by Device / Package Combination

Device Package

TQG144

CPG196

CSG225

FT(G)256

CSG324FG(G)484CSG484FG(G)676FG(G)900

XC6SLX4000XC6SLX9

02(1)22XC6SLX160

2(1)

22XC6SLX252

22XC6SLX452

222XC6SLX752(2)2(2)4XC6SLX1002(2)2(2)4XC6SLX1502(2)

2(2)

4

4

XC6SLX25T 22XC6SLX45T 2

22XC6SLX75T 2(2)2(2)4XC6SLX100T 2(2)2(2)44XC6SLX150T

2(2)

2(2)

4

4

Notes:

1.For devices in the CSG225 package, the MCBs support only the x4 and x8 memory interface width options, meaning LPDDR devices cannot be supported. In addition, there are only 13 MCB address bits available in this package, which limits the maximum memory density to 256Mb for DDR2 and 512Mb for DDR and DDR3.

2.For devices with four MCBs, only two MCBs are bonded out in the FGG484 and CSG484 packages.

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Chapter 1:Memory Controller Block Overview

Supported Memory Configurations

The Spartan-6 FPGA MCB supports a wide range of common memory types, configurations, and densities, as shown in Table 1-3.Software and Tool Support

The Spartan-6 FPGA MCB is supported by standard software and tool flows like other soft and embedded IP blocks offered by Xilinx. For conventional (i.e., non-embedded) FPGA designs, the MCB can be integrated into a design using the Memory Interface Generator (MIG) tool, available in the CORE Generator tool.

The MIG tool is used to generate memory interfaces for all Xilinx FPGAs. It produces the necessary RTL design files, user constraints files (UCFs), and script files for simulation and implementation of memory solutions offered by Xilinx. The Getting Started chapter in UG416, Spartan-6 FPGA Memory Interface Solutions User Guide , contains detailed

step-by-step instructions on how to use the MIG tool to implement memory interfaces based on the MCB.

For embedded designs (e.g., MicroBlaze? processor designs), the IP configurator GUI found in the Xilinx Platform Studio tool within the EDK environment can be used to

specify the memory interface characteristics. In this flow, the MCB serves as the underlying hardware implementation of the MPMC IP block, available in the EDK library. In addition to setting up the controller and memory attributes, the tool generates the necessary soft bridges to the PLB bus, Xilinx Cache Link (XCL), LocalLink (LL), or other specified interface for connecting EDK peripherals to the resulting memory controller ports.

Table 1-3:

Supported Memory Configurations

Memory Density

Width (# DQ bits)

Memory Type

LPDDR DDR DDR2

DDR3

128Mb

x16X

X x8X x4

X

256Mb

x16X

X X x8X X x4

X

X 512Mb

x16X

X X X x8X X X x4

X

X X 1

Gb x16X

X X X x8X X X x4

X

X X 2 Gb

x16X X x8X X x4

X

X 4 Gb (1)

x16

X

Notes:

1.The MCB supports single-die, 4Gb memory components (when available from memory suppliers) but not dual-die, 4Gb memory components.

Chapter2 MCB Functional Description

This chapter provides a detailed functional description of the Spartan?-6 FPGA MCB. It

contains the following sections:

?Architecture Overview

?Port Configurations

?Arbitration

?Programmability

?Interface Details

Architecture Overview

The MCB provides a simple, reliable means of interfacing to a single component memory

device. The MCB User Interface removes the complexities of DDR memory interfacing so

that more engineering resources can be directed to the unique aspects of the FPGA design.

The MCB can operate at speeds considerably faster than a comparable “soft” solution

implemented in the FPGA logic. With data rates up to 800Mb/s, the MCB more than

doubles the performance of prior generation low-cost FPGA memory interface solutions,

allowing higher levels of bandwidth and/or narrower memory buses. This provides the

significant benefit of conserving valuable FPGA logic and I/O resources that are otherwise

required to communicate with the memory device.

Figure2-1 expands on the MCB block diagram introduced in Chapter1 to show the major

signals associated with the User Interface internal to the FPGA as well as the I/O signals

connected to the external memory device. While the User Interface can be configured to

support up to six ports, for simplicity, Figure2-1 shows only the signals for a single

bidirectional port.

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Chapter 2:MCB Functional Description

Figure 2-1:MCB Architecture with Major Internal and I/O Signals

There are three basic types of ports that can be established at the User Interface:

?Read port (unidirectional)

?Write port (unidirectional)

?Read and Write port (bidirectional)

Each port contains a command path and a datapath. For a unidirectional port, a command

path is paired with a single read-only or a single write-only datapath. However, for a

bidirectional port, a single command path is shared by both the read and write datapaths

associated with that port. FIFOs are used at the User Interface of the command path and

datapath to queue up memory requests and to manage the transfer from the user clock

domain to the memory controller clock domain.

The command path signals for a port are used to issue requests to the command FIFOs. The

command FIFOs have a user-programmable depth up to four. They store the instruction

type (read, write, refresh, etc.), address, and burst length associated with a requested

memory transaction. The command path also includes full and empty status flag outputs

from the command FIFOs, indicating whether new requests can be accepted. There are six

command FIFOs available in hardware; the port configuration determines how many are

accessible to the User Interface (see Port Configurations). For more details on the

command path signals, refer to Interface Details, page25.

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Port Configurations In the datapath, the underlying hardware contains six 32-bit ports, two of which are

inherently bidirectional. The other four ports are inherently unidirectional but can be

combined to create bidirectional ports as well. There are five possible port configurations

that combine these six hardware ports to implement the desired User Interface (see Port

Configurations). The width of the read and write data word fields of the User Interface are

naturally determined by the chosen configuration.

The datapath FIFOs are 64 deep, allowing for burst lengths of up to 64 data words from a

given start address. In addition to the data word field, the write path FIFOs contain mask

bit fields that allow optional masking of write data on a per byte basis. Full, empty,

underrun, count, and error outputs indicate the current status of the write data FIFOs. The

read data FIFOs have a similar set of status outputs. For more details on the read and write

datapath signals, refer to Interface Details, page25.

The arbiter inside the MCB uses a time slot based arbitration mechanism to determine

which of the one to six ports of the User Interface currently has access to the memory. There

are also methods for allowing some ports greater priority, and thus frequent access to the

memory, as discussed in Arbitration.

Bank management logic in the MCB allows up to eight memory banks to be open

simultaneously, allowing the controller to maintain high efficiency levels when accessing

data spread across multiple banks. In addition, read and write requests to the memory can

include an optional auto-precharge to automatically close a bank upon completion of the

transaction to improve the efficiency of random data accesses within a bank. The MCB

does not perform any reordering of transactions.

Port Configurations

The five possible port configurations for the User Interface are shown in Figure2-2. In

Configuration 1, the user ports essentially map directly to the underlying six physical

hardware ports. For the other configurations, the diagram shows how the physical ports

are concatenated to create different user port combinations. As shown in Figure2-2, the

MIG tool always sequentially numbers ports for the User Interface starting from 0,

regardless of the underlying physical port numbers.

In all five port configurations, the command path, write datapath, and read datapath

within a given port all have separate clocks and therefore can be connected to independent

clock domains. However, it is recommended that all paths related to a given port be kept

on a single clock domain to simplify the interface requirements.

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Chapter 2:MCB Functional Description

Figure 2-2:Possible Port Configurations for the User Interface

Selecting a Port Configuration

The MIG tool in the CORE Generator? tool provides a simple graphical interface for

setting up the number and type of ports required for a specific application. For designs that

require less than the full width or functionality of the User Interface, unused ports can

simply be disabled through the MIG interface. In the event that additional ports are

required beyond the six ports provided in the MCB, port bridges with additional

arbitration mechanisms can be implemented in the FPGA logic to expand the MCB port

capabilities.

Arbitration

The arbiter inside the MCB uses a time slot based arbitration mechanism to determine

which port of the User Interface currently has access to the memory. There are 12 time slots

in the arbitration table as shown in Table2-1. Each time slot corresponds to a single

memory clock cycle. The order of port priority in a given time slot is determined by the

port numbers entered into the Priority 1 through 6 columns moving from left to right

across the table.

Table2-1 shows the case where the User Interface is configured for the maximum six ports.

If the MCB is configured to have fewer than six ports, the arbitration table automatically

adjusts to have priority columns only for the selected number of ports.

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Arbitration

Table 2-1:MCB Arbitration Table with Round Robin Configuration

Time Slot Priority 1Priority 2Priority 3Priority 4Priority 5Priority 6

0012345

1123450

2234501

3345012

4450123

5501234

6012345

7123450

8234501

9345012

10450123

11501234

During a given clock cycle, the arbiter determines which port to service in that time slot. It

moves left to right across the priority columns to find the first port in that row that has a

command pending in its command FIFO. That port is then serviced with execution of the

pending command, and the arbiter moves on to the next time slot on the following clock

cycle. If no port has a command pending for that row, no action occurs for that time slot

and a clock cycle is lost.

The order of port priorities in the arbitration table is fully programmable. The MIG tool

provides a default round-robin scheme as illustrated in Table2-1, where all ports are given

the highest priority in 2 of the 12 available time slots. However, the MIG tool also provides

a custom option where the user can define any arbitration table. This allows for some ports

to be given greater overall access to the memory device. However, care should be exercised

when using this option to ensure that the assigned priorities do not prevent any active

ports from receiving access to the memory device.

It is possible to configure the User Interface to have five ports (two 32-bit bidirectional

ports and three 32-bit unidirectional ports, with one 32-bit unidirectional port disabled). In

this case, the arbitration table is reduced to 10 time slots. When the number of time slots is

evenly divisible by the number of ports, each port is ensured to receive equal access to the

memory device, if desired.

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Chapter 2:MCB Functional Description

Programmability

The MCB is highly configurable through a set of memory device and controller attributes, allowing it to support multiple memory standards and configurations. The MIG tool

within the CORE Generator tool and the IP Configurator in the Xilinx Platform Studio tool within the EDK environment provide a simple means of configuring the MCB attributes to implement the desired memory interface (for example, see the “Getting Started” chapter in UG416, Spartan-6 FPGA Memory Interface Solutions User Guide ).

Table 2-2 and Table 2-3 list the memory device and controller attributes, respectively, supported by the MCB. The specific HDL parameter names, possible values, and

descriptions associated with each of the attributes are provided. In general, the MIG tool or IP Configurator tools are responsible for setting all parameter values, so the values should not be modified directly.

Memory timing parameters are taken from the vendor data sheets, and are automatically assigned by the tools when a supported device is selected. Timing parameters can be specified when creating a custom device (see the “Setting Controller Options” section in the Spartan-6 FPGA Memory Interface Solutions User Guide ).

Table 2-2:

Memory Device Attributes

Memory Attributes Parameter Name(s)Description / Possible Values

Memory Type

C_MEM_TYPE

This attribute sets the memory standard implemented by the MCB.

Possible values: DDR, DDR2, DDR3, LPDDR.

Memory Data Bus Width C_NUM_DQ_PINS This attribute sets the bit width of the DQ bus. Possible values: “4“, “8“, “16“.

Memory Address Bus Width

C_MEM_ADDR_WIDTH

This attribute sets the memory address bus width (the total number of address bits).Possible values: Based on device selection in the MIG tool.

Memory Bank Address Bus Width

C_MEM_BANKADDR_WIDTH

This attribute sets the number of bank address bits.

Possible values: Based on device selection in the MIG tool.

Memory Column Address Bus Width

C_MEM_NUM_COL_BITS

This attribute sets the number of column address bits.

Possible values: Based on device selection in the MIG tool.

Memory Burst Length

C_MEM_BURST_LEN

This attribute sets the memory burst length to be used. The MIG tool determines the value based on the memory standard, port

configuration, and interface width. DDR3 will always be set to 8.Possible values: “4“, “8“.