SPC-XRDSC-G12864A5DYLYSD-1(A)-A0
欣瑞达电子
X.R.D ELECTRONIC CO.，LTD SPECIFICATIONS FOR LCD
MODULE
CUSTOMER MODEL XRDSC-G12864A5DYLYSD-1(A)
CUSTOMER
APPROVED
APPROVED BY CHECKED BY ORGANIZED BY
地址：深圳市宝安区石岩镇水田长城路鼎丰科技园E栋2-3楼
电话：0755－27622354 27622834
传真：0755－27622832
Specification Revision History
Version Content Date
Issue 5-Jan-10 A0 First
CONTENTS
MODULE CLASSIFICATION INFORMATION PHYSICAL DATA
MECHANICAL DIMENSIONS
BLOCK DIAGRAM
INTERFACE PIN CONNECTIONS
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
BACKLIGHT
OPTICAL CHARACTERISTICS
OPERATING PRINCIPLES & METHODS
DISPLAY DATA RAM ADDRESS MAP
POWER SUPPLY FOR LCM MODULE
EXAMPLE
RELIABILITY
INSPECTION CRITERIA
PRECAUTIONS FOR USING LCD MODULES USING LCD MODULES
MODULE CLASSIFICATION INFORMATION
PHYSICAL DATA
V ALUE
UNIT ITEM STANDARD
NUMBER OF GRAPHIC 128×64 mm
MODULE DIMENSION 93.0×70.0×14.0(MAX) mm
EFFECTIVE DISPLAY AREA 71.7×39.0 mm
DOT SIZE 0.48×0.48 mm
DOT PITCH 0.52×0.52 mm
LCD TYPE STN/YELLOW-GREEN
DUTY 1/64
VIEWING DIRECTION 6 o’clock
BACK LIGHT TYPE BOTTOM LIT LED
BACK LIGHT COLOR YELLOW-GREEN
APPROX. WEIGHT 85 g
MECHANICAL DIMENSIONS
BLOCK DIAGRAM
LED(+)LED(-)
VOUT V0VDD VSS CS1
CS2/RST RS,R/W,E
D0~D7
INTERFACE PIN CONNECTIONS
NO SYMBOL LEVEL FUNCTION
1 VSS 0V Ground
2 VDD +5.0V Supply voltage for logic
3 V0 --- Input voltage for LCD
4 RS H/L
Register selection input
H : Data signal, L : Instruction signal 5 R/W H/L
Read/write selection input
H : Read mode, L : Write mode 6 E H, H → L Read/write enable signal.
H: Read data/instruction
H → L: Write data/instruction
7 DB0 H/L 8 DB1 H/L 9 DB2 H/L 10 DB3 H/L
11 DB4 H/L 12 DB5 H/L 13 DB6 H/L 14 DB7 H/L Data bus 0-7
15 CS1 H Chip select signal, CS1=H chip is active 16 CS2 H Chip select signal, CS2=H chip is active
17 /RST L Reset signal. When RSTB=L,
- ON / OFF register becomes set by 0. (display off)
- Display start line register becomes set by 0 (Z-address 0 set, display from line 0)
After releasing reset, this condition can be changed only by instruction.
18 VOUT -10V Output voltage for LCD 19 LED(+) +4.2V Back light anode 20 LED(-) 0V Back light cathode
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL MIN
MAX UNIT
Supply voltage for logic
VDD -0.3 7.0 V Supply voltage for LCD V0 VDD-19.0 VDD+0.3 V Input voltage
VI -0.3 VDD+0.3 V Operating temperature TOP -20 +70 °C Storage temperature
TST -30 +80 °C
ELECTRICAL CHARACTERISTICS
u DC Characteristics
Condition: VDD=+5.0V±10%, VSS=0V , VDD-V0=8 to 17V , Ta=-30 to +85℃
PARAMETER SYMBOL CONDITION
MIN TYP MAX UNIT
Supply voltage for logic VDD ---- 4.5 5.0 5.5 V
Supply current for logic IDD ---- 2.0 2.4 2.8 mA Operating voltage for LCD VDD-V0 ---- 9.2 9.6 10.0 V Input voltage ' H ' level V IH ---- 2.0 ---- VDD V Input voltage ' L ' level V IL ---- 0 ---- 0.8 V output voltage ' H ' level V OH I OH =-200μA 2.4 ---- ---- V output voltage ' L ' level
V OL I OL = 1.6mA ---- ---- 0.4 V
u AC Characteristics
Write mode (refer to Figure-3) : VDD=+5.0V±10%, VSS=0V , Ta=-30 to +85℃
PARAMETER SYMBOL MIN TYP MAX UNIT
E cycle time
t C 1000 ---- ---- ns
E high level width t WH 450 ns E low level width t WL 450 ns E rise time t R 25 ns E fall time
t F 25 ns Address set-up time t ASU 140 ---- ---- ns Address hold time t AH 10 ---- ---- ns Data set-up time t DSU 200 ---- ---- ns Data hold time
t DHW 10 ns
Read mode (refer to Figure-4) : VDD=+5.0V±10%, VSS=0V , Ta=-30 to +85℃
PARAMETER SYMBOL MIN TYP MAX UNIT
E cycle time
t C 1000 ---- ---- ns E high level width t WH 450 ns E low level width t WL 450 ns E rise time t R 25 ns E fall time
t F 25 ns Address set-up time t ASU 140 ---- ---- ns Address hold time t AH 10 ---- ---- ns Data set-up time t DSU 200 ---- ---- ns Data delay time t D ---- ---- 320 ns Data hold time
t DHR 20 ns
BACKLIGHT
u Backlight Type
Backlight Type: LED(YELLOW-GREEN) u Power Supply For Backlight LED Chip 2*36=72
dies
u Absolute Maximum Rating
PARAMETER SYMBOL
CONDITION MAX UNIT
Absolute maximum forward current Ifm 720 mA Peak forward current Ifp 1 MSEC plus 10% Duty Cycle 2160 mA Reverse voltage V R 7.0 V Life Hour If(forward current) =360mA 80000 H
Note: For operation above 25℃,Then Ifm Ifp must be decreased, the Current decreased is -1.08mA/℃ for
DC drive and -2.58mA/℃ Pulse drive, the power dissipation is -4.5mＷ/℃.The product working current must not more than the 70% of the Ifm or Ifp according to the working temperature.
u Electrical-Optical Characteristics
PARAMETER SYMBOL
CONDITION MIN TYP MAX UNIT
Forward voltage Vf
(LED(+)-LED(-))
----
4.1 4.3 V Forward current If ----
175 200 mA Reverse current Ir VR =
7.0V ---- ---- 3600 μA Wavelength λp If(forward current) = 360mA 570 572 575 Luminance
Lv If(forward current) = 200mA 16 cd /㎡
Note:The Master Screen’s luminance is
the average value of 5 points,and The Lvmin./Lvmax. is not less than 70%. The measurement instrument is BM-7 luminance Colorimeter. The aperture is Φ5 mm.
OPTICAL CHARACTERISTICS
Test instrument is LCD-5000,made in Japan
Item Symbol Condition Min Typ Max Unit Remarks Note
Operating voltage V op 25℃
8.8 9.0 9.2 V --- --- Tr ---- ---- 128 400 ms --- 1
Response time
Td ---- ---- 143 400 ms --- 1
Contrast ratio Cr ---- ---- 24 ---- --- --- 2
---- 60 ---- deg ?=0° 3 Viewing angle
range θ
Cr ≥6 ---- 28 ---- deg ?=180° 3
u Definition Of Viewing Angle
Note1: Definition of response time
Note2: Definition of contrast ratio ‘Cr’ Note3: Definition of viewing angle range ‘θ’
Note4:Measuring Instruments For Electro-optical Characteristics
*1.Light source position for measuring the reflective type of LCD panel
*2.Light source position for measuring the transflective / transmissive types of LCD pane l
OPERATING PRINCIPLES & METHODS u Control And Display Command
Command R
S
R
/
W
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
Function
Display ON/OFF 0 0 0 0 1 11110/1 Controls the display on or off. Internal status and display RAM data are not affected.
0:OFF, 1:ON
Set
Address 0 0 0 1 Y address (0～63) Sets the Y address in the Y address counter.
Set Page (X address) 0 0 1 0 1 11
Page
(0～7)
Sets the X address at the X address
register.
Display
Start
Line 0 0 1 1 Display start line
(0～63)
Indicates the display data RAM
displayed at the top of the screen.
Status Read 0 1 B
U
S
Y
O
N
/
O
F
F
R
E
S
E
T
0000
Read status
0 : Ready
BUSY
1 : In operation
0 : ON
Display
ON/OFF 1 :Display
OFF
0 : Normal
RESET
1 : Reset
Write Display Data 1 0 Write Data Writes data (DB0:7) into display data RAM. After writing instruction, Y address is increased by 1 automatically.
Read Display Data 1 1 Read Data Reads data (DB0:7) from display data RAM to the data bus.
u I/O Buffer
Input buffer controls the status between the enable and disable of chip. Unless the CS1 or CS2 is in active mode, input or output of data and instruction do not execute. Therefore internal state is not
changed. But RSTB can operate regardless of CS1 and CS2.
u Input Register
Input register is provided to interface with MPU which is different operating frequency. Input register stores the data temporarily before writing it into display data RAM.
When CS1 or CS2 is in the active mode, R/W and RS select the input register. The data from MPU is written into input register and then write it into display data RAM. Data is latched when falling of the E signal and written automatically into the display data RAM by internal operation.
u Output Register
Output register stores the data temporarily from display data RAM when CS1 or CS2 is in active mode and R/W and RS=H. Stored data in display data RAM is latched in output register. When CS1 or CS2 is in active mode and R/W=H, RS=L, status data (busy check)can be read out.
To read the contents of display data RAM, twice access of read instruction is needed. In first access, data in display data RAM is latched into output register. In second access, MPU can read data which is latched. That is, to read the data in display data RAM, it needs dummy read. But status read does not need dummy read.
RS R/W Function
0 Instruction
1 Status read(busy cheek) 0 Data write(from input register to display data RAM
1
1 Data read(from display data RAM to output register)
u Reset
System reset can be initialized by setting RSTB terminal at low level when turning power on,
receiving instruction from MPU. When RSTB becomes low, following procedure is occurred. - Display off - Display start line register become set by 0.(Z-address 0)
While RSTB is low level, no instruction except status read can be accepted. Reset status appears at DB4. After DB4 is low, any instruction can be accepted. The Conditions of power supply at initial power up are shown in table 1.
Table 1. Power Supply Initial Conditions
Item Symbol Min Typ Max Unit Reset time tRST 1.0 --- --- us Rise time tr --- --- 200
ns
u Busy Flag
Busy flag indicates that KS0108B is operating or not operating. When busy flag is high, KS0108B is in internal operating. When busy flag is low, KS0108B can accept the data or instruction. DB7 indicates busy flag of the KS0108B.
u Display ON/OFF Flip-Flop
The display on/off flip-flop makes on/off of the liquid crystal display. When flip-flop is reset (logical low). selective voltage or non selective voltage appears on segment output terminals. When flip-flop is set (logical high).non selective voltage appears on segment output terminals regardless of display RAM data.
The display on/off flip-flop can change status by instruction. The display data at all segment disappear while RSTB is low. The status of the flip-flop is output to DB5 by read instruction.
V DD
RSTB E Busy
u X Page Register
X page register designates page of the internal display data RAM. It has not count function. An address is set by instruction.
u Y Address Counter
Y address counter designates address of the internal display data RAM. An address is set by instruction and is increased by 1 automatically by read or write operations of display data.
u Display Data RAM
Display data RAM stores a display data for liquid crystal display. To express on state of dot matrix of liquid crystal display. write data 1. The other way. off state writes 0.
u Display Start Line Register
The display start line register indicates address of display data RAM to display top line of liquid
crystal display. Bit data (DB<0:5>) of the display start line set instruction is latched in display start line register. It is used for scrolling of the liquid crystal display screen
u Contents
(1) Display ON/OFF
RS R/W D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 1 1 1 1 1 D
The display data appears when D is 1 and disappears when D is 0. Though the data is not on the
screen with D =0, it remains in the display data RAM. Therefore, you can make it appear by
changing D = 0 into D = 1.
(2) Set Address(Y Address)
RS R/W D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0
Y address (AC0 - AC5) of the display data RAM is set in the Y address counter. An address is set
by instruction and increased by 1 automatically by read or write operations of display data.
(3) Set Page(X Address)
RS R/W D7 D6 D5 D4 D3 D2 D1 D0
AC0
0 0 1 0 1 1 1 AC2
AC1 X address(AC0 - AC2) of the display data RAM is set in the X address register. Writing or
reading to or from MPU is executed in this specified page until the next page is set.
(4) Display Start Line (Z Address)
RS R/W D7 D6 D5 D4 D3 D2 D1 D0
0 0 1 1 AC5 AC4 AC3 AC2 AC1 AC0
Z address (AC0 - AC5) of the display data RAM is set in the display start line register and
displayed at the top of the screen. When the display duty cycle is 1/64 or others(1/32 - 1/64),
the data of total line number of LCD screen, from the line specified by display start line
instruction, is displayed.
(5) Status Read
RS R/W D7 D6 D5 D4 D3 D2 D1 D0
RESET0 0 0 0
ON/OFF
0 1 BUSY
BUSY
When BUSY is 1, the Chip is executing internal operation and no instructions are accepted.
When BUSY is 0, the Chip is ready to accept any instructions.
ON/OFF
When ON/OFF is 1, the display is OFF.
When ON/OFF is 0, the display is ON.
RESET
When RESET is 1, the system is being initialized.
In this condition, no instructions except status read can be accepted.
When RESET is 0, initializing has finished and the system is in the usual operation condition.
(6) Write Display Data
RS R/W D7 D6 D5 D4 D3 D2 D1 D0
1 0 D7 D6 D5 D4 D3 D
2 D1 D0 Writes data (D0 - D7) into the display data RAM. After writing instruction, Y address is increased by 1 automatically.
(7) Read Display Data
RS R/W D7 D6 D5 D4 D3 D2 D1 D0
1 1 D7 D6 D5 D4 D3 D
2 D1 D0 Reads data (D0 - D7) from the display data RAM. After reading instruction, Y address is increased by 1 automatically.
DISPLAY DATA RAM ADDRESS MAP
P AGE
ADDRESS
DISPLA Y
DA T A
CS1
=H CS2=H
LINE ADDRESS COM
MON
D0 C0 0 D1 C1 1 D2 C2 2 D3 C3 3 D4 C4 4 D5 C5 5 D6 C6 6 B8
D7 C7 7 D0 C8 8 D1 C9 9 D2 CA 10 D3 CB 11 D4 CC 12 D5 CD 13 D6 CE 14 B9
D7
CF 15
. . . . . .
. . . .
.
.
. . . . . . . . . . . . D0 F0 48 D1 F1 49
D2 F2 50
D3 F3 51 D4 F4 52 D5 F5 53 D6 F6 54 BE
D7 F7 55 D0 F8 56 D1 F9 57 D2 FA 58 D3 FB 59 D4 FC 60 D5 FD 61 D6 FE 62 BF
D7 FF 63
C O L U M N A
D D R
E S S 40 41 42 43 44 45 46
……
7F
40
……
7F
S E G M E N T
S E G 0 S E G 1 S E G 2 S E G 3 S E G 4 S E G 5 S E G 6
……
S E G 63 S E G 64 S E G 127
POWER SUPPLY FOR LCM MODULE
D D-V0=9.6V
V
EXAMPLE
u Application Circuit
u Programme
TRS EQU P3.6
TRW EQU P3.5
TE EQU P3.4
TCS1 EQU P3.1
TCS2 EQU P3.0
TRES EQU P3.7
ORG 0000H
AJMP MAIN
ORG 0003H
LJMP INNT
ORG 0100H
MAIN:MOV SP,#60H
MOV IE,#81H
MOV IP,#01H
MOV TCON,#00H
LCALL initialize
LCALL DIS0
LCALL DIS1 LCALL DIS2
LCALL DIS3
LCALL DIS4
LCALL DIS5
LCALL DIS6
LCALL DIS8
AJMP MAIN
initialize: SETB TRES
LCALL DELY1
CLR TRES
LCALL DELY1
TT:LCALL RCMD1
JB ACC.7,TT
JNB ACC.4,initialize
TT1:LCALL RCMD2
JB ACC.7,TT1
JNB ACC.4,initialize SETB TRES
LCALL DELY1
TT2:LCALL RCMD1
JB ACC.7,TT
JB ACC.4,initialize
TT3:LCALL RCMD2
JB ACC.7,TT3
JB ACC.4,initialize
MOV A,#3FH
LCALL WCMD1
LCALL WCMD2
MOV A,#0C0H
LCALL WCMD1
LCALL WCMD2
MOV A,#0B8H LCALL WCMD1 LCALL WCMD2 MOV A,#040H LCALL WCMD1 LCALL WCMD2 RET DIS0:MOV A,#0C0H ;"*" LCALL WCMD1 LCALL WCMD2 MOV R0,#0B8H D00:MOV A,R0 LCALL WCMD1 LCALL WCMD2 MOV A,#40H LCALL WCMD1 LCALL WCMD2 MOV
R7,#40H MOV A,#55H D01:LCALL WDAT1 LCALL WDAT2 CPL A DJNZ R7,D01 INC R0 CJNE R0,#0C0H,D00 RET DIS1:MOV A,#0C0H ;"*" LCALL WCMD1 LCALL WCMD2 MOV R0,#0B8H D10:MOV A,R0 LCALL WCMD1 LCALL WCMD2 MOV A,#40H LCALL
WCMD1 LCALL WCMD2 MOV R7,#40H MOV A,#55H D11:LCALL WDAT1 LCALL WDAT2 CPL A DJNZ R7,D11 INC R0 CJNE R0,#0C0H,D10 LCALL DELY2 RET DIS2:MOV DPTR,#M0 MOV A,#0C0H LCALL WCMD1 LCALL WCMD2 MOV R0,#0B8H C20:MOV A,R0 LCALL WCMD1 LCALL WCMD2 MOV A,#40H LCALL WCMD1 MOV R7,#40H C21:MOV A,#00H MOVC A,@A+DPTR LCALL WDAT1 INC DPTR DJNZ R7,C21 MOV A,#40H LCALL WCMD2 MOV R7,#40H C22:MOV A,#00H MOVC A,@A+DPTR LCALL WDAT2 INC DPTR DJNZ R7,C22 INC R0 CJNE R0,#0C0H,C20 LCALL DELY2 RET DIS3:MOV DPTR,#M1 MOV A,#0C0H LCALL WCMD1 LCALL WCMD2 MOV R0,#0B8H C30:MOV A,R0 LCALL WCMD1 LCALL WCMD2 MOV A,#40H LCALL WCMD1 MOV R7,#40H C31:MOV A,#00H MOVC A,@A+DPTR LCALL WDAT1 INC DPTR DJNZ R7,C31 MOV A,#40H LCALL WCMD2 MOV R7,#40H C32:MOV A,#00H MOVC A,@A+DPTR LCALL WDAT2 INC DPTR DJNZ R7,C32
INC R0
CJNE R0,#0C0H,C30
LCALL DELY2
RET
DIS4: MOV A,#0C0H
LCALL WCMD1
LCALL WCMD2
MOV
R0,#0B8H
C40:MOV A,R0
LCALL WCMD1
LCALL WCMD2
MOV A,#40H
LCALL WCMD1
MOV R7,#40H
C41:MOV A,#0FFH
LCALL WDAT1
DJNZ R7,C41
MOV A,#40H
LCALL WCMD2
MOV R7,#40H
C42:MOV A,#0FFH
LCALL WDAT2
DJNZ R7,C42
INC R0
CJNE R0,#0C0H,C40
LCALL DELY2
RET
DIS5:MOV DPTR,#M2
MOV A,#0C0H
LCALL WCMD1
LCALL WCMD2
MOV
R0,#0B8H
C50:MOV A,R0
LCALL WCMD1
LCALL WCMD2
MOV
A,#40H
LCALL
WCMD1 MOV R7,#40H
C51:MOV A,#00H
MOVC A,@A+DPTR
LCALL WDAT1
INC DPTR
DJNZ R7,C51
MOV A,#40H
LCALL WCMD2
MOV R7,#40H
C52:MOV A,#00H
MOVC A,@A+DPTR
LCALL WDAT2
INC DPTR
DJNZ R7,C52
INC R0
CJNE R0,#0C0H,C50
LCALL DELY2
RET
DIS6:MOV A,#0C0H ;
LCALL WCMD1
LCALL WCMD2
MOV R0,#0B8H
D60:MOV A,R0
LCALL WCMD1
LCALL WCMD2
MOV A,#40H
LCALL WCMD1
LCALL WCMD2
MOV R7,#40H
MOV A,#55H
D61:LCALL WDAT1
LCALL WDAT2
DJNZ R7,D61
INC R0
CJNE R0,#0C0H,D60
LCALL DELY2
MOV R7,#0C0H
MOV R0,#01H
FF:MOV A,R7
ADD A,#01H
MOV R7,A
LCALL WCMD1
LCALL WCMD2
LCALL DELY2
DJNZ R0,FF
RET
DIS8:MOV A,#0C0H ;
LCALL WCMD1
LCALL WCMD2
MOV R0,#0B8H
D80:MOV A,R0
LCALL WCMD1
LCALL WCMD2
MOV A,#40H
LCALL WCMD1
LCALL WCMD2
MOV R7,#20H
D81:MOV A,#0FFH
LCALL WDAT1
LCALL WDAT2
MOV A,#00H
LCALL WDAT1
LCALL WDAT2
DJNZ R7,D81
INC R0
CJNE R0,#0C0H,D80
LCALL DELY2
DIS8E: MOV A,#0C0H ;
LCALL WCMD1
LCALL WCMD2
MOV R0,#0B8H
D80E:MOV A,R0
LCALL WCMD1
LCALL WCMD2
MOV R7,#40H
MOV R6,#40H
D81E:MOV A,R6
LCALL WCMD1
LCALL RDAT1
LCALL RDAT1
CPL A
MOV 21H,A
MOV A,R6
LCALL WCMD2
LCALL RDAT2
LCALL RDAT2
CPL A
MOV 22H,A
MOV A,R6
LCALL WCMD1
LCALL WCMD2
MOV A,21H
LCALL WDAT1
MOV A,22H
LCALL WDAT2
INC R6
DJNZ R7,D81E
INC R0
CJNE R0,#0C0H,D80E
LCALL DELY2
RET
WCMD1:PUSH ACC
CLR TE
SETB TCS1
CLR TCS2
CLR TRS
SETB TRW
BUSY1:MOV P1,#0FFH
SETB TE
MOV A,P1
CLR TE
JB ACC.7,BUSY1
POP ACC
CLR TRW
MOV P1,A
SETB TE
CLR TE
CLR TCS1