Document # SRAM113 REV A
P4C198/P4C198L, P4C198A/P4C198AL ULTRA HIGH SPEED 16K x 4STATIC CMOS RAMS
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)– 10/12/15/20/25 ns (Commercial)– 12/15/20/25/35 ns (Industrial)
– 15/20/25/35/45 ns (Military)
Low Power Operation (Commercial/Military)
5V ± 10% Power Supply
Data Retention, 10 μA Typical Current from 2.0V
P4C198L/198AL (Military)
Output Enable & Chip Enable Control Functions – Single Chip Enable P4C198
– Dual Chip Enable P4C198A
Common Inputs and Outputs
Fully TTL Compatible Inputs and Outputs Standard Pinout (JEDEC Approved)– 24-Pin 300 mil DIP – 24-Pin 300 mil SOJ
– 28-Pin 350 x 550 mil LCC
FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS
The P4C198/L and P4C198A/L are 65,536-bit ultra high-speed static RAMs organized as 16K x 4. Each device features an active low Output Enable control to eliminate data bus contention. The P4C198/L also have an active low Chip Enable (the P4C198A/L have two Chip Enables,both active low) for easy system expansion. The CMOS memories require no clocks or refreshing and have equal access and cycle times. Inputs are fully TTL-compatible.The RAMs operate from a single 5V ± 10% tolerance power supply. Data integrity is maintained with supply
DESCRIPTION
voltages down to 2.0V. Current drain is typically 10 μA from a 2.0V supply.
Access times as fast as 12 nanoseconds are available,permitting greatly enhanced system operating speeds.CMOS is used to reduce power consumption to a low 715mW active, 193 mW standby.
The P4C198/L and P4C198A/L are available in 24-pin 300 mil DIP and SOJ, and 28-pin 350 x 550 mil LCC packages providing excellent board level densities.
DIP (P4, C4, D4),
SOJ (J4)P4C198 (P4C198A)
LCC (L5)
P4C198 (P4C198A)
P4C198/198L, P4C198A/198AL
CE 1, CE 2 ≥ V IH Mil.V CC = Max., Ind./Com’l.f = 0, Outputs Open V IN ≤ V LC or V IN ≥ V HC
MAXIMUM RATINGS (1)
Symbol Parameter Value Unit V CC
Power Supply Pin with –0.5 to +7V
Respect to GND Terminal Voltage with –0.5 to V TERM Respect to GND V CC +0.5V (up to 7.0V)
T A
Operating Temperature
–55 to +125
°C
Symbol Parameter Value Unit T BIAS Temperature Under –55 to +125°C Bias
T STG
Storage Temperature –65 to +150
°C P T Power Dissipation 1.0W I OUT
DC Output Current
50
mA
Notes:
1.Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM ratingconditions for extended periods may affect reliability.
2.Extended temperature operation guaranteed with 400 linear feet per minute of air flow.
3.Transient inputs with V IL and I IL not more negative than –3.0V and –100mA, respectively, are permissible for pulse widths up to 20 ns.
4.This parameter is sampled and not 100% tested.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
I SB
Standby Power Supply
Current (TTL Input Levels)
CE 1, CE 2 ≥ V IH Mil.
V CC = Max ., Ind./Com’l.
f = Max., Outputs Open ______4035____________
2015
40n/a 1.5n/a
mA
mA
______
Standby Power Supply Current
(CMOS Input Levels)
I SB1
Commercial
Grade(2)Ambient Temperature
GND V CC 0°C to +70°C –40°C to +85°C 0V 0V
5.0V ± 10%5.0V ± 10%
0V 5.0V ± 10%–55°C to +125°C Military
Symbol C IN C OUT
Parameter Input Capacitance Output Capacitance
Conditions V IN = 0V V OUT = 0V
57
Unit pF pF
CAPACITANCES (4)
V CC = 5.0V, T A = 25°C, f = 1.0MHz n/a = Not Applicable
Symbol DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage (2)V IH V IL V HC V LC V CD V OL V OH I LI I LO Parameter
Input High Voltage Input Low Voltage CMOS Input High Voltage CMOS Input Low Voltage Input Clamp Diode Voltage Output Low Voltage (TTL Load)
Output High Voltage (TTL Load)
Input Leakage Current Output Leakage Current
Test Conditions
V CC = Min., I IN = –18 mA I OL = +10 mA, V CC = Min.I OL = +8 mA, V CC = Min.I OH = –4 mA, V CC = Min.V CC = Max. Mil.V IN = GND to V CC Ind./Com’l.V CC = Max., CE = V IH , Mil.V OUT = GND to V CC Ind./Com’l.
P4C198 / 198A Min 2.2–0.5(3)V CC –0.2–0.5(3)2.4–10–5–10–5Max V CC +0.50.8V CC +0.50.2–1.2
0.4
+10+5+10+5P4C198L / 198AL
Min Max 2.2–0.5(3)V CC –0.2–0.5(3)
2.4–5n/a –5n/a V CC +0.50.8V CC +0.5
0.20.4
–1.2
+5n/a +5n/a Unit
V V V V V V V V μA μA Typ.Industrial
0.5
0.5
DATA RETENTION CHARACTERISTICS (P4C198L/P4C198AL Military Temperature Only)
Typ.*Max
Symbol Parameter Test Condition Min V CC =V CC =Unit 2.0V 3.0V 2.0V 3.0V V DR V CC for Data Retention 2.0
V I CCDR Data Retention Current 10
15
600
900
μA t CDR Chip Deselect to CE ≥V CC – 0.2V,
0ns Data Retention Time V IN ≥ V CC – 0.2V or t
R ?
Operation Recovery Time
t RC §
ns
*T A = +25°C
§t RC = Read Cycle Time
?
This parameter is guaranteed but not tested.
*V CC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V.
198: CE = V IL , OE = V IH
198A: CE 1 = V IL , CE 2 = V IL . OE = V IH
V IN ≤ 0.2V
DATA RETENTION WAVEFORM
I CC
Symbol
Parameter
Temperature
Range
Dynamic Operating Current*
Commercial Industrial Military
–10N/A
–12–15–20–25–35–45Unit N/A mA mA mA
POWER DISSIPATION CHARACTERISTICS VS. SPEED
N/A 150155160170180N/A
170
160
155
150
145
180170160155150N/A N/A
P4C198/198L, P4C198A/198AL
Sym.Parameter Unit
-10
-12-15
-20
-25
-35
-45
Min Max Min
Max Min Max Min Max Min Max Min Max Min Max t RC Read Cycle Time 10
12
1520
253545ns t AA Address Access 10121520253545ns Time t AC Chip Enable 10
12
15
20
25
35
45
ns Access Time t OH Output Hold from 2222222ns Address Change t LZ Chip Enable to 2
2222
2
2
ns Output in Low Z t HZ Chip Disable to 67810101415ns Output in High Z t OE Output Enable 6
7
9
12
15
25
30
ns Low to Data Valid t OLZ
Output Enable to 2
2
22
22
2
ns Output in Low Z
t OHZ Output Disable to
67
9
9
10
14
15
ns Output in High Z t PU Chip Enable to 0
00
ns Power Up Time t PD
Chip Disable to 10
12
1520
25
35
45
ns
Power Down Time
AC CHARACTERISTICS—READ CYCLE
(V CC = 5V ± 10%, All Temperature Ranges)(2)
READ CYCLE NO.1 (OE OE controlled)(5)
Notes:
5.WE is HIGH for READ cycle.
READ CYCLE NO. 2 (ADDRESS Controlled)(5,6)
READ CYCLE NO. 3 (CE (12) Controlled)(5,7,8)
10.Read Cycle Time is measured from the last valid address
to the first transitioning address.
11.Transitions caused by a chip enable control have similar
delays irrespective of whether CE 1 or CE 2 causes them (P4C198A/L).
12.CE 1, CE 2 for P4C198A/L.
Notes:
6.CE (CE 1 CE 2 for P4C198A/L) and OE are LOW READ cycle.
7.OE is LOW for the cycle.
8.ADDRESS must be valid prior to, or coincident with CE (CE 1
and CE 2 for P4C198A/L) transition LOW.
9.Transition is measured ± 200mV from steady state voltage
prior to change, with loading as specified in Figure 1.
P4C198/198L, P4C198A/198AL
-10
-12-15-20
-25
-35
-45
Min Max
Min Max Min Max Min Max Min Max Min Max Min Max
t WC Write Cycle Time 10121315203040ns t CW Chip Enable Time 781015203035ns to End of Write t AW Address Valid to 881015202535ns End of Write t AS Address Set-up 0000000ns Time t WP Write Pulse 891012202535ns Width t AH
Address Hold 0
ns
Time from End of Write
t DW Data Valid to End 76710131520ns of Write t DH Data Hold Time 0
ns t WZ Write Enable to 7
678101015ns Output in High Z t OW
Output Active 33
3
3
3
3
3
ns
from End of Write
AC CHARACTERISTICS—WRITE CYCLE
(V CC = 5V ± 10%, All Temperature Ranges)(2)
Sym.Parameter Unit WRITE CYCLE NO. 1 (With OE high)
WRITE CYCLE NO. 2 (WE CONTROLLED)(13,14)
1520 08
WRITE CYCLE NO. 3 (CE (12) CONTROLLED)(13,14)
Notes:
13.CE (CE 1, CE 2 for P4C198A/L) and WE must be LOW for WRITE
cycle.
14.OE is LOW for this WRITE cycle.
15.If CE (CE 1 or CE 2 for P4C198A/L) goes HIGH simultaneously with WE
HIGH, the output remains in a high impedance state.
16.Write Cycle Time is measured from the last valid address to the first
transitioning address.
P4C198/198L, P4C198A/198AL
TRUTH TABLES
P4C198/L P4C198A/L CE 1CE 2WE OE Mode Output H X X X Standby High Z X H X X Standby High Z L L H H Output Inhibit High Z L L H L READ D OUT L
L
L
X
WRITE
D IN
CE WE OE Mode Output H X X Standby High Z L H H Output Inhibit High Z L H L READ D OUT L
L
X
WRITE
D IN
Input Pulse Levels GND to 3.0V
Input Rise and Fall Times 3ns Input Timing Reference Level 1.5V Output Timing Reference Level 1.5V
Output Load
See Figures 1 and 2
* including scope and test fixture.
Note:
Because of the ultra-high speed of the P4C198/L and P4C198A/L, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the V CC and ground planes directly up to the contactor fingers. A 0.01 μF high
Figure 1. Output Load
Figure 2. Thevenin Equivalent
frequency capacitor is also required between V CC and ground. To avoid signal reflections, proper termination must be used; for example, a 50?test environment should be terminated into a 50? load with 1.73V (Thevenin Voltage) at the comparator input, and a 116? resistor must be used in series with D OUT to match 166? (Thevenin Resistance).
AC TEST CONDITIONS
* Military temperature range with MIL-STD-883, Class B processing.N/A = Not available
SELECTION GUIDE
The P4C198 and P4C198A are available in the following temperature, speed and package options.
ORDERING INFORMATION
P4C198/198L, P4C198A/198AL
SIDE BRAZED DUAL IN-LINE PACKAGE
CERDIP DUAL IN-LINE PACKAGE
SOJ SMALL OUTLINE IC PACKAGE RECTANGULAR LEADLESS CHIP CARRIER
P4C198/198L, P4C198A/198AL
PLASTIC DUAL IN-LINE PACKAGE
REVISIONS
DOCUMENT NUMBER:SRAM113
DOCUMENT TITLE:P4C198 / P4C198L, P4C198A / P4C198AL ULTRA HIGH SPEED 16K x 4 STATIC CMOS
RAMS
REV.ISSUE
DATE
ORIG. OF
CHANGE
DESCRIPTION OF CHANGE
OR1997DAB New Data Sheet
A Oct-05JD
B Change logo to Pyramid