KSI_eMMC5.0_HS200_Datasheet_11.5x13_V1.0_4GB_A08 _General
____________________________________________________________________________________________________________________
CONFIDENTIAL
1
Flash Storage Specification
?2014 Kingston Solutions Inc.
Embedded Multimedia Card
(e ?MMC ?5.0 HS200)
EMMC04G-S100-A08
Preliminary
Datasheet
V1.0
Kingston Solutions Inc.
____________________________________________________________________________________________________________________
CONFIDENTIAL
2
Flash Storage Specification
?2014 Kingston Solutions Inc.
Product Features ：
? Packaged NAND flash memory with e?MMC? 5.0 interface ? Compliant with e?MMC ? Specification Ver.4.4, 4.41,4.5&5.0 ?
Bus mode
- High-speed e ?MMC ? protocol
- Provide variable clock frequencies of 0-200MHz.
- Ten-wire bus (clock, 1 bit command, 8 bit data bus) and a hardware reset. ? Supports three different data bus widths : 1 bit(default), 4 bits, 8 bits
- Data transfer rate: up to 52Mbyte/s (using 8 parallel data lines at 52 MHz) - Single data rate : up to 200Mbyte/s @ 200MHz - Dual data rate : up to 104Mbyte/s @ 52MHz
? Supports (Alternate) Boot Operation Mode to provide a simple boot sequence method ? Supports SLEEP/AWAKE (CMD5).
? Host initiated explicit sleep mode for power saving
? Enhanced Write Protection with Permanent and Partial protection options ? Supports Multiple User Data Partition with Enhanced User Data Area options ? Supports Background Operations & High Priority Interrupt (HPI) ? Supports enhanced storage media feature for better reliability ? Operating voltage range : - VCCQ = 1.8 V/3.3 V - VCC = 3.3 V
? Error free memory access
- Internal error correction code (ECC) to protect data communication - Internal enhanced data management algorithm
- Solid protection of sudden power failure safe-update operations for data content ? Security
- Support secure bad block erase commands
- Enhanced write Protection with permanent and partial protection options ? Quality
- RoHS compliant (for detailed RoHS declaration, please contact your KSI representative.) ? Supports Field Firmware Update(FFU) ? Enhanced Device Life time ? Support Pre EOL information ? Optimal Size
? Supports Production State Awareness ? Supports Power Off Notification for Sleep
____________________________________________________________________________________________________________________
CONFIDENTIAL
3
Flash Storage Specification
?2014 Kingston Solutions Inc.
Device Summary:
Table 1 – Device Summary
Product Part number NAND Density Package Operating voltage EMMC04G-S100-A08
8GB
FBGA153
VCC=3.3V,
VCCQ=1.8V/3.3V
1. Product Description
Kingston e?MMC? products follow the JEDEC e?MMC? 5.0 standard. It is an ideal universal storage solutions for many electronic devices, including smartphones, tablet PCs, PDAs, eBook readers, digital cameras, recorders, MP3, MP4 players, electronic learning products, digital TVs and set-top boxes. E?MMC? encloses the MLC NAND and e?MMC? controller inside as one JEDEC standard package, providing a standard interface to the host. The e?MMC? controller directly manages NAND flash, including ECC, wear-leveling, IOPS optimization and read sensing.
1.1. e ?MMC ? Standard Specification
The Kingston NAND Device is fully compatible with the JEDEC Standard Specification No.JESD84-B50. This datasheet describes the key and specific features of the Kingston e ?MMC ? Device. Any additional information required interfacing the Device to a host system and all the practical methods for device detection and access can be found in the proper sections of the JEDEC Standard Specification.
2. Product Specification
2.1. System Performance
Table 2 – e ?MMC ? Device Performance
Products
Typical value
Read Sequential (MB/s) Write Sequential (MB/s)
EMMC04G-S100-A08 100 12
Note 1: Values given for an 8-bit bus width, running HS200 mode from KSI proprietary tool, VCC=3.3V,
VCCQ=1.8V.
Note 2: For performance number under other test conditions, please contact your KSI representatives. Note 3: Performance numbers might be subject to changes without notice.
____________________________________________________________________________________________________________________
CONFIDENTIAL
4
Flash Storage Specification
?2014 Kingston Solutions Inc.
2.2. Power Consumption
Table 3 – e ?MMC ? Device Power Consumption
Products
Read(mA) Write(mA) Standby(mA)
Typ Typ Typ
EMMC04G-S100-A08 78.5 56.1 0.149
Note 1; Values given for an 8-bit bus width, a clock frequency of 52MHz DDR mode, VCC= 3.3V±5%, VCCQ=3.3V±5% Note 2: Current numbers might be subject to changes without notice.
2.3. User Density
Total user density depends on device type.
For example ,52MB in the SLC mode requires 104 MB in MLC. This results in decreasing
2.4. Capacity according to partition
Capacity Boot partition 1
Boot partition 2
RPMB 4 GB
4096 KB
4096 KB
4096 KB
2.5. User Density
Device
User Density Size
4 GB
3825205248 Bytes
____________________________________________________________________________________________________________________
CONFIDENTIAL
5
Flash Storage Specification
?2014 Kingston Solutions Inc.
1. e ?MMC ? Device and System
3.1. e ?MMC ? System Overview
The e ?MMC ? specification covers the behavior of the interface and the Device controller. As part of this specification the existence of a host controller and a memory storage array are implied but the operation of these pieces is not fully specified.
The Kingston NAND Device contains a single chip MMC controller and NAND flash memory module. The micro-controller interfaces with a host system allowing data to be written to and read from the NAND flash memory module. The controller allows the host to be independent from details of erasing and programming the flash memory.
Figure 1 – e ?MMC ? System Overview
3.2. Memory Addressing
Previous implementations of the e ?MMC ? specification (versions up to v4.1) are following byte addressing with 32 bit field. This addressing mechanism permitted for e ?MMC ? densities up to and including 2 GB.
To support larger densities the addressing mechanism was update to support sector addresses (512 B sectors). The sector addresses shall be used for all devices with capacity larger than 2 GB. To determine the addressing mode use the host should read bit [30:29] in the OCR register.
____________________________________________________________________________________________________________________
CONFIDENTIAL
6
Flash Storage Specification
?2014 Kingston Solutions Inc.
3.3. e ?MMC ? Device Overview
The e ?MMC ? device transfers data via a configurable number of data bus signals. The communication signals are:
3.3.1 Clock (CLK)
Each cycle of this signal directs a one bit transfer on the command and either a one bit (1x) or a two bits transfer (2x) on all the data lines. The frequency may vary between zero and the maximum clock frequency.
3.3.2 Command (CMD)
This signal is a bidirectional command channel used for Device initialization and transfer of commands. The CMD signal has two operation modes: open-drain for initialization mode, and push-pull for fast command transfer. Commands are sent from the e ?MMC ? host controller to the e ?MMC ? Device and responses are sent from the Device to the host.
3.3.3 Input/Outputs (DAT0-DAT7)
These are bidirectional data channels. The DAT signals operate in push-pull mode. Only the Device or the host is driving these signals at a time. By default, after power up or reset, only DAT0 is used for data transfer. A wider data bus can be configured for data transfer, using either DAT0-DAT3 or DAT0-DAT7, by the e ?MMC ? host controller. The e ?MMC ? Device includes internal pull-ups for data lines DAT1-DAT7. Immediately after entering the 4-bit mode, the Device disconnects the internal pull ups of lines DAT1, DAT2, and DAT3. Correspondingly, immediately after entering to the 8-bit mode the Device disconnects the internal pull-ups of lines DAT1–DAT7.
____________________________________________________________________________________________________________________
CONFIDENTIAL
7
Flash Storage Specification
?2014 Kingston Solutions Inc.
He signals on the e ?MMC ? interface are described in Table 4.
Table 4 – e ?MMC ? Interface
Name Type 1 Description CLK I Clock DAT0 I/O/PP Data
DAT1 I/O/PP Data DAT2 I/O/PP Data DAT3 I/O/PP Data DAT4 I/O/PP Data DAT5 I/O/PP Data
DAT6 I/O/PP Data DAT7 I/O/PP Data CMD I/O/PP/OD Command/Response RST_n I Hardware reset VCC S Supply voltage for Core VCCQ S Supply voltage for I/O VSS S Supply voltage ground for Core VSSQ S Supply voltage ground for I/O
Note1：I : input; O : output; PP : push-pull; OD : open-drain; NC : Not connected (or logical high); S : power supply.
Each Device has a set of information registers (see also 0, Device Registers.)
Table 5 – e ?MMC ? Registers
Name
Width
(bytes)
Description Implementation
CID 16 Device Identification number, an individual number for identification. Mandatory
RCA 2 Relative Device Address, is the Device system address, dynamically
assigned by the host during initialization.
Mandatory
DSR 2 Driver Stage Register, to configure the Device’s output drivers. Optional
CSD 16
Device Specific Data, information about the Device operation
conditions.
Mandatory OCR 4 Operation Conditions Register. Used by a special broadcast command
to identify the voltage type of the Device.
Mandatory
EXT_CSD 512 Extended Device Specific Data. Contains information about the Device
capabilities and selected modes. Introduced in standard v4.0 Mandatory
The host may reset the device by:
? Switching the power supply off and back on. The device shall have its own power-on detection
circuitry which puts the device into a defined state after the power-on Device. ? A reset signal
? By sending a special command
3.4. Bus Protocol
After a power-on reset, the host must initialize the device by a special message-based e ?MMC ? bus protocol. For more details, refer to section 5.3.1 of the JEDEC Standard Specification No.JESD84-B50.
____________________________________________________________________________________________________________________
CONFIDENTIAL
8
Flash Storage Specification
?2014 Kingston Solutions Inc.
3.5. Bus Speed Modes
e ?MMC ? defines several bus speed modes. Table 6 summarizes the various modes.
Table 6— Bus Speed Modes
Mode Name Data Rate IO Voltage Bus Width Frequency Max Data Transfer
(implies x8 bus width)
Backwards
Compatibility with legacy MMC card Single 3.3/1.8V 1, 4, 8 0-26MHz 26MB/s High Speed SDR Single 3.3/1.8V 4, 8 0-52MHz 52MB/s High Speed DDR Dual 3.3/1.8V 4, 8 0-52MHz 104MB/s HS200
Single
1.8V
4, 8
0-200MHz
200MB/s
3.5.1 HS200 Bus Speed Mode
The HS200 mode offers the following features: ? SDR Data sampling method
? CLK frequency up to 200MHz Data rate – up to 200MB/s ? 8-bits bus width supported
? Single ended signaling with 4 selectable Drive Strength ? Signaling levels of 1.8V
?
Tuning concept for Read Operations
3.5.2 HS200 System Block Diagram
Figure 2 shows a typical HS200 Host and Device system. The host has a clock generator, which supplies CLK to the Device. For write operations, clock and data direction are the same, write data can be transferred synchronous with CLK, regardless of transmission line delay. For read operations, clock and data direction are opposite; the read data received by Host is delayed by round-trip delay, output delay and latency of Host and Device. For reads, the Host needs to have an adjustable sampling point to reliably receive the incoming data
Figure 2 — Host and Device Block Diagram
____________________________________________________________________________________________________________________
CONFIDENTIAL
9
Flash Storage Specification
?2014 Kingston Solutions Inc.
2. e ?MMC ? Functional Description
4.1 e ?MMC ? Overview
All communication between host and device are controlled by the host (master). The host sends a command, which results in a device response. For more details, refer to section 6.1 of the JEDEC Standard Specification No.JESD84-B50.
Five operation modes are defined for the e ?MMC ? system (hosts and devices): ? Boot operation mode
? Device identification mode ? Interrupt mode ? Data transfer mode ? Inactive mode
4.2 Boot Operation Mode
In boot operation mode, the master (e ?MMC ? host) can read boot data from the slave (e ?MMC ? device) by keeping CMD line low or sending CMD0 with argument + 0xFFFFFFFA, before issuing CMD1. The data can be read from either boot area or user area depending on register setting. For more details, refer to section 6.3 of the JEDEC Standard Specification No.JESD84-B50.
4.3 Device Identification Mode
While in device identification mode the host resets the device , validates operation voltage range and access mode, identifies the device and assigns a Relative device Address (RCA) to the device on the bus. All data communication in the Device Identification Mode uses the command line (CMD) only. For more details, refer to section 6.4 of the JEDEC Standard Specification No.JESD84-B50.
4.4 Interrupt Mode
The interrupt mode on the e ?MMC ? system enables the master (e ?MMC ? host) to grant the transmission allowance to the slaves (Device) simultaneously. This mode reduces the polling load for the host and hence, the power consumption of the system, while maintaining adequate responsiveness of the host to a Device request for service. Supporting e ?MMC ? interrupt mode is an option, both for the host and the Device. For more details, refer to section 6.5 of the JEDEC Standard Specification No.JESD84-B50.
4.5 Data Transfer Mode
When the Device is in Stand-by State, communication over the CMD and DAT lines will be performed in push-pull mode. For more details, refer to section 6.6 of the JEDEC Standard Specification No.JESD84-B50.
____________________________________________________________________________________________________________________
CONFIDENTIAL
10
Flash Storage Specification
?2014 Kingston Solutions Inc.
4.5.1 Data Read
The DAT0-DAT7 bus line levels are high when no data is transmitted. For more details, refer to section 6.6.10 of the JEDEC Standard Specification No.JESD84-B50.
4.5.2 Data Write
The data transfer format of write operation is similar to the data read. For more details, refer to section 6.6.11 of the JEDEC Standard Specification No.JESD84-B50.
4.5.3 Erase
In addition to the implicit erase executed by the Device as part of the write operation, provides a host explicit erase function. For more details, refer to section 6.6.12 of the JEDEC Standard Specification No.JESD84-B50.
4.5.4 TRIM
The TRIM operation is similar to the default erase operation described (See Section 6.6.12 of JESD84-B50). The TRIM function applies the erase operation to write blocks instead of erase groups. The TRIM function allows the host to identify data that is no longer required so that the Device can erase the data if necessary during background erase events. For more details, refer to section 6.6.13 of the JEDEC Standard Specification No.JESD84-B50.
4.5.5 Sanitize
The Sanitize operation is a feature, in addition to TRIM and Erase that is used to remove data from the device. The use of the Sanitize operation requires the device to physically remove data from the unmapped user address space. For more details, refer to section 6.6.14 of the JEDEC Standard Specification No.JESD84-B50.
4.5.6 Discard
The Discard is similar operation to TRIM. The Discard function allows the host to identify data that is no longer required so that the device can erase the data if necessary during background erase events. For more details, refer to section 6.6.15 of the JEDEC Standard Specification No.JESD84-B50.
4.5.7 Write Protect Management
In order to allow the host to protect data against erase or write, the e ?MMC ? shall support two levels of write protect commands. For more details, refer to section 6.6.18 of the JEDEC Standard Specification No.JESD84-B50.
4.5.8 Application-Specific Commands
The e ?MMC ? system is designed to provide a standard interface for a variety applications types. In this environment, it is anticipated that there will be a need for specific customers/applications
____________________________________________________________________________________________________________________
CONFIDENTIAL
11
Flash Storage Specification
?2014 Kingston Solutions Inc.
features. For more details, refer to section 6.6.23 of the JEDEC Standard Specification No.JESD84-B50.
4.5.9 Sleep (CMD5)
A Device may be switched between a Sleep state and a Standby state by SLEEP/AWAKE (CMD5). In the Sleep state the power consumption of the memory device is minimized. For more details, refer to section 6.6.24 of the JEDEC Standard Specification No.JESD84-B50.
4.5.10 Replay Protected Memory Block
A signed access to a Replay Protected Memory Block is provided. This function provides means for the system to store data to the specific memory area in an authenticated and replay protected manner. For more details, refer to section 6.6.25 of the JEDEC Standard Specification No.JESD84-B50.
4.5.11 Dual Data Rate Mode Selection
After the host verifies that the Device complies with version 4.4, or higher, of this standard, and supports dual data rate mode, it may enable the dual data rate data transfer mode in the Device. For more details, refer to section 6.6.26 of the JEDEC Standard Specification No.JESD84-B50.
4.5.12 Dual Data Rate Mode Operation
After the Device has been enabled for dual data rate operating mode, the block length parameter of CMD17, CMD18, CMD24, CMD25 and CMD56 automatically default to 512 bytes and cannot be changed by CMD16 (SET_BLOCKLEN) command which becomes illegal in this mode. For more details, refer to section 6.6.27 of the JEDEC Standard Specification No.JESD84-B50.
4.5.13 Background Operations
Devices have various maintenance operations need to perform internally. In order to reduce latencies during time critical operations like read and write, it is better to execute maintenance operations in other times – when the host is not being serviced. For more details, refer to section 6.6.28 of the JEDEC Standard Specification No.JESD84-B50.
4.5.14 High Priority Interrupt (HPI)
In some scenarios, different types of data on the device may have different priorities for the host. For example, writing operation may be time consuming and therefore there might be a need to suppress the writing to allow demand paging requests in order to launch a process when requested by the user. For more details, refer to section 6.6.29 of the JEDEC Standard Specification No.JESD84-B50.
4.5.15 Context Management
To better differentiate between large sequential operations and small random operations, and to improve multitasking support, contexts can be associated with groups of read or write
____________________________________________________________________________________________________________________
CONFIDENTIAL
12
Flash Storage Specification
?2014 Kingston Solutions Inc.
commands. Associating a group of commands with a single context allows the device to optimize handling of the data. For more details, refer to section 6.6.30 of the JEDEC Standard Specification No.JESD84-B50.
4.5.16 Data Tag Mechanism
The mechanism permits the device to receive from the host information about specific data types (for instance file system metadata, time-stamps, configuration parameters, etc.). The information is conveyed before a write multiple blocks operation at well-defined addresses. By receiving this information the device can improve the access rate during the following read and update operations and offer a more reliable and robust storage. For more details, refer to section 6.6.31 of the JEDEC Standard Specification No.JESD84-B50.
4.5.17 Packed Commands
Read and write commands can be packed in groups of commands (either all read or all write) that transfer the data for all commands in the group in one transfer on the bus, to reduce overheads. For more details, refer to section 6.6.32 of the JEDEC Standard Specification No.JESD84-B50.
4.5.18 Real Time Clock Information
Providing real time clock information to the device may be useful for internal maintenance operations. Host may provide either absolute time (based on UTC) if available, or relative time. This feature provides a mechanism for the host to update both real time clock and relative time updates (see CMD49). For more details, refer to section 6.6.38 of the JEDEC Standard Specification No.JESD84-B50.
4.5.19 Power Off Notification
The host should notify the device before it powers the device off. This allows the device to better prepare itself for being powered off. For more details, refer to section 6.6.39 of the JEDEC Standard Specification No.JESD84-B50.
4.6 Inactive Mode
The device will enter inactive mode if either the device operating voltage range or access mode is not valid. The device can also enter inactive mode with GO_INACTIVE_STATE command (CMD15). The device will reset to Pre-idle state with power cycle. For more details, refer to section 6.1 of the JEDEC Standard Specification No.JESD84-B50.
4.7 Clock Control
The e ?MMC ? bus clock signal can be used by the host to put the Device into energy saving mode, or to control the data flow (to avoid under-run or over-run conditions) on the bus. The host is allowed to lower the clock frequency or shut it down. For more details, refer to section 6.7 of the JEDEC Standard Specification No.JESD84-B50.
____________________________________________________________________________________________________________________
CONFIDENTIAL
13
Flash Storage Specification
?2014 Kingston Solutions Inc.
4.8 Error Conditions
Refer to section 6.8 of the JEDEC Standard Specification No.JESD84-B50.
4.9 Minimum Performance
Refer to section 6.9 of the JEDEC Standard Specification No.JESD84-B50.
4.10 Commands
Refer to section 6.10 of the JEDEC Standard Specification No.JESD84-B50.
4.11 Device State Transition Table
Refer to section 6.11 of the JEDEC Standard Specification No.JESD84-B50.
4.12 Responses
Refer to section 6.12 of the JEDEC Standard Specification No.JESD84-B50.
4.13 Timings
Refer to section 6.15 of the JEDEC Standard Specification No.JESD84-B50.
4.14 H/W Reset Operation
Note1: Device will detect the rising edge of RST_n signal to trigger internal reset sequence
Figure 3 – H/W Reset Waveform
____________________________________________________________________________________________________________________
CONFIDENTIAL
14
Flash Storage Specification
?2014 Kingston Solutions Inc.
Table 7 – H/W Reset Timing Parameters
Symbol Comment
Min Max
Unit tRSTW RST_n pulse width 1 [us] tRSCA RST_n to Command time 2001
[us]
tRSTH
RST_n high period (interval time)
1
[us]
Note1：74 cycles of clock signal required before issuing CMD1 or CMD0 with argument 0xFFFFFFFA
4.15 Noise Filtering Timing for H/W Reset
Device must filter out 5ns or less pulse width for noise immunity
Device must not detect these rising edge
Figure 4 – Noise Filtering Timing for H/W Reset
Device must not detect 5ns or less of positive or negative RST_n pulse. Device must detect more than or equal to 1us of positive or negative RST_n pulse width.
4.16 Field Firmware Update(FFU)
Field Firmware Updates (FFU) enables features enhancement in the field. Using this mechanism the host downloads a new version of the firmware to the e.MMC device and, following a successful download, instructs the e.MMC device to install the new downloaded firmware into the device.
In order to start the FFU process the host first checks if the e.MMC device supports FFU
capabilities by reading SUPPPORTED_MODES and FW_CONFIG fields in the EXT_CSD. If the e.MMC device supports the FFU feature the host may start the FFU process. The FFU process starts by
switching to FFU Mode in MODE_CONFIG field in the EXT_CSD. In FFU Mode host should use closed-ended or open ended commands for downloading the new firmware and reading vendor proprietary data. In this mode, the host should set the argument of these commands to be as defined in FFU_ARG field.
____________________________________________________________________________________________________________________
CONFIDENTIAL
15
Flash Storage Specification
?2014 Kingston Solutions Inc.
In case these commands have a different argument the device behavior is not defined and the FFU process may fail. The host should set Block Length to be DATA_SECTOR_SIZE. Downloaded
firmware bundle must be DATA_SECTOR_SIZE size aligned (internal padding of the bundle might be required).Once in FFU Mode the host may send the new firmware bundle to the device using one or more write commands.
The host could regain regular functionality of write and read commands by setting MODE_CONFIG field in the EXT_CSD back to Normal state. Switching out of FFU Mode may abort the firmware
download operation. When host switched back to FFU Mode, the host should check the FFU Status to get indication about the number of sectors which were downloaded successfully by reading the
NUMBER_OF_FW_SECTORS_CORRECTLY_PROGRAMMED in the extended CSD. In case the number of sectors which were downloaded successfully is zero the host should re-start downloading the new firmware bundle from its first sector. In case the number of sectors which were downloaded
successfully is positive the host should continue the download from the next sector, which would resume the firmware download operation.
In case MODE_OPERATION_CODES field is not supported by the device the host sets to NORMAL state and initiates a CMD0/HW_Reset/Power cycle to install the new firmware. In such case the device doesn’t need to use NUMBER_OF_FW_SECTORS_CORRECTLY_PROGRAMMED.
In both cases occurrence of a CMD0/HW_Reset/Power occurred before the host successfully
downloaded the new firmware bundle to the device may cause the firmware download process to be aborted.
____________________________________________________________________________________________________________________
CONFIDENTIAL
16
Flash Storage Specification
?2014 Kingston Solutions Inc.
4.17 Device Life time
4.17.1 DEVICE LIFE TIME SET TYB B
This field provides an estimated indication about the device life time which is reflected by the averaged wear out of memory of Type B relative to its maximum estimated device life time
Table 8 – Device life time estimation type B value
Value Description 0x00 Not defined
0x01 0% - 10% device life time used 0x02 10% -20% device life time used 0x03 20% -30% device life time used 0x04 30% - 40% device life time used 0x05 40% - 50% device life time used 0x06 50% - 60% device life time used 0x07 60% - 70% device life time used 0x08 70% - 80% device life time used 0x09 80% - 90% device life time used 0x0A 90% - 100% device life time used
0x0B Exceeded its maximum estimated device life time
Others
Reserved
4.17.2 DEVICE LIFE TIME SET TYB A
This field provides an estimated indication about the device life time which is reflected by the averaged wear out of memory of Type A relative to its maximum estimated device life time
Table 9 – Device life time estimation type A value
Value Description 0x00 Not defined
0x01 0% - 10% device life time used 0x02 10% -20% device life time used 0x03 20% -30% device life time used 0x04 30% - 40% device life time used 0x05 40% - 50% device life time used 0x06
50% - 60% device life time used
____________________________________________________________________________________________________________________
CONFIDENTIAL
17
Flash Storage Specification
?2014 Kingston Solutions Inc.
0x07 60% - 70% device life time used 0x08 70% - 80% device life time used 0x09 80% - 90% device life time used 0x0A 90% - 100% device life time used
0x0B Exceeded its maximum estimated device life time
Others
Reserved
4.18 Pre EOL Information
This field provides indication about device life time reflected by average reserved blocks
Table 10 – Pre EOL info value
Value Pre-EOL Info. Description 0x00 Not Defined 0x01 Normal Normal
0x02 Warning Consumed 80% of reserved block
0x03 Urgent 0x04 ~ 0xFF
Reserved
4.19 Optimal Size
4.19.1 OPTIMAL READ SIZE
This field provides the minimum optimal (for the device) read unit size for the different partitions.
Table 11 – Optimal read size value
Value Optimal Read Size 0x00 Not defined 0x01 4KB x 1 = 4KB 0x02 4KB x 2 = 8KB
…
0xFF
4KB x 255 = 1020KB
____________________________________________________________________________________________________________________
CONFIDENTIAL
18
Flash Storage Specification
?2014 Kingston Solutions Inc.
4.19.2 OPTIMAL WRITE SIZE
This field provides the minimum optimal (for the device) write unit size for the different partitions. “Optimal” relates to the minimum wearout done by the device.
Table 12 – Optimal write size value
Value Optimal Write Size
0x00 Not defined 0x01 4KB x 1 = 4KB 0x02 4KB x 2 = 8KB
…
0xFF
4KB x 255 = 1020KB
4.19.3 OPTIMAL TRIM UNIT SIZE
This field provides the minimum optimal (for the device) trim unit size for the different partitions. “Optimal” relates to the minimum wearout done by the device.
Table 13 – Optimal trim unit size value
Value Optimal Trim unit Size
0x00 Not defined 0x01 4KB x 1 = 4KB 0x02 4KB x 2 = 8KB 0x03 4KB x 4 = 16KB
…
0x15 4KB x 2^20 = 4GB
Reserved
4.19 Production State Awareness
e.MMC device could utilize the information of whether it is in production environment and operate differently than it operates in the field.
For example, content which was loaded into the storage device prior to soldering might get corrupted, at higher probability, during device soldering. The e.MMC device could use “special” internal operations for loading content prior to device soldering which would reduce production failures and use “regular” operations post-soldering.
____________________________________________________________________________________________________________________
CONFIDENTIAL
19
Flash Storage Specification
?2014 Kingston Solutions Inc.
PRODUCTION_STATE_AWARENESS [133] field in extended CSD is used as a mechanism through which the host should report to the device whether it is pre or post soldering state.
This specification defines two methods, Manual Mode and Auto Mode, to manage the device production state.
The trigger for starting or re-starting the process using the ‘special’ internal operations is setting correctly PRE_LOADING_DATA_SIZE field. Before setting this field the host is expected to make sure that the device is clean and any data which was written before to the device is expected to be erased using CMD35, CMD36 and CMD38.
In case the host erased data, override existing data or preformed re-partition during production state awareness it should restart the production state awareness process by re-setting PRE_LOADING_DATA_SIZE.
4.21.1 Manual Mode
Using Manual Mode method the host explicitly sets the production state by changing the
PRODUCTION_STATE_AWARENESS field. The host should to PRE_SOLDERING_WRITES state when the device is in production prior soldering and before the host loaded content to the device. When loading of content is complete the host should set to PRE_SOLDERING_POST_WRITES state. In this state the host should not write content to the device until soldering is preformed. Once soldered, the host should set PRODUCTION_STATE_AWARENESS to Normal state.
In this mode the host is not expected to write any data to the device until PRODUCTION_STATE_AWARENESS is set to PRE_SOLDERING_ WRITES.
In case the feature is enabled and the host writes to the device not in PRE_SOLDERING_WRITES state the device may response with an error.
PRODUCTION_STATE_AWARENESS state change may exceed the switch command timeout. The maximum timeout for PRODUCTION_STATE_AWARENESS state change is defined by the device manufacturer in INI_ PRODUCTION_STATE_AWARENESS_TIMEOUT [218].
4.20 Power off Notification for sleep
The host should notify the device before it powers the device off. This allows the device to better prepare itself for being powered off. Power the device off means to turn off all its power supplies. In particular, the host should issue a power off notification (POWER_OFF_LONG, POWER_OFF_SHORT ) if it intends to turn off both VCC and VCCQ power I or it may use to a power off notification (SLEEP_NOTIFICATION ) if it intends to turn-off VCC after moving the device to Sleep state.
To indicate to the device that power off notification is supported by the host, a supporting host shall first set the POWER_OFF_NOTIFICATION byte in EXT_CSD [34] to POWERED_ON (0x01). To
____________________________________________________________________________________________________________________
CONFIDENTIAL
20
Flash Storage Specification
?2014 Kingston Solutions Inc.
execute a power off, before powering the device down the host will changes the value to either
POWER_OFF_SHORT (0x02) or POWER_OFF_LONG (0x03). Host should waits for the busy line to be de-asserted. Once the setting has changed to either 0x02 or 0x03, host may safely power off the device.
The host may issue SLEEP_AWAKE (CMD5) to enter or to exit from Sleep state if
POWER_OFF_NOTIFICATION byte is set to POWERED_ON. Before moving to Standby state and then to Sleep state, the host sets POWER_OFF_NOTIFICATION to SLEEP_NOTIFICATION and waits for the DAT0 line de-assertion. While in Sleep (slp) state VCC (Memory supply) may be turned off as defined in 4.1.6. Removing power supplies other than VCC while the device is in the Sleep (slp) state may result in undefined device behavior. Before removing all power supplies, the host should transition the device out of Sleep (slp) state back to Transfer state using CMD5 and CMD7 and then execute a power off notification setting POWER_OFF_NOTIFICATION byte to either POWER_OFF_SHORT or POWER_OFF_LONG.
If host continues to send commands to the device after switching to the power off setting (POWER _OFF_LONG, POWER_OFF_SHORT or SLEEP_NOTIFICATION) or performs HPI during its busy conditio n, the device shall restore the POWER_OFF_NOTIFICATION byte to POWERED_ON.
If host tries to change POWER_OFF_NOTIFICATION to 0x00 after writing another value there, a SWIT CH_ERROR is generated.
The difference between the two power-off modes is how urgent the host wants to turn power off. The device should respond to POWER_OFF_SHORT quickly under the generic CMD6 timeout. If more t ime is acceptable, POWER_OFF_LONG may be used and the device shall respond to it within the POW ER_OFF_LONG_TIME timeout.
While POWER_OFF_NOTIFICATION is set to POWERED_ON, the device expects the host to host shall: ?Keep the device power supplies alive (both Vcc and Vccq) and in their active mode
?Not power off the device intentionally before changing POWER_OFF_NOTIFICATION to either POWER_OFF_LONG or POWER_OFF_SHORT
?Not power off VCC intentionally before changing POWER_OFF_NOTIFICATION to SLEEP_NOTIFICATION and before moving the device to Sleep state
Before moving to Sleep state hosts may set the POWER_OFF_NOTIFICATION byte to
SLEEP_NOTIFICATION (0x04) if aware that the device is capable of autonomously initiating
background operations for possible performance improvements. Host should wait for the busy line to be de-asserted. Busy line may be asserted up the period defined in SLEEP_NOTIFICATION_TIME byte in EXT_CSD [216]. Once the setting has changed to 0x04 host may set the device into Sleep mode (CMD7+CMD5). After getting out from Sleep the POWER_OFF_NOTIFICATION byte will restore its