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RT8010智联创新

RT8010/A

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Features

+2.5V to +5.5V Input Range

Output Voltage (Adjustable Output From 0.6V to V IN )`RT8010 : 1.0V, 1.2V, 1.5V, 1.6V, 1.8V, 2.5V and 3.3V Fixed/Adjustable Output Voltage

`RT8010A Adjustable Output Voltage Only

1A Output Current 95% Efficiency

No Schottky Diode Required

1.5MHz Fixed-Frequency PWM Operation

Small 6-Lead WDFN and 16-Lead WQFN Package

RoHS Compliant and 100% Lead (Pb)-Free

Applications

Mobile Phones

Personal Information Appliances Wireless and DSL Modems MP3 Players

Portable Instruments

1.5MHz, 1A, High Efficiency PWM Step-Down DC/DC Converter

General Description

The RT8010/A is a high-efficiency Pulse-Width-Modulated (PWM) step-down DC-DC converter. Capable of delivering 1A output current over a wide input voltage range from 2.5V to 5.5V, the RT8010/A is ideally suited for portable electronic devices that are powered from 1-cell Li-ion battery or from other power sources such as cellular phones, PDAs and hand-held devices.

Two operating modes are available including : PWM/Low-Dropout autoswitch and shut-down modes. The Internal synchronous rectifier with low R DS(ON) dramatically reduces conduction loss at PWM mode. No external Schottky diode is required in practical application.

The RT8010/A enters Low-Dropout mode when normal PWM cannot provide regulated output voltage by continuously turning on the upper PMOS. RT8010/A enter shut-down mode and consumes less than 0.1μA when EN pin is pulled low.

The switching ripple is easily smoothed-out by small package filtering elements due to a fixed operating frequency of 1.5MHz. This along with small WDFN-6L 2x2and WQFN-16L 3x3 package provides small PCB area application. Other features include soft start, lower internal reference voltage with 2% accuracy, over temperature protection, and over current protection.

Note :

RichTek Pb-free and Green products are :

`RoHS compliant and compatible with the current require- ments of IPC/JEDEC J-STD-020.

`Suitable for use in SnPb or Pb-free soldering processes.`100% matte tin (Sn) plating.

Ordering Information

Pin Configurations

(TOP VIEW)

WDFN-6L 2x2 (RT8010)Marking Information

For marking information, contact our sales representative directly or through a RichTek distributor located in your area, otherwise visit our website for detail.

FB/VOUT

GND GND GND

VIN

VIN VIN

VIN G N D E N N C N C

C X X

NC VIN

FB/VOUT GND LX

EN WQFN-16L 3x3 (RT8010A)

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RT8010/A

https://www.sodocs.net/doc/6b8554169.html, Typical Application Circuit

Figure 1. Fixed Voltage Regulator

Figure 2. Adjustable Voltage Regulator

????+=R2R11 x V V REF OUT with R2 = 300k Ω to 60k Ω so the I R2 = 2μA to 10μA,

and (R1 x C1) should be in the range between 3x10-6 and 6x10-6 for component selection.

Figure 3

Layout note:

1.The distance that C IN connects to V IN is as close as possible (Under 2mm).

2. C OUT should be placed near RT8010/A.

Layout Guide

V IN

OUT

V IN

OUT

between V DD and

GND as closer as

possible

compontents away

from this trace

RT8010/A_FIX between V DD and GND as closer as possible

short trace, keep

sensitive compontents

away from this trace

RT8010/A

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Function Block Diagram

FB/VOUT

GND

RT8010/A

https://www.sodocs.net/doc/6b8554169.html, Absolute Maximum Ratings (Note 1)

Supply Input Voltage ------------------------------------------------------------------------------------------------------6.5V

EN, FB Pin Voltage -------------------------------------------------------------------------------------------------------?0.3V to V IN

Power Dissipation, P D @ T A = 25°C

WDFN-6L 2x2--------------------------------------------------------------------------------------------------------------0.606W WQFN-16L 3x3------------------------------------------------------------------------------------------------------------1.47W

Package Thermal Resistance (Note 4)

WDFN-6L 2x2, θJA ---------------------------------------------------------------------------------------------------------

165°C/W WDFN-6L 2x2, θJC --------------------------------------------------------------------------------------------------------20°C/W WQFN-16L 3x3, θJA -------------------------------------------------------------------------------------------------------68°C/W WQFN-16L 3x3, θJC ------------------------------------------------------------------------------------------------------7.5°C/W Lead Temperature (Soldering, 10 sec.)-------------------------------------------------------------------------------260°C

Storage T emperature Range --------------------------------------------------------------------------------------------?65°C to 150°C Junction T emperature -----------------------------------------------------------------------------------------------------150°C

ESD Susceptibility (Note 2)

HBM (Human Body Mode)----------------------------------------------------------------------------------------------2kV MM (Machine Mode)------------------------------------------------------------------------------------------------------200V

Electrical Characteristics

(V IN = 3.6V, V OUT = 2.5V, V REF = 0.6V, L = 2.2μH, C IN = 4.7μF, C OUT = 10μF, T A = 25°C, I MAX = 1A unless otherwise specified)

To be continued

Recommended Operating Conditions (Note 3)

Supply Input Voltage ------------------------------------------------------------------------------------------------------2.5V to 5.5V Junction T emperature Range -------------------------------------------------------------------------------------------- ?40°C to 125°C

Ambient T emperature Range -------------------------------------------------------------------------------------------- ?40°C to 85°C

RT8010/A

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Note 1. Stresses listed as the above “Absolute Maximum Ratings ” may cause permanent damage to the device. These are for

stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability.

Note 2. Devices are ESD sensitive. Handling precaution recommended.

Note 3. The device is not guaranteed to function outside its operating conditions.

Note 4. θJA is measured in the natural convection at T A = 25°C on a high effective four layers thermal conductivity test board of

JEDEC 51-7 thermal measurement standard. The case point of θJC is on the expose pad for the QFN package.

Note 5. ΔV = I OUT x P RDS(ON)Note 6. Guarantee by design.

RT8010/A

https://www.sodocs.net/doc/6b8554169.html, Typical Operating Characteristics

Efficiency vs. Output Current

01020304050607080

901000

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Output Current (A)E f f i c i e n c y (%)

Efficiency vs. Output Current

010203040506070

901000

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Output Current (A)E f f i c i e n c y (%)

Efficiency vs. Output Current

01020

304050607080

90100

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Output Current (A)

E f f i c i e n c y (%

)

UVLO Voltage vs.Temperature

1.2

1.3

1.41.51.61.71.81.9

2.0-40-25-10

95110125

Temperature I n p u t V o l t a g

e (V )

(°C)

EN Pin Threshold vs. Input Voltage

2.5

2.8

3.1

3.4

3.7

4.3

4.6

4.9

5.2

5.5

Input Voltage (V)E N P i n T h r e s h o l d (V )

EN Pin Threshold vs. Temperature

0.4

0.50.6

0.70.80.91.01.11.21.31.4

1.51.6-40-25-10

95110125

Temperature E N P i n T h r e s h o l d (V )

(°C)

RT8010/A

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Output Voltage vs. Temperature

1.15

1.161.171.181.191.201.211.221.23

1.241.25-40-25-10

95110125

Temperature O u t p u t V o l t a g e (V

)

(°C)

Output Current Limit vs. Input Voltage

2.5

2.8

3.1

3.4

3.7

4.3

4.6

4.9

5.2

5.5

Input Voltage (V)

O u t p u t C u r r e n t L i m i t (A )

Output Current Limit vs. Temperature

1.5

1.61.71.81.9

2.02.12.22.32.42.5

2.6-40-25-10

95110125

Temperature O u t p u t C u r r e n t L i m i t (A )

(°C)

Frequency vs. Temperature

1.20

1.25

1.301.351.401.451.501.55

1.60-40-25-10

95110125

Temperature F r e q u e n c y (k H z )

(°

Frequency vs. Input Voltage

2.5

2.8

3.1

3.4

3.7

4.3

4.6

4.9

5.2

5.5

Input Voltage (V)F r e q u e n c y (k H z )

Output Voltage vs. Load Current

1.180

1.1851.1901.1951.2001.2051.2101.2151.220

1.2251.2300

0.1

0.2

0.3

0.40.50.60.70.80.91

Load Current (A)

O u t p u t V o l t a g e (V )

RT8010/A

https://www.sodocs.net/doc/6b8554169.html, Power On from EN

Time (100μs/Div)

V IN = 3.6V, V OUT = 1.2V, I OUT = 10mA

V OUT (1V/Div)V EN (2V/Div)I IN

(500mA/Div)

Power On from EN

Time (100μs/Div)

V IN = 3.6V, V OUT = 1.2V, I OUT = 1A

V OUT (1V/Div)V EN (2V/Div)I IN

(500mA/Div)

Power Off from EN

Time (100μs/Div)

V IN = 3.6V, V OUT = 1.2V, I LX = 1A

V OUT (1V/Div)V EN (2V/Div)I LX (1A/Div)

Power On from VIN

Time (250μs/Div)

V EN = 3V, V OUT = 1.2V, I LX = 1A

V OUT (1V/Div)V IN (2V/Div)I LX (1A/Div)

Load Transient Response

Time (50μs/Div)

V IN = 3.6V, V OUT = 1.2V I OUT = 50mA to 1A

V OUT ac (50mV/Div)

I OUT

(500mA/Div)

Load Transient Response

Time (50μs/Div)

V IN = 3.6V, V OUT = 1.2V I OUT = 50mA to 0.5A

V OUT ac (50mV/Div)

I OUT

(500mA/Div)

RT8010/A

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Load Transient Response

Time (50μs/Div)

V IN = 5V, V OUT = 1.2V I OUT = 50mA to 1A

V OUT ac (50mV/Div)I OUT

(500mA/Div)

Output Ripple Voltage

Time (500ns/Div)

V IN = 3.6V, V OUT = 1.2V I OUT = 1A

V OUT (10mV/Div)V LX (2V/Div)

Output Ripple Voltage

Time (500ns/Div)

V IN = 5V, V OUT = 1.2V I OUT = 1A

V OUT (10mV/Div)

V LX (2V/Div)

Load Transient Response

Time (50μs/Div)

V IN = 5V, V OUT = 1.2V I OUT = 50mA to 0.5A

V OUT ac (50mV/Div)

I OUT

(500mA/Div)

RT8010/A

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????+

≤OUT L OUT 8fC 1ESR ΔI ΔV Applications Information

The basic RT8010/A application circuit is shown in Typical Application Circuit. External component selection is determined by the maximum load current and begins with the selection of the inductor value and operating frequency followed by C IN and C OUT .Inductor Selection

For a given input and output voltage, the inductor value and operating frequency determine the ripple current. The ripple current ΔI L increases with higher V IN and decreases with higher inductance.

Having a lower ripple current reduces the ESR losses in

the output capacitors and the output voltage ripple. Highest efficiency operation is achieved at low frequency with small ripple current. This, however, requires a large inductor.A reasonable starting point for selecting the ripple current is ΔI L = 0.4(I MAX ). The largest ripple current occurs at the highest V IN . To guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation :

Inductor Core Selection

Once the value for L is known, the type of inductor must

be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores,forcing the use of more expensive ferrite or mollypermalloy cores. Actual core loss is independent of core size for a fixed inductor value but it is very dependent on the inductance selected. As the inductance increases, core losses decrease. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase.

Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation.Ferrite core material saturates “hard ”, which means that inductance collapses abruptly when the peak design

????

??×??????×=IN OUT OUT L V V 1L f V

ΔI ??????

?×?

?????=IN(MAX)OUT L(MAX)OUT V 1V L current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple.Do not allow the core to saturate!

Different core materials and shapes will change the size/current and price/current relationship of an inductor.T oroid or shielded pot cores in ferrite or permalloy materials are small and don't radiate energy but generally cost more than powdered iron core inductors with similar characteristics. The choice of which style inductor to use mainly depends on the price vs size requirements and any radiated field/EMI requirements.C IN and C OUT Selection

The input capacitance, C IN , is needed to filter the trapezoidal current at the source of the top MOSFET. To prevent large ripple voltage, a low ESR input capacitor sized for the maximum RMS current should be used. RMS current is given by :1V V V V I I OUT

OUT OUT(MAX)

RMS ?=This formula has a maximum at V IN = 2V OUT , where I RMS = I OUT /2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design.

The selection of C OUT is determined by the effective series resistance (ESR) that is required to minimize voltage ripple and load step transients, as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. Loop stability can be checked by viewing the load transient response as described in a later section.The output ripple, ΔV OUT , is determined by :

RT8010/A

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The output ripple is highest at maximum input voltage since ΔI L increases with input voltage. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Special polymer capacitors offer very low ESR but have lower capacitance density than other types. Tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient and audible piezoelectric effects.The high Q of ceramic capacitors with trace inductance can also lead to significant ringing.

Using Ceramic Input and Output Capacitors

Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. However, care must be taken when these capacitors are used at the input and output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, V IN . At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at V IN large enough to damage the part.

Output Voltage Programming

The resistive divider allows the FB pin to sense a fraction of the output voltage as shown in Figure 4.

)

R1(1V V REF OUT += Figure 4. Setting the Output Voltage

where V REF is the internal reference voltage (0.6V typ.)For adjustable voltage mode, the output voltage is set by an external resistive divider according to the following equation :

Efficiency Considerations

The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Efficiency can be expressed as :Efficiency = 100% ? (L1+ L2+ L3+ ...)

where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses : VIN quiescent current and I 2R losses.

The VIN quiescent current loss dominates the efficiency loss at very low load currents whereas the I 2R loss dominates the efficiency loss at medium to high load currents. In a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence.

1. The VIN quiescent current appears due to two factors including : the DC bias current as given in the electrical characteristics and the internal main switch and synchronous switch gate charge currents. The gate charge current results from switching the gate capacitance of the internal power MOSFET switches. Each time the gate is switched from high to low to high again, a packet of charge ΔQ moves from V IN to ground.

The resulting ΔQ/Δt is the current out of V IN that is typically larger than the DC bias current. In continuous mode,I GATECHG = f(Q T +Q B )

where Q T and Q B are the gate charges of the internal top and bottom switches. Both the DC bias and gate charge losses are proportional to V IN and thus their effects will be more pronounced at higher supply voltages.

V OUT

RT8010/A 12

https://www.sodocs.net/doc/6b8554169.html, Checking Transient Response

The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, V OUT immediately shifts by an amount equal to ΔI LOAD (ESR), where ESR is the effective series resistance of C OUT. ΔI LOAD also begins to charge or discharge C OUT generating a feedback error signal used by the regulator to return V OUT to its steady-state value. During this recovery time, V OUT can be monitored for overshoot or ringing that would indicate a stability problem.

Layout Considerations

Follow the PCB layout guidelines for optimal performance of RT8010/A.

` For the main current paths as indicated in bold lines in Figure 6, keep their traces short and wide.

` Put the input capacitor as close as possible to the device pins (VIN and GND).

` LX node is with high frequency voltage swing and should be kept small area. Keep analog components away from LX node to prevent stray capacitive noise pick-up.

` Connect feedback network behind the output capacitors. Keep the loop area small. Place the feedback components near the RT8010/A.

2. I2R losses are calculated from the resistances of the internal switches, R SW and external inductor R L. In continuous mode, the average output current flowing through inductor L is “chopped” between the main switch and the synchronous switch. Thus, the series resistance looking into the LX pin is a function of both top and bottom MOSFET R DS(ON) and the duty cycle (DC) as follows :

R SW = R DS(ON)TOP x DC + R DS(ON)BOT x (1?DC)

The R DS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus, to obtain I2R losses, simply add R SW to R L and multiply the result by the square of the average output current.

Other losses including C IN and C OUT ESR dissipative losses and inductor core losses generally account for less than 2% of the total loss.

Thermal Considerations

The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula :

P D(MAX) = ( T J(MAX) - T A ) / θJA

Where T J(MAX) is the maximum operation junction temperature, T A is the ambient temperature and the θJA is the junction to ambient thermal resistance.

For recommended operating conditions specification of RT8010/A DC/DC converter, where T J(MAX) is the maximum junction temperature of the die and T A is the maximum ambient temperature. The junction to ambient thermal resistance θJA is layout dependent. For WDFN-6L 2x2 packages, the thermal resistance θJA is 165°C/W on the standard JEDEC 51-7 four layers thermal test board.

The maximum power dissipation at T A = 25°C can be calculated by following formula :

P D(MAX) = (125°C ? 25°C) / 165°C/W = 0.606W for WDFN-6L 2x2 packages

The maximum power dissipation depends on operating ambient temperature for fixed T J(MAX) and thermal resistance θJA.For RT8010/A packages, the Figure 5 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed.

Figure 5. Derating Curves for RT8010/A Package

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

0255075100125

Ambient Temperature

(

)

(°C)

RT8010/A

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` Connect all analog grounds to a command node and then connect the command node to the power ground behind the output capacitors.

` An example of 2-layer PCB layout is shown in Figure 7to Figure 8 for reference.

Figure 6. EVB Schematic

Figure 7. Top Layer

Figure 8. Bottom Layer

Table 2. Recommended Capacitors for C IN and C OUT

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Richtek Technology Corporation

Headquarter

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Tel: (8863)5526789 Fax: (8863)5526611

Richtek Technology Corporation

Taipei Office (Marketing)

8F, No. 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C.

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W-Type 16L QFN 3x3 Package

RT8010智联创新

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