STM32F107_Datasheet_15274

September 2009Doc ID 15274 Rev 41/95

STM32F105xx STM32F107xx

Connectivity line, ARM-based 32-bit MCU with 64/256 KB Flash, USB OTG, Ethernet, 10 timers, 2 CANs, 2 ADCs, 14 communication interfaces

Features

I

Core: ARM 32-bit Cortex?-M3 CPU –72 MHz maximum frequency,

1.25DMIPS/MHz (Dhrystone

2.1) performance at 0 wait state memory access

–Single-cycle multiplication and hardware division I

Memories

–64 to 256 Kbytes of Flash memory

–up to 64 Kbytes of general-purpose SRAM I

Clock, reset and supply management

– 2.0 to 3.6V application supply and I/Os –POR, PDR, and programmable voltage detector (PVD)

–3-to-25 MHz crystal oscillator

–Internal 8 MHz factory-trimmed RC –Internal 40 kHz RC with calibration

–32 kHz oscillator for RTC with calibration I

Low power

–Sleep, Stop and Standby modes

–V BAT supply for RTC and backup registers I

2 × 12-bit, 1 μs A/D converters (16 channels)–Conversion range: 0 to 3.6 V –Sample and hold capability –Temperature sensor

–up to 2 MSPS in interleaved mode I 2 × 12-bit D/A converters

I

DMA: 12-channel DMA controller

–Supported peripherals: timers, ADCs, DAC, I 2Ss, SPIs, I 2Cs and USARTs I

Debug mode

–Serial wire debug (SWD) & JTAG interfaces –Cortex-M3 Embedded T race Macrocell?I

Up to 80 fast I/O ports

–51/80 I/Os, all mappable on 16 external interrupt vectors and almost all 5V-tolerant I

CRC calculation unit, 96-bit unique ID

I

Up to 10 timers with pinout remap capability –Up to four 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter and

quadrature (incremental) encoder input – 1 × 16-bit motor control PWM timer with dead-time generation and emergency stop – 2 × watchdog timers (Independent and Window)

–SysTick timer: a 24-bit downcounter – 2 × 16-bit basic timers to drive the DAC I

Up to 14 communication interfaces with pinout remap capability

–Up to 2 × I 2C interfaces (SMBus/PMBus)–Up to 5 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control)–Up to 3 SPIs (18 Mbit/s), 2 with a

multiplexed I 2S interface that offers audio class accuracy via advanced PLL schemes – 2 × CAN interfaces (2.0B Active) with 512bytes of dedicated SRAM

–USB 2.0 full-speed device/host/OTG

controller with on-chip PHY that supports HNP/SRP/ID with 1.25 Kbytes of dedicated SRAM

–10/100 Ethernet MAC with dedicated DMA and SRAM (4 Kbytes): IEEE1588 hardware support, MII/RMII available on all packages

Table 1.

Device summary

Reference Part number

STM32F105xx

STM32F105R8, STM32F105V8 STM32F105RB, STM32F105VB STM32F105RC, STM32F105VC STM32F107xx

STM32F107RB, STM32F107VB STM32F107RC, STM32F107VC

https://www.sodocs.net/doc/6413876447.html,

Contents STM32F105xx, STM32F107xx

Contents

1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.3.1ARM? Cortex?-M3 core with embedded Flash and SRAM . . . . . . . . . 13

2.3.2Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.3.3CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 13

2.3.4Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.3.5Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 13

2.3.6External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 14

2.3.7Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.3.8Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.3.9Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.10Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.11Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.12Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.13DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.3.14RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 16

2.3.15Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.16I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.3.17Universal synchronous/asynchronous receiver transmitters (USARTs) 18

2.3.18Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.3.19Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.3.20Ethernet MAC interface with dedicated DMA and IEEE 1588 support . 19

2.3.21Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.3.22Universal serial bus on-the-go full-speed (USB OTG FS) . . . . . . . . . . . 20

2.3.23GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 20

2.3.24Remap capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.3.25ADCs (analog-to-digital converters) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.3.26DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.3.27Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.3.28Serial wire JT AG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 22 2/95 Doc ID 15274 Rev 4

STM32F105xx, STM32F107xx Contents

2.3.29Embedded Trace Macrocell? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.1Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.1.1Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.1.2Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.1.3Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.1.4Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.1.5Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.1.6Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.1.7Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.2Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.3Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.3.1General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.3.2Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 35

5.3.3Embedded reset and power control block characteristics . . . . . . . . . . . 35

5.3.4Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.3.5Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.3.6External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5.3.7Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

5.3.8PLL, PLL2 and PLL3 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

5.3.9Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

5.3.10EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

5.3.11Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 52

5.3.12I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

5.3.13NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

5.3.14TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

5.3.15Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

5.3.1612-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

5.3.17DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

5.3.18Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

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Contents STM32F105xx, STM32F107xx

6.1Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

6.2Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

6.2.1Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

6.2.2Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 80

7Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Appendix A Applicative block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

A.1USB OTG FS interface solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

A.2Ethernet interface solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

A.3Complete audio player solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

A.4USB OTG FS interface + Ethernet/I2S interface solutions . . . . . . . . . . . . 89 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

4/95 Doc ID 15274 Rev 4

STM32F105xx, STM32F107xx List of tables List of tables

Table 1.Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2.STM32F105xx and STM32F107xx features and peripheral counts . . . . . . . . . . . . . . . . . . 10 Table 3.STM32F105xx and STM32F107xx family versus STM32F103xx family . . . . . . . . . . . . . . 11 Table 4.Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 5.Pin definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 6.Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 7.Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 8.Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 9.General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 10.Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 11.Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 12.Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 13.Maximum current consumption in Run mode, code with data processing

running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 14.Maximum current consumption in Run mode, code with data processing

running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 15.Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 38 Table 16.Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 38 Table 17.Typical current consumption in Run mode, code with data processing

running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 18.Typical current consumption in Sleep mode, code running from Flash or

RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 19.Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 20.High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 21.Low-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 22.HSE 3-25 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 23.LSE oscillator characteristics (f LSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 24.HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 25.LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 26.Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 27.PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 28.PLL2 and PLL3 characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 29.Flash memory characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 30.Flash memory endurance and data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 31.EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 32.EMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 33.ESD absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 34.Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 35.I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 36.Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 37.I/O AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 38.NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 39.TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 40.I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 41.SCL frequency (f PCLK1= 36 MHz.,V DD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 42.SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 43.I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table https://www.sodocs.net/doc/6413876447.html,B OTG FS startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

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List of tables STM32F105xx, STM32F107xx Table https://www.sodocs.net/doc/6413876447.html,B OTG FS DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table https://www.sodocs.net/doc/6413876447.html,B OTG FS electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 47.Ethernet DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 48.Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 49.Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 50.Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 51.ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 52.R AIN max for f ADC = 14 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 53.ADC accuracy - limited test conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 54.ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 55.DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 56.TS characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 57.LQPF100 – 100-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . 77 Table 58.LQFP64 – 64 pin low-profile quad flat package mechanical data. . . . . . . . . . . . . . . . . . . . 78 Table 59.Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 60.Ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 61.PLL configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 62.Applicative current consumption in Run mode, code with data

processing running from Flash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 63.Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6/95 Doc ID 15274 Rev 4

STM32F105xx, STM32F107xx List of figures List of figures

Figure 1.STM32F105xx and STM32F107xx connectivity line block diagram . . . . . . . . . . . . . . . . . 12 Figure 2.STM32F105xxx and STM32F107xxx connectivity line LQFP100 pinout . . . . . . . . . . . . . . 23 Figure 3.STM32F105xxx and STM32F107xxx connectivity line LQFP64 pinout . . . . . . . . . . . . . . . 24 Figure 4.Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 5.Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 6.Pin input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 7.Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 8.Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 9.Typical current consumption on V BAT with RTC on vs. temperature at

different V BAT values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 10.Typical current consumption in Stop mode with regulator in Run mode

versus temperature at different V DD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 11.Typical current consumption in Stop mode with regulator in Low-power

mode versus temperature at different V DD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 12.Typical current consumption in Standby mode versus temperature at

different V DD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 13.High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 14.Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 15.Typical application with an 8 MHz crystal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 16.Typical application with a 32.768 kHz crystal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 17.I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 18.Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 19.I2C bus AC waveforms and measurement circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 20.SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 21.SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 22.SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figure 23.I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 24.I2S master timing diagram (Philips protocol)(1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure https://www.sodocs.net/doc/6413876447.html,B OTG FS timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . 65 Figure 26.Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 27.Ethernet RMII timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Figure 28.Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Figure 29.ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Figure 30.Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Figure 31.Power supply and reference decoupling (V REF+ not connected to V DDA). . . . . . . . . . . . . . 72 Figure 32.Power supply and reference decoupling (V REF+ connected to V DDA). . . . . . . . . . . . . . . . . 72 Figure 33.12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 34.LQFP100, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Figure 35.Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Figure 36.LQFP64 – 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Figure 37.Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Figure 38.LQFP100 P D max vs. T A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Figure https://www.sodocs.net/doc/6413876447.html,B OTG FS device mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Figure 40.Host connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Figure 41.OTG connection (any protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Figure 42.MII mode using a 25 MHz crystal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Figure 43.RMII with a 50 MHz oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Figure 44.RMII with a 25 MHz crystal and PHY with PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

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List of figures STM32F105xx, STM32F107xx Figure 45.RMII with a 25 MHz crystal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure https://www.sodocs.net/doc/6413876447.html,plete audio player solution 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Figure https://www.sodocs.net/doc/6413876447.html,plete audio player solution 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Figure https://www.sodocs.net/doc/6413876447.html,B OTG FS + Ethernet solution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Figure https://www.sodocs.net/doc/6413876447.html,B OTG FS + I2S (Audio) solution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

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STM32F105xx, STM32F107xx Introduction

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1 In t roduc t

ion

This datasheet provides the description of the STM32F105xx and STM32F107xx connectivity line microcontrollers. For more details on the whole STMicroelectronics

STM32F10xxx family, please refer to Section 2.2: Full compatibility throughout the family .The STM32F105xx and STM32F107xx datasheet should be read in conjunction with the STM32F10xxx reference manual.

For information on programming, erasing and protection of the internal Flash memory please refer to the STM32F10xxx Flash programming manual.

The reference and Flash programming manuals are both available from the STMicroelectronics website https://www.sodocs.net/doc/6413876447.html,.

For information on the Cortex?-M3 core please refer to the Cortex?-M3 Technical Reference Manual, available from the https://www.sodocs.net/doc/6413876447.html, website at the following address: https://www.sodocs.net/doc/6413876447.html,/help/index.jsp?topic=/com.arm.doc.ddi0337e/.

2 Descrip t

ion

The STM32F105xx and STM32F107xx connectivity line family incorporates the high-performance ARM ? Cortex?-M3 32-bit RISC core operating at a 72MHz frequency, high-speed embedded memories (Flash memory up to 256 Kbytes and SRAM up to 64 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All devices offer two 12-bit ADCs, four general-purpose 16-bit timers plus a PWM timer, as well as standard and advanced communication interfaces: up to two I 2Cs, three SPIs, two I2Ss, five USARTs, an USB OTG FS and two CANs. Ethernet is available on the STM32F107xx only.

The STM32F105xx and STM32F107xx connectivity line family operates in the –40 to +105°C temperature range, from a 2.0 to 3.6V power supply. A comprehensive set of power-saving mode allows the design of low-power applications.

The STM32F105xx and STM32F107xx connectivity line family offers devices in two different package types: from 64 pins to 100 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family.

Description STM32F105xx, STM32F107xx

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These features make the STM32F105xx and STM32F107xx connectivity line microcontroller family suitable for a wide range of applications:

G Motor drive and application control G Medical and handheld equipment

G Industrial applications: PLC, inverters, printers, and scanners G Alarm systems, Video intercom, and HVAC G

Home audio equipment

Figure 1 shows the general block diagram of the device family.

2.1 Device overview

1.Please refer to Table 5: Pin definitions for peripheral availability when the I/O pins are shared by the peripherals required

by the application.2.The SPI2 and SPI3 interfaces give the flexibility to work in either the SPI mode or the I 2S audio mode.

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2.2 Full compa

ibili y throughout the family

The STM32F105xx and STM32F107xx constitute the connectivity line family whose

members are fully pin-to-pin, software and feature compatible.

The STM32F105xx and STM32F107xx are a drop-in replacement for the low-density (STM32F103x4/6), medium-density (STM32F103x8/B) and high-density

(STM32F103xC/D/E) performance line devices, allowing the user to try different memory densities and peripherals providing a greater degree of freedom during the development cycle.

(1)

1.Please refer to Table 5: Pin definitions for peripheral availability when the I/O pins are shared by the peripherals required

by the application.2.Ports F and G are not available in devices delivered in 100-pin packages.

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2.3 Overview

1.T A = –40 °C to +85 °C (suffix 6, see Table 60) or –40 °C to +105 °C (suffix 7, see Table 60), junction temperature up to

105°C or 125 °C, respectively.

2.AF = alternate function on I/O port pin.

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2.3.1 ARM ? Cortex?-M3 core with embedded Flash and SRAM

The ARM Cortex?-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.The ARM Cortex?-M3 32-bit RISC processor features exceptional code-efficiency,

delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices.

With its embedded ARM core, STM32F105xx and STM32F107xx connectivity line family is compatible with all ARM tools and software.

Figure 1 shows the general block diagram of the device family.

2.3.2 Embedded Flash memory

64 to 256 Kbytes of embedded Flash is available for storing programs and data.

2.3.3 CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit

data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of

verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location.

2.3.4 Embedded SRAM

20 to 64 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait

states.

2.3.5 Nested vectored interrupt controller (NVIC)

The STM32F105xx and STM32F107xx connectivity line embeds a nested vectored interrupt controller able to handle up to 67 maskable interrupt channels (not including the 16 interrupt lines of Cortex?-M3) and 16 priority levels.

G Closely coupled NVIC gives low latency interrupt processing G Interrupt entry vector table address passed directly to the core G Closely coupled NVIC core interface G Allows early processing of interrupts

G Processing of late arriving higher priority interrupts G Support for tail-chaining

G Processor state automatically saved

G

Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt latency.

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2.3.6 Ex t ernal in t errup t

/event controller (EXTI)

The external interrupt/event controller consists of 20 edge detector lines used to generate

interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 80 GPIOs can be connected to the 16 external interrupt lines.

2.3.7 Clocks and startup

System clock selection is performed on startup, however, the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 3-25 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example with failure of an indirectly used external oscillator).

A single 25 MHz crystal can clock the entire system including the ethernet and US

B OTG FS peripherals. Several prescalers and PLLs allow the configuration of the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum

frequency of the AHB and the high speed APB domains is 72 MHz. The maximum allowed frequency of the low speed APB domain is 36 MHz. Refer to Figure 48: USB OTG FS + Ethernet solution on page 89.

The advanced clock controller clocks the core and all peripherals using a single crystal or oscillator. In order to achieve audio class performance, an audio crystal can be used. In this case, the I 2S master clock can generate all standard sampling frequencies from 8kHz to 96kHz with less than 0.5% accuracy error. Refer to Figure 49: USB OTG FS + I 2S (Audio) solution on page 89.

To configure the PLLs, please refer to T able 61 on page 90, which provides PLL configurations according to the application type.

2.3.8 Boo t modes At startup, boot pins are used to select one of three boot options:

G Boot from User Flash G Boot from System Memory G

Boot from embedded SRAM

The boot loader is located in System Memory. It is used to reprogram the Flash memory by

using USART1, USART2 (remapped), CAN2 (remapped) or USB OTG FS in device mode (DFU: device firmware upgrade). For remapped signals refer to T able 5: Pin definitions .The USART peripheral operates with the internal 8MHz oscillator (HSI), however the CAN and USB OTG FS can only function if an external 8 MHz, 14.7456 MHz or 25 MHz clock (HSE) is present.

For full details about the boot loader, please refer to AN2662.

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2.3.9 Power supply schemes

G

V DD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. Provided externally through V DD pins.

G

V SSA , V DDA = 2.0 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs and PLL (minimum voltage to be applied to V DDA is 2.4 V when the ADC is used). V DDA and V SSA must be connected to V DD and V SS , respectively.

G

V BAT = 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when V DD is not present.

2.3.10 Power supply supervisor

The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains in reset mode when V DD is below a specified threshold, V POR/PDR , without the need for an external reset circuit.

The device features an embedded programmable voltage detector (PVD) that monitors the V DD /V DDA power supply and compares it to the V PVD threshold. An interrupt can be

generated when V DD /V DDA drops below the V PVD threshold and/or when V DD /V DDA is higher than the V PVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

2.3.11 Vol t age regula t or

The regulator has three operation modes: main (MR), low power (LPR) and power down.

G MR is used in the nominal regulation mode (Run) G LPR is used in the Stop modes.

G

Power down is used in Standby mode: the regulator output is in high impedance: the

kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost)

This regulator is always enabled after reset. It is disabled in Standby mode.

2.3.12 Low-power modes

The STM32F105xx and STM32F107xx connectivity line supports three low-power modes to

achieve the best compromise between low power consumption, short startup time and available wakeup sources:

G

Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

G

Stop mode

Stop mode achieves the lowest power consumption while retaining the content of

SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode.

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB OTG FS wakeup.

Description STM32F105xx, STM32F107xx

G Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal

voltage regulator is switched off so that the entire 1.8 V domain is powered off. The

PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

Standby mode, SRAM and register contents are lost except for registers in the Backup

domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a

rising edge on the WKUP pin, or an RTC alarm occurs.

Note:The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode.

2.3.13 DMA

The flexible 12-channel general-purpose DMAs (7 channels for DMA1 and 5 channels for

DMA2) are able to manage memory-to-memory, peripheral-to-memory and memory-to-

peripheral transfers. The two DMA controllers support circular buffer management,

removing the need for user code intervention when the controller reaches the end of the

buffer.

Each channel is connected to dedicated hardware DMA requests, with support for software

trigger on each channel. Configuration is made by software and transfer sizes between

source and destination are independent.

The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose, basic

and advanced control timers TIMx, DAC, I2S and ADC.

In the STM32F107xx, there is a DMA controller dedicated for use with the Ethernet (see

Section2.3.20: Ethernet MAC interface with dedicated DMA and IEEE 1588 support for

more information).

2.3.14 RTC (real-time clock) and backup registers

The RTC and the backup registers are supplied through a switch that takes power either on

V DD supply when present or through the V BAT pin. The backup registers are forty-two 16-bit

registers used to store 84 bytes of user application data when V DD power is not present.

They are not reset by a system or power reset, and they are not reset when the device

wakes up from the Standby mode.

The real-time clock provides a set of continuously running counters which can be used with

suitable software to provide a clock calendar function, and provides an alarm interrupt and a

periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the

internal low power RC oscillator or the high-speed external clock divided by 128. The

internal low-speed RC has a typical frequency of 40 kHz. The RTC can be calibrated using

an external 512 Hz output to compensate for any natural quartz deviation. The RTC features

a 32-bit programmable counter for long term measurement using the Compare register to

generate an alarm. A 20-bit prescaler is used for the time base clock and is by default

configured to generate a time base of 1 second from a clock at 32.768 kHz.

For more information, please refer to AN2604: “STM32F101xx and STM32F103xx RTC

calibration”, available from https://www.sodocs.net/doc/6413876447.html,.

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2.3.15 Timers and watchdogs

The STM32F105xx and STM32F107xx devices include an advanced-control timer, four general-purpose timers, two basic timers, two watchdog timers and a SysTick timer.Table 4 compares the features of the general-purpose and basic timers.

Advanced-control timer (TIM1)

The advanced control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable inserted dead-times. It can also be seen as a complete general-purpose timer. The 4 independent channels can be used for:

G Input capture G Output compare

G PWM generation (edge or center-aligned modes)G

One-pulse mode output

If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If configured as the 16-bit PWM generator, it has full modulation capability (0-100%). The counter can be frozen in debug mode.

Many features are shared with those of the standard TIM timers which have the same

architecture. The advanced control timer can therefore work together with the TIM timers via the Timer Link feature for synchronization or event chaining.

General-purpose timers (TIMx)

There are up to 4 synchronizable standard timers (TIM2, TIM3, TIM4 and TIM5) embedded in the STM32F105xx and STM32F107xx connectivity line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture/output compare, PWM or one pulse mode output. This gives up to 16 input captures / output compares / PWMs on the largest packages. They can work together with the Advanced Control timer via the Timer Link feature for synchronization or event chaining.

The counter can be frozen in debug mode.

Table 4.

Timer feature comparison

Timer

Counter resolution Counter type Prescaler factor DMA request generation Capture/compare channels Complementary outputs TIM116-bit

Up, down, up/down Any integer between 1 and 65536Y es

4

Y es

TIMx (TIM2, TIM3, TIM4, TIM5)16-bit Up, down, up/down

Any integer between 1 and 65536Y es 4No

TIM6, TIM7

16-bit Up Any integer between 1 and 65536

Y es 0No

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Any of the standard timers can be used to generate PWM outputs. Each of the timers has independent DMA request generations.

Basic timers TIM6 and TIM7

These timers are mainly used for DAC trigger generation. They can also be used as a generic 16-bit time base.

Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is

clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.

Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features:

G A 24-bit down counter G Autoreload capability

G Maskable system interrupt generation when the counter reaches 0.G

Programmable clock source

2.3.16 I2C bus

Up to two I2C bus interfaces can operate in multimaster and slave modes. They can support

standard and fast modes.

They support 7/10-bit addressing mode and 7-bit dual addressing mode (as slave). A hardware CRC generation/verification is embedded.

They can be served by DMA and they support SMBus 2.0/PMBus.

2.3.17 Universal synchronous/asynchronous receiver transmitters (USARTs)

The STM32F105xx and STM32F107xx connectivity line embeds three universal

synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3) and two universal asynchronous receiver transmitters (UART4 and UART5).

These five interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability.

The USART1 interface is able to communicate at speeds of up to 4.5 Mbit/s. The other available interfaces communicate at up to 2.25 Mbit/s.

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USART1, USART2 and USART3 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller except for UART5.

2.3.18 Serial peripheral interface (SPI)

Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in

full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC/SDHC (a) modes.All SPIs can be served by the DMA controller.

2.3.19 In t er-in t egra t

ed sound (I 2S)

Two standard I 2S interfaces (multiplexed with SPI2 and SPI3) are available, that can be

operated in master or slave mode. These interfaces can be configured to operate with 16/32 bit resolution, as input or output channels. Audio sampling frequencies from 8 kHz up to 96kHz are supported. When either or both of the I 2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency with less than 0.5% accuracy error owing to the advanced clock controller (see Section 2.3.7: Clocks and startup ).

Please refer to the “Audio frequency precision” tables provided in the “Serial peripheral interface (SPI)” section of the STM32F10xxx reference manual.

2.3.20 E t herne t

MAC interface with dedicated DMA and IEEE 1588 support

Peripheral not available on STM32F105xx devices.

The STM32F107xx devices provide an IEEE-802.3-2002-compliant media access controller

(MAC) for ethernet LAN communications through an industry-standard media-independent interface (MII) or a reduced media-independent interface (RMII). The STM32F107xx requires an external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber, etc.). the PHY is connected to the STM32F107xx MII port using as many as 17 signals (MII) or 9 signals (RMII) and can be clocked using the 25MHz (MII) or 50 MHz (RMII) output from the STM32F107xx.

The STM32F107xx includes the following features:

G Supports 10 and 100 Mbit/s rates

G

Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM and the descriptors (see the STM32F105xx/STM32F107xx reference manual for details)

G Tagged MAC frame support (VLAN support)G Half-duplex (CSMA/CD) and full-duplex operation G

MAC control sublayer (control frames) support

a.SDHC = Secure digital high capacity.

Description

STM32F105xx, STM32F107xx

20/95 Doc ID 15274 Rev 4

G 32-bit CRC generation and removal

G

Several address filtering modes for physical and multicast address (multicast and group addresses)

G 32-bit status code for each transmitted or received frame

G

Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive FIFO are both 2 Kbytes, that is 4 Kbytes in total

G

Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 with the timestamp comparator connected to the TIM2 trigger input G

Triggers interrupt when system time becomes greater than target time

2.3.21 Con t

roller area network (CAN)

The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to

1Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one CAN is used). The 256 bytes of SRAM which are allocated for each CAN (512 bytes in total) are not shared with any other peripheral.

2.3.22 Universal serial bus on-the-go full-speed (USB OTG FS)

The STM32F105xx and STM32F107xx connectivity line devices embed a USB OTG full-speed (12Mb/s) device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are:

G

1.25 KB of SRAM used exclusively by the endpoints (not shared with any other peripheral)

G 4 bidirectional endpoints

G HNP/SNP/IP inside (no need for any external resistor)

G

for OTG/Host modes, a power switch is needed in case bus-powered devices are connected

G

the SOF output can be used to synchronize the external audio DAC clock in isochronous mode

G

in accordance with the USB 2.0 Specification, the supported transfer speeds are:–in Host mode: full speed and low speed –

in Device mode: full speed

2.3.23 GPIOs (general-purpose inputs/outputs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as

input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current-capable except for analog inputs.

The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.I/Os on APB2 with up to 18 MHz toggling speed