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FT5x06 电容触摸屏控制器

FT5x06

True Multi-Touch

Capacitive Touch

Panel Controller

INTRODUCTION

The FT5x06 Series ICs are single-chip capacitive touch panel controller ICs with a built-in 8 bit Micro-controller unit (MCU).They adopt the mutual capacitance approach, which supports true multi-touch capability. In conjunction with a mutual capacitive touch panel, the FT5x06 have user-friendly input functions, which can be applied on many portable devices, such as cellular phones, MIDs, netbook and notebook personal computers.

The FT5x06 series ICs include FT5206/FT5306/FT5406, the difference of their specifications will be listed individually in this datasheet.

FEATURES

z Mutual Capacitive Sensing Techniques

z True Multi-touch with up to 10 Points of Absolution X and Y Coordinates z Immune to RF Interferences

z Auto-calibration: Insensitive to Capacitance and Environ-mental Variations z Supports up to 28 Transmit Lines and 16 Receive Lines z Supports up to 8.9” Touch Screen

z Full Programmable Scan Sequences with Individual Ad-justable Receive Lines and Transmit Lines to Support Various Applications z High Report Rate: More than 100Hz

z Touch Resolution of 100 Dots per Inch (dpi) or above -- depending on the Panel Size z Optional Interfaces :I2C/SPI z 2.8V to 3.6V Operating Voltage z Supports 1.8V/AVDD IOVCC

z Capable of Driving Single Channel (transmit/receive) Re-sistance: Up to15K ? z Capable of Supporting Single Channel (transmit/receive) Capacitance: 60 pF z Optimal Sensing Mutual Capacitor: 1pF~4pF z 12-Bit ADC Accuracy

z Built-in MCU with 28KB Program Memory, 6KB Data Memory and 256B Internal Data Space z 11 Internal Interrupt Sources and 2 External Interrupt Sources z 3 Operating Modes

? Active ? Monitor ? Hibernate

z Operating Temperature Range: -40°C to +85°C

FT5x06 Array

DATASHEET

INTRODUCTION..........................................................................................................................................................I FEATURES....................................................................................................................................................................I 1 OVERVIEW.. (1)

1.1 T YPICAL A PPLICATIONS (1)

2 FUNCTIONAL DESCRIPTION (1)

2.1 A RCHITECTURAL O VERVIEW (1)

2.2 MCU (2)

2.3 O PERATION M ODES (2)

2.4 H OST I NTERFACE (3)

2.5 S ERIAL I NTERFACE (3)

2.5.1 I2C (3)

2.5.2 SPI (4)

3 ELECTRICAL SPECIFICATIONS (8)

3.1 A BSOLUTE M AXIMUM R ATINGS (8)

3.2 DC C HARACTERISTICS (9)

3.3 AC C HARACTERISTICS (9)

3.4 I/O P ORTS C IRCUITS (10)

3.5 POWER ON/R ESET/W AKE S EQUENCE (11)

4 PIN CONFIGURATIONS (12)

5 PACKAGE INFORMATION (15)

5.1 P ACKAGE I NFORMATION OF QFN-5X5-40L P ACKAGE (15)

5.2 P ACKAGE I NFORMATION OF QFN-6X6-48L P ACKAGE (16)

5.3 P ACKAGE I NFORMATION OF QFN-8X8-68L P ACKAGE (17)

5.4 O RDER I NFORMATION (18)

1OVERVIEW

1.1Typical Applications

FT5x06 accommodate a wide range of applications with a set of buttons up to a 2D touch sensing device, their typical applications are listed below.

z Mobile phones, smart phones

z MIDs

z Netbook

z Navigation systems, GPS

z Game consoles

z Car applications

z POS (Point of Sales) devices

z Portable MP3 and MP4 media players

z Digital cameras

FT5x06 Series ICs support 2.8”~8.9” Touch Panel, users may find out their target IC from the specs. listed in the following table,

Panel Package

Model Name

Touch Panel Size

TX RX Type Pin Size

FT5206GE1 15 10 QFN5*5 40 0.75-P0.4 2.8"～3.8"

FT5306DE4 20 12 QFN6*6 48 0.75-P0.4 4.3"～7"

FT5406EE8 28 16 QFN8*8 68 0.75-P0.4 7"～8.9"

2FUNCTIONAL DESCRIPTION

2.1Architectural Overview

Figure2-1 shows the overall architecture for the FT5x06.

Figure 2-1 FT5x06 System Architecture Diagram

The FT5x06 is comprised of five main functional parts listed below,

z Touch Panel Interface Circuits

The main function for the AFE and AFE controller is to interface with the touch panel. It scans the panel by sending AC signals to the panel and processes the received signals from the panel. So, it supports both Transmit (TX) and Receive (RX) functions. Key pa-rameters to configure this circuit can be sent via serial interfaces, which will be explained in detail in a later section.

z8051-based MCU

This MCU is 8051 compatible with some enhancements. For instant, larger program and data memories are supported. In addition, a Multiplication-Division unit (MDU) is implemented to speed up the touch detection algorithms. Furthermore, a Flash ROM is implemented to store programs and some key parameters.

Complex signal processing algorithms are implemented with firmware running on this MCU to process further the received signals in order to detect the touches reliably. Communication protocol software is also implemented on this MCU to exchange data and control information with the host processor.

z External Interface

?I2C/SPI: an interface for data exchange with host

?INT: an interrupt signal to inform the host processor that touch data is ready for read

?WAKE: an interrupt signal for the host to change F5x06 from Hibernate to Active mode

?/RST: an external low signal reset the chip.

z A watch dog timer is implemented to ensure the robustness of the chip.

z A voltage regulator to generate 1.8V for digital circuits from the input VDD3 supply

2.2MCU

This section describes some critical features and operations supported by the 8051 compatible MCU.

Figure 2-2 shows the overall structure of the MCU block. In addition to the 8051 compatible MCU core, we have added the following circuits,

z MDU: A 16x8 Multiplier and A 32/32 Divider

z Program Memory: 28KB Flash

z Data Memory: 6KB SRAM

z Real Time Clock (RTC): A 32KHz RC Oscillator

z Timer: A number of timers are available to generate different clocks

z Master Clock: 24/ 48MHz from a 48MHz RC Oscillator

z Clock Manager: To control various clocks under different operation conditions of the system

Figure 2-2 MCU Block Diagram

2.3Operation Modes

FT5x06 operates in the following three modes:

z Active Mode

When in this mode, FT5x06 actively scans the panel. The default scan rate is 60 frames per second. The host processor can configure FT5x06 to speed up or to slow down.

z Monitor Mode

When in this mode, FT5x06 scans the panel at a reduced speed. The default scan rate is 25 frames per second and the host processor can increase or decrease this rate. When in this mode, most algorithms are stopped. A simpler algorithm is being executed to de-termine if there is a touch or not. When a touch is detected, FT5x06 shall enter the Active mode immediately to acquire the touch information quickly. During this mode, the serial port is closed and no data shall be transferred with the host processor. z Hibernate Mode

In this mode, the chip is set in a power down mode. It shall only respond to the “WAKE” or “RESET” signal from the host processor. The chip therefore consumes very little current, which help prolong the standby time for the portable devices.

2.4 Host Interface

Figure 2-3 shows the interface between a host processor and FT5x06. This interface consists of the following three sets of signals: z Serial Interface

z Interrupt from FT5x06 to the Host z Wake-up Signal from the Host to FT5x06

Figure 2-3 Host Interface Diagram

The serial interfaces of FT5x06 is I2C or SPI. The details of this interface are described in detail in Section 2.5. The interrupt signal (/INT) is used for FT5x06 to inform the host that data are ready for the host to receive. The /WAKE signal is used for the host to wake up FT5x06 from the Hibernate mode. After exiting the Hibernate mode, FT5x06 shall enter the Active mode.

2.5 Serial Interface

FT5x06 supports the I2C or SPI interfaces, which can be used by a host processor or other devices.

2.5.1 I2C

The I2C is always configured in the Slave mode. The data transfer format is shown in Figure 2-4

Figure 2-4 I2C Serial Data Transfer Format

Figure 2-5 I2C master write, slave read

Figure 2-6 I2C master read, slave write

Table 2-1 lists the meanings of the mnemonics used in the above figures.

Table 2-1 Mnemonics Description

Mnemonics

Description

S I2C Start or I2C Restart

A[6:0]

Slave address A[6:4]: 3’b011

A[3:0]: data bits are identical to those of I2CCON[7:4] register.

W 1’b0: Write R 1’b1: Read A(N) ACK(NACK) P

STOP: the indication of the end of a packet (if this bit is missing, S will indicate the end

of the current packet and the beginning of the next packet)

I2C Interface Timing Characteristics is shown in Table 2-2.

Table 2-2 I2C Timing Characteristics

Parameter

Unit Min Max

SCL frequency

KHz 0 400

Bus free time between a STOP and START condition us 4.7 \ Hold time (repeated) START condition us 4.0 \ Data setup time

ns 250 \ Setup time for a repeated START condition us 4.7 \ Setup Time for STOP condition

4.0

2.5.2 SPI

SPI is a 4 wire serial interface. The following is a list of the 4 wires: z SCK: serial data clock

z MOSI: data line from master to slave z MISO: data line from slave to master z SLVESEL: active low select signal

SPI transfers data at 8bit packets. The phase relationship between the data and the clock can be defined by the two registers: phase and polck. Some data transfer examples can be found in Figure 2-7 to Figure 2-10.

Figure 2-7 SPI Data Transfer Format (Phase=0, POLCK=0)

Figure 2-8 SPI Data Transfer Format (PHASE=0, POLCK=1)

bit7bit6bit5bit4bit3bit2bit1bit0

MSB

MISO/MOS

SCK

SLVSEL

PHASE=1 POLE=0

Figure 2-9 SPI Data Transfer Format (Phase=1, POLCK=0)

Figure 2-10 SPI Data Transfer Format (Phase=1, POLCK=1)

SPI can be configured into either Master or Slave mode via the MAS bit of the SPI0CON register. When in the Master mode, the SPI needs to supply the data clock, whose frequency relationship with the Master clock can be set by CLKDVD bits of the SPI0CON register. When it is configured in the Slave mode, the clock, SCK, is supplied by the external Master. The maximum data clock

frequency must not be higher than

mclk

SPI Interface Timing Characteristics is shown in the following Figure2-11,Figure2-12, Figure2-13, Figure2-14 and Table 2-3.

MOSI SCK(POLCK=0

)

SLVSEL

MISO Tmckh Tmckl

Tmsf c

SCK(POLCK=1

)

PHASE=0

Tmsr c

Tmo

Tmh

Tsd

Figure 2-11 SPI master Timing PHASE =0

MOSI SCK(POLCK=0

)

SLVSEL

MISO Tmck

Tmckl Tmsfc

SCK(POLCK=1

)PHASE=1

Tmo

Tmh

Tmsr c

Figure 2-12 SPI master Timing PHASE =1

Figure 2-13 SPI slave Timing PHASE = 0

MOSI

SCK(POLCK=0

)

SLVSEL

MISO

Tsck

Tsckl

Tsfc

SCK(POLCK=1

)

PHASE=1

Tsr

Figure 2-14 SPI slave Timing PHASE = 1

Table 2-3 SPI Timing Parameters

Parameter Description Min Max Units

Master Mode timing (see figure 2-11,2-12)

Tmckh sck high time 4×Tsysclk -- ns Tmckl sck low time 4×Tsysclk -- ns Tmo sck shift edge to mosi data change 0 -- ns

Tmh mosi data valid to sck shift edge 3×Tsysclk -- ns Tsd slvsel falling edge to mosi data valid 4×Tsysclk -- ns Tmsfc slvsel falling edge to first sck edge (Tmckh+Tmckl)/2-- ns

Tmsrc last sck edge to slvsel rising edge (Tmckh+Tmckl)/2-- ns

Slave mode timing(See figure 2-13,2-14)

Tsckh sck high Time 4×Tsysclk -- ns Tsckl sck low Time 4×Tsysclk -- ns Tsd slvsel falling edge to Miso valid data time 0 4xTsysclk ns

Ts Mosi Data valid to sck sample edge 0 -- ns

Th sck sample edge to Mosi data change 4×Tsysclk -- ns To sck shift edge to Miso data change 0 4xTsysclk ns

Tsfc slvsel falling edge to first sck edge 4×Tsysclk -- ns Tsrc last sck edge to slvsel rising edge 4×Tsysclk -- ns *Tsysclk is equal to one period of the device system clock

3ELECTRICAL SPECIFICATIONS

3.1Absolute Maximum Ratings

Table 3-1 Absolute Maximum Ratings

Item Symbol Unit Value Note Power Supply Voltage 1 VDDA - VSSA V -0.3 ~ +3.6 1, 2

Power Supply Voltage 2 VDD3 – VSS V -0.3 ~ +3.6 1, 3

I/O Power Supply Voltage Vt V -0.3 ~ IOVCC + 0.3 1,4

Operating Temperature Topr ℃-40 ~ +85 1

Storage Temperature Tstg ℃-55 ~ +125 1

Notes

1.If used beyond the absolute maximum ratings, FT5x06 may be permanently damaged. It is strongly recommended that the device

be used within the electrical characteristics in normal operations. If exposed to the condition not within the electrical characteristics,

it may affect the reliability of the device.

2.Make sure VDDA(high)≥VSSA (low)

3.Make sure VDD (high)≥VSS (low)

4.IOVCC is set to VDD3 or VDDD by software configuration.

3.2DC Characteristics

Table 3-2 DC Characteristics (VDDA=VDD3=2.8~3.6V, Ta=-40~85℃)

Item Symbol Unit Test Condition Min. Typ. Max. Note Input high-level voltage VIH V 0.7 x IOVCC -- IOVCC

Input low -level voltage VIL V -0.3 -- 0.3 x IOVCC

Output high -level voltage VOH V IOH=-0.1mA 0.7 x IOVCC -- --

Output low -level voltage VOL V IOH=0.1mA -- -- 0.3 x IOVCC

I/O leakage current ILI μA Vin=0~VDDA -1 --

Current consumption （Normal operation mode）Iopr mA

VDDA=VDD3 = 2.8V

Ta=25℃ MCLK=24MHz-- 6

Current consumption （Monitor mode）Imon mA

VDDA=VDD3 = 2.8V

Ta=25℃ MCLK=24MHz-- 4

Current consumption （Sleep mode）Islp mA

VDDA=VDD3 = 2.8V

Ta=25℃ MCLK=24MHz-- 0.03

Step-up output voltage VDD5 V VDDA=VDD3= 2.8V 5 5.25

5.6

Power Supply voltage VDDA

VDD3 V 2.7 2.8~3.6

3.7

3.3AC Characteristics

Table 3-3 AC Characteristics of Oscillators

Item Symbol Unit Test Condition Min. Typ. Max. Note

OSC clock 1 fosc1 MHz VDD3 = 2.8V

Ta=25℃43 48 52

OSC clock 2 fosc2 KHz VDD3 = 2.8V

Ta=25℃29 32 36

Table 3-4 AC Characteristics of TX & RX

Item Symbol Unit Test Condition Min Typ Max Note TX acceptable clock ftx KHz 100 150 270

TX output rise time Ttxr nS -- 20 --

TX output fall time Ttxf nS -- 20 --

RX input voltage Trxi V 1.2 -- 1.6

3.4 I/OPortsCircuits

Figure 3-1 Digital Input & Output Port Circuits Figure 3-2 Digital In/Out Port Circuit

Figure 3-3 Reset Input Port Circuits Figure 3-4 Wake Input Port Circuits

Figure 3-5 INT output Port Circuits Figure 3-6 SCL/SDA Port Circuits

3.5

POWER ON/Reset/Wake Sequence

The GPIO such as Wake, INT and I2C should be pulled down to be low before powering on. The signal of waking up should be set to be high after powering on. INT signal will be sent to the host after initializing all parameters and then start to report points to the host.

Powe r

Figure 3-7 Power on time

Pow er I NT I 2C/

SPI

W akeup Figure 3-8 Power on Sequence

Reset time must be enough to guarantee reliable reset, The time of starting to report point after resetting approach to the time of

starting to report point after powering on.

Pow er I NT I 2C/SPI

RESET

Figure 3-8 Reset Sequence

Wake time must be enough to wake up the system, The time of starting to report point after waking approach to the time of starting to report point after powering on

Pow er I NT I 2C/SPI

W ak eup

Figure 3-8 Wake Sequence

Table 3-5 Power on/Reset/Wake Sequence Parameters

Parameter

Description

Min Max Units Tris Rise time from 0.1VDD to 0.9VDD

-- 10 ms Tpon Time of starting to report point after powering on 300 -- ms Trsi Time of starting to report point after resetting 300 -- ms Trst Reset time

5 -- ms Twai Time of starting to report point after waking 300 -- ms Twak

Wake up time

4 PIN CONFIGURATIONS

Pin List of FT5x06

Table 4-1 Pin Definition of FT5x06

Pin No.

Name

FT5206GE1

FT5306DE4

FT5406EE8

Type Description

VSSA 40 1 1 PWR

Analog ground

NC 1 2 2 Not connected NC 48 3 Not connected TX28 4 O Transmit output pin TX27 5 O Transmit output pin TX26 6 O Transmit output pin TX25 7 O Transmit output pin TX24 8 O Transmit output pin TX23 9 O Transmit output pin TX22 10 O Transmit output pin TX21 11 O Transmit output pin TX20 3 12 O Transmit output pin TX19 4 13 O Transmit output pin TX18 5 14 O Transmit output pin TX17 6 15 O Transmit output pin TX16 7 16 O Transmit output pin TX15 2 8 17 O Transmit output pin TX14

Transmit output pin

TX13 4 10 19 O Transmit output pin TX12 5 11 20 O Transmit output pin TX11 6 12 21 O Transmit output pin TX10 7 13 22 O Transmit output pin TX9 8 14 23 O Transmit output pin TX8 9 15 24 O Transmit output pin TX7 10 16 25 O Transmit output pin TX6 11 17 26 O Transmit output pin TX5 12 18 27 O Transmit output pin TX4 13 19 28 O Transmit output pin TX3 14 20 29 O Transmit output pin TX2 15 21 30 O Transmit output pin TX1 16 22 31 O Transmit output pin

VDD5 17 23 32

PWR internal generated 5V power supply， A 1μF ceramic capacitor to ground is required.

VDD3 18 24 33 PWR Analog power supply

VSS 19 25 34

PWR Analog

ground

VDDD 20 26 35

PWR Digital power supply (1.8V), generated internal. A 1μF ceramic capacitor to ground is required.

TEST_EN 21 27 36 I Test mode enabled at high and float in normal mode GPIO0 37 I/O General Purpose Input/Output port

GPIO1 38 I/O General Purpose Input/Output port

GPIO2 39 I/O General Purpose Input/Output port

GPIO3 40 I/O General Purpose Input/Output port

SSEL/SCL 22 28 41 I/O SPI Slave mode, chip select, active low / I2C clock input SCK 23 29 42 I SPI Slave mode, clock input

MOSI/SDA 24 30 43 I/O SPI Slave mode, data input / I2C data input and output MISO 25 31 44 O SPI Slave mode, data output

/RST 26 32 45 I External Reset, Low is active

WAKE 27 33 46 I External interrupt from the host

INT 28 34 47 O External interrupt to the host

NC 48 Not

connected NC 49 Not

connected NC 50 Not

connected NC 51 Not

connected

VDDA 30 35 52 PWR Analog power supply

RX1 29 36 53 I Receiver input pins

RX2 31 37 54 I Receiver input pins

RX3 32 38 55 I Receiver input pins

RX4 33 39 56 I Receiver input pins

RX5 34 40 57 I Receiver input pins

RX6 35 41 58 I Receiver input pins

RX7 36 42 59 I Receiver input pins

RX8 37 43 60 I Receiver input pins

RX9 38 44 61 I Receiver input pins

RX10 39 45 62 I Receiver input pins

RX11 46 63 I Receiver input pins RX12 47 64 I Receiver input pins RX13 65 I Receiver input pins RX14 66 I Receiver input pins RX15 67 I Receiver input pins RX16 68 I Receiver input pins

FT5206GE1 Package Diagram FT5306DE4 Package Diagram VSSA

TX28

TX27

TX26

TX25

TX24

TX18

TX15

INT

WAKE

SSEL/SCL

/RST

MOSI/SDA

GPIO1

VDDD

PACKAGE INFORMATION

5.1

Package Information of QFN-5x5-40L Package

Millimeter Item

Symbol

Min Typ Max

Total Thickness A 0.7 0.75 0.8

Stand Off

A1 0 0.035 0.05 Mold Thickness A2 ----0.55 0.57

L/F Thickness A3 0.203 REF Lead Width b 0.150.20 0.25 D 5 BSC Body Size E 5 BSC Lead Pitch e 0.4 BSC J 3.5 3.6 3.7 EP Size

K 3.5 3.6 3.7 Lead Length

L 0.350.4 0.45

Package Edge Tolerance aaa 0.1 Mold Flatness bbb 0.1

Co Planarity ccc 0.08 Lead Offset ddd 0.1 0.1

5.2Package Information of QFN-6x6-48L Package

Millimeter

Item Symbol

Min Typ Max Total Thickness A 0.70.75 0.8

Stand Off A1 0 0.035 0.05

Mold Thickness A2 ----0.55 0.57

L/F Thickness A3 0.203 REF

Lead Width b 0.150.20 0.25

BSC

D 6

Body Size

BSC

E 6

Lead Pitch e 0.4

BSC

4.3

J 4.1 4.2

EP Size

4.3

K 4.1 4.2

Lead Length L 0.350.4 0.45

Package Edge Tolerance aaa 0.1

Mold Flatness bbb 0.1

Co Planarity ccc 0.08

Lead Offset ddd 0.1

5.3Package Information of QFN-8x8-68L Package

Millimeter

Item Name Symbol

Min Typ Max

Total Thickness A 0.7 0.75 0.8

Stand Off A1 0 0.035 0.05

Mold Thickness A2 ---- 0.55 0.57

L/F Thickness A3 0.203 REF

Lead Width b 0.15 0.20 0.25

D 8

BSC

Body Size

BSC

E 8

Lead Pitch e 0.4 BSC

6.3

6.2

J 6.1

EP Size

6.3

6.2

K 6.1

Lead Length L 0.35 0.4 0.45

Package Edge Tolerance aaa 0.1

Mold Flatness bbb 0.1

Coplanarity ccc

0.08

Lead Offset ddd 0.1

5.4

Order Information

QFN

40Pin(5 * 5 )/48Pin( 6 * 6 )/68Pin ( 8 * 8 )

Package Type

0.75 - P0.4

Product Name FT5206GE1/ FT5306DE4/FT5406EE8

Note:

1). The last two letters in the product name indicate the package type and lead pitch and thickness. 2). The second last letter indicates the package type. D : QFN-6*6 , E : QFN-8*8, G : QFN-5*5

3). The last letter indicates the lead pitch and thickness. E : 0.75 - P0.4 Product Name Package Type # TX Pins

# RX Pins

FT5206GE1 FT5306DE4 FT5406EE8

QFN-40L QFN-48L QFN-68L

15 20 28

10 12 16

FT5x06 电容触摸屏控制器

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