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CH7317B datasheet rev1.1

CH7317B datasheet rev1.1
CH7317B datasheet rev1.1

CH7317B Chrontel

CH7317B SDVO? / RGB DAC

Features General Description

?Supporting analog RGB outputs for a display monitor

?Supporting maximum pixel rate of 165MP/s or graphics resolutions up to 1920x1200*

?High-speed SDVO? (1G~2Gbps) AC-coupled serial differential RGB inputs

?Supporting monitor connection detection ?Programmable power management

?Fully programmable through serial port ?Configuration through Intel? SDVO Opcode ??Offered in 64-pin LQFP package and 64-pin QFN package

* Reduced Blanking

? Intel? Proprietary. The CH7317B is a Display Controller device interfaces seamlessly to HDTV or PC monitors that is equipped with a VGA RGB interface display connector. Its input port, complied with Intel SDVO Specification 1.2, can accept a digital graphics, high-speed, AC-coupled, serial-differential RGB input signal, and convert it to analog RGB signal for driving the display.

The CH7317B supports maximum pixel rate of 165MP/s and is capable of displaying up to 1920x1200 resolution with reduced blanking. The built-in serial port controller will allow the graphics chipset to obtain the monitor’s EDID information or communicate with CH7317B internal registers through SDVO Opcodes. In addition, the transmitter is designed with a monitor connection detection algorithm that allows the graphics chipset to read back the connection status through CH7317B internal registers.

The CH7317B provides the Boundary-scan test to help system developers to check the interconnection between chip I/O and the printed circuit board for faults. When the device is powered down by the graphics chipset, its current consumption is less than 100uA. The CH7317B is available in 64-pin LQFP and 64-pin QFN packages.

SDVO_

SDVO_R(+,-) SDVO_G(+,-) SDVO_B(+,-)

SPC

SPD

RESET*

ISET

SC_PROM

SD_PROM

AS

SC_DDC

SD_DDC

VSYNC,

HSYNC

DAC0

DAC1

DAC2 Figure 1: Functional Block Diagram

Table of Contents

1.0Pin-Out____________________________________________________________________4 1.1Package Diagram___________________________________________________________________4

1.2Pin Description_____________________________________________________________________6

2.0Functional Description________________________________________________________8 2.1Input Interface______________________________________________________________________8 2.2VGA Output Operation_______________________________________________________________8

2.3Command Interface_________________________________________________________________9

3.0Register Control____________________________________________________________12

4.0Electrical Specifications______________________________________________________13 4.1Absolute Maximum Ratings__________________________________________________________13 4.2Recommended Operating Conditions___________________________________________________13 4.3Electrical Characteristics____________________________________________________________14 4.4DC Specifications__________________________________________________________________14

4.5AC Specifications__________________________________________________________________16

5.0Package Dimensions_________________________________________________________17

6.0Revision History____________________________________________________________19

Figures and Tables

List of Figures

Figure 1: Functional Block Diagram (1)

Figure 2: 64-Pin LQFP Package (4)

Figure 3: 64-Pin QFN Package (5)

Figure 4: Control Bus Switch (10)

Figure 5: NAND Tree Connection (10)

Figure 6: 64 Pin LQFP Package (17)

Figure 7: 64 Pin QFN Package (8 X 8 mm) (18)

List of Tables

Table 1: Pin Description (6)

Table 2: CH7317B supported Pixel Rates, Clock Rates, Data Transfer Rates and Fill Patterns (8)

Table 3: Various VGA resolutions (9)

Table 4: Video DAC Configurations for CH7317B (9)

Table 5: Signal Order in the NAND Tree Testing (11)

Table 6: Signals not Tested in NAND Test besides power pins (11)

Table 7: Revisions (19)

Figure 5: NAND Tree Connection Set BSCAN =1; (internal weak pull low)

Set all signals listed in to 1.

3.0Register Control

The CH7317B is controlled via a serial control port. The serial bus uses only the SC clock to latch data into registers, and does not use any internally generated clocks so that the device can be written to in all power down modes. The device will retain all register values during power down modes.

Registers 00h to 11h are reserved for Opcode use. All registers except bytes 00h to 11h are reserved for internal factory use. For details regarding Intel? SDVO Opcodes, please contact Intel?.

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