W9412G6IH-5;中文规格书,Datasheet资料
2M × 4 BANKS × 16 BITS DDR SDRAM
Table of Contents-
1.GENERAL DESCRIPTION (4)
2.FEATURES (4)
3.KEY PARAMETERS (5)
4.PIN CONFIGURATION (6)
5.PIN DESCRIPTION (7)
6.BLOCK DIAGRAM (8)
7.FUNCTIONAL DESCRIPTION (9)
7.1Power Up Sequence (9)
7.2Command Function (10)
7.2.1Bank Activate Command (10)
7.2.2Bank Precharge Command (10)
7.2.3Precharge All Command (10)
7.2.4Write Command (10)
7.2.5Write with Auto-precharge Command (10)
7.2.6Read Command (10)
7.2.7Read with Auto-precharge Command (10)
7.2.8Mode Register Set Command (11)
7.2.9Extended Mode Register Set Command (11)
7.2.10No-Operation Command (11)
7.2.11Burst Read Stop Command (11)
7.2.12Device Deselect Command (11)
7.2.13Auto Refresh Command (11)
7.2.14Self Refresh Entry Command (12)
7.2.15Self Refresh Exit Command (12)
7.2.16Data Write Enable /Disable Command (12)
7.3Read Operation (12)
7.4Write Operation (13)
7.5Precharge (13)
7.6Burst Termination (13)
7.7Refresh Operation (13)
7.8Power Down Mode (14)
7.9Input Clock Frequency Change during Precharge Power Down Mode (14)
7.10Mode Register Operation (14)
7.10.1Burst Length field (A2 to A0) (14)
7.10.2Addressing Mode Select (A3) (15)
7.10.3CAS Latency field (A6 to A4) (16)
7.10.4DLL Reset bit (A8) (16)
7.10.5Mode Register/Extended Mode register change bits (BA0, BA1) (16)
7.10.6Extended Mode Register field (16)
7.10.7Reserved field (16)
8.OPERATION MODE (17)
8.1Simplified Truth Table (17)
8.2Function Truth Table (18)
8.3Function Truth Table for CKE (21)
8.4Simplified Stated Diagram (22)
9.ELECTRICAL CHARACTERISTICS (23)
9.1Absolute Maximum Ratings (23)
9.2Recommended DC Operating Conditions (23)
9.3Capacitance (24)
9.4Leakage and Output Buffer Characteristics (24)
9.5DC Characteristics (25)
9.6AC Characteristics and Operating Condition (26)
9.7AC Test Conditions (27)
10.SYSTEM CHARACTERISTICS FOR DDR SDRAM (30)
10.1Table 1: Input Slew Rate for DQ, DQS, and DM (30)
10.2Table 2: Input Setup & Hold Time Derating for Slew Rate (30)
10.3Table 3: Input/Output Setup & Hold Time Derating for Slew Rate (30)
10.4Table 4: Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate (30)
10.5Table 5: Output Slew Rate Characteristics (X16 Devices only) (30)
10.6Table 6: Output Slew Rate Matching Ratio Characteristics (31)
10.7Table 7: AC Overshoot/Undershoot Specification for Address and Control Pins (31)
10.8Table 8: Overshoot/Undershoot Specification for Data, Strobe, and Mask Pins (32)
10.9System Notes: (33)
11.TIMING WAVEFORMS (35)
11.1Command Input Timing (35)
11.2Timing of the CLK Signals (35)
11.3Read Timing (Burst Length = 4) (36)
11.4Write Timing (Burst Length = 4) (37)
11.5DM, DATA MASK (W9412G6IH) (38)
11.6Mode Register Set (MRS) Timing (39)
11.7Extend Mode Register Set (EMRS) Timing (40)
11.8Auto-precharge Timing (Read Cycle, CL = 2) (41)
11.9Auto-precharge Timing (Read cycle, CL = 2), continued (42)
11.10Auto-precharge Timing (Write Cycle) (43)
11.11Read Interrupted by Read (CL = 2, BL = 2, 4, 8) (44)
11.12Burst Read Stop (BL = 8) (44)
11.13Read Interrupted by Write & BST (BL = 8) (45)
11.14Read Interrupted by Precharge (BL = 8) (45)
11.15Write Interrupted by Write (BL = 2, 4, 8) (46)
11.16Write Interrupted by Read (CL = 2, BL = 8) (46)
11.17Write Interrupted by Read (CL = 3, BL = 4) (47)
11.18Write Interrupted by Precharge (BL = 8) (47)
11.19 2 Bank Interleave Read Operation (CL = 2, BL = 2) (48)
11.20 2 Bank Interleave Read Operation (CL = 2, BL = 4) (48)
11.21 4 Bank Interleave Read Operation (CL = 2, BL = 2) (49)
11.22 4 Bank Interleave Read Operation (CL = 2, BL = 4) (49)
11.23Auto Refresh Cycle (50)
11.24Precharged/Active Power Down Mode Entry and Exit Timing (50)
11.25Input Clock Frequency Change during Precharge Power Down Mode Timing (50)
11.26Self Refresh Entry and Exit Timing (51)
12.Package Specification (52)
12.166L TSOP – 400 mil (52)
13.REVISION HISTORY (53)
1. GENERAL DESCRIPTION
W9412G6IH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR SDRAM); organized as 2M words × 4 banks × 16 bits. W9412G6IH delivers a data bandwidth of up to 500M words per second (-4). To fully comply with the personal computer industrial standard, W9412G6IH is sorted into the following speed grades: -4, -5, -5I, -6 and -6I. The -4 is compliant to the DDR500/CL3 and CL4 specification. The -5/-5I is compliant to the DDR400/CL3 specification (the -5I grade which is guaranteed to support -40°C ~ 85°C). The -6/-6I is compliant to the DDR333/CL2.5 specification (the -6I grade which is guaranteed to support -40°C ~ 85°C).
All Input reference to the positive edge of CLK (except for DQ, DM and CKE). The timing reference point for the differential clock is when the CLK and CLK signals cross during a transition. Write and Read data are synchronized with the both edges of DQS (Data Strobe).
By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W9412G6IH is ideal for main memory in high performance applications.
2. FEATURES
? 2.5V ±0.2V Power Supply for DDR333/400
? 2.5V ±0.1V Power Supply for DDR500
?Up to 250 MHz Clock Frequency
?Double Data Rate architecture; two data transfers per clock cycle
?Differential clock inputs (CLK and CLK)
?DQS is edge-aligned with data for Read; center-aligned with data for Write
?CAS Latency: 2, 2.5, 3 and 4
?Burst Length: 2, 4 and 8
?Auto Refresh and Self Refresh
?Precharged Power Down and Active Power Down
? Write Data Mask
?Write Latency = 1
?15.6μS Refresh interval (4K/64 mS Refresh)
?Maximum burst refresh cycle: 8
? Interface: SSTL_2
?Packaged in TSOP II 66-pin, using Lead free materials with RoHS compliant
3. KEY PARAMETERS
SYMBOL DESCRIPTION MIN./MAX.
-4 -5/-5I -6/-6I Min. - 7.5 nS 7.5 nS CL = 2 Max. - 12 nS 12 nS Min. - 6 nS 6 nS CL = 2.5
Max. - 12 nS 12 nS Min. 4 nS 5 nS 6 nS CL = 3 Max.
12 nS
12 nS
12 nS Min. 4 nS - - t CK
Clock Cycle Time
CL = 4
Max. 12 nS - - t RAS Active to Precharge Command Period Min. 40 nS 40 nS 42 nS t RC
Active to Ref/Active Command Period Min. 48 nS 50 nS 54 nS I DD0
Operating Current:
One Bank Active-Precharge Max. 130 mA 130 mA 120 mA I DD1 Operating Current:
One Bank Active-Read-Precharge Max. 140 mA 140 mA 130 mA I DD4R Burst Operation Read Current Max. 185 mA 180 mA 170 mA I DD4W
Burst Operation Write Current Max. 185 mA 180 mA 170 mA I DD5
Auto Refresh Current Max. 200 mA 200 mA 190 mA I DD6
Self Refresh Current
Max.
3 mA
3 mA
3 mA
4. PIN CONFIGURATION
V SS DQ15V SSQ DQ14DQ13V DDQ DQ12DQ11V SSQ DQ10DQ9V DDQ DQ8V SS NC UDQS CLK CKE A11A9A8A7A6A5A4V SS
666564636261605958575655545352515049484746454443424140123456789101112131415161718192021222324252627V DD DQ0V DDQ DQ1DQ2V SSQ DQ3DQ4V DDQ DQ5DQ6V SSQ DQ7NC V DDQ BA0BA1A10/AP
A0A1A2A3CS RAS CAS WE 282930313233
393837363534
V DD
LDM NC LDQS NC V DD NC V SSQ NC NC NC CLK UDM V REF
5. PIN DESCRIPTION
6. BLOCK DIAGRAM
7. FUNCTIONAL DESCRIPTION
7.1 Power Up Sequence
(1) Apply power and attempt to CKE at a low state (≤0.2V), all other inputs may be undefined
1) Apply V DD before or at the same time as V DDQ.
2) Apply V DDQ before or at the same time as V TT and V REF.
(2) Start Clock and maintain stable condition for 200 μS (min.).
(3) After stable power and clock, apply NOP and take CKE high.
(4) Issue precharge command for all banks of the device.
(5) Issue EMRS (Extended Mode Register Set) to enable DLL and establish Output Driver Type.
(6) Issue MRS (Mode Register Set) to reset DLL and set device to idle with bit A8.
(An additional 200 cycles(min) of clock are required for DLL Lock before any executable command applied.)
(7) Issue precharge command for all banks of the device.
(8) Issue two or more Auto Refresh commands.
(9) Issue MRS-Initialize device operation with the reset DLL bit deactivated A8 to low.
Initialization sequence after power-up
7.2 Command Function
7.2.1 Bank Activate Command
(RAS =“L”, CAS =“H”, WE= “H”, BA0, BA1 = Bank, A0 to A11 = Row Address)
The Bank Activate command activates the bank designated by the BA (Bank address) signal. Row addresses are latched on A0 to A11 when this command is issued and the cell data is read out of the sense amplifiers. The maximum time that each bank can be held in the active state is specified as t RAS (max). After this command is issued, Read or Write operation can be executed.
7.2.2 Bank Precharge Command
(RAS =“L”, CAS =“H”, WE= “L”, BA0, BA1 = Bank, A10 = “L”, A0 to A9, A11 = Don’t Care) The Bank Precharge command percharges the bank designated by BA. The precharged bank is switched from the active state to the idle state.
7.2.3 Precharge All Command
(RAS =“L”, CAS =“H”, WE= “L”, BA0, BA1 = Don’t Care, A10 = “H”, A0 to A9, A11 = Don’t Care)
The Precharge All command precharges all banks simultaneously. Then all banks are switched to the idle state.
Command
7.2.4 Write
(RAS =“H”, CAS =“L”, WE= “L”, BA0, BA1 = Bank, A10 = “L”, A0 to A8 = Column Address) The write command performs a Write operation to the bank designated by BA. The write data are latched at both edges of DQS. The length of the write data (Burst Length) and column access sequence (Addressing Mode) must be in the Mode Register at power-up prior to the Write operation.
7.2.5 Write with Auto-precharge Command
(RAS =“H”, CAS =“L”, WE= “L”, BA0, BA1 = Bank, A10 = “H”, A0 to A8 = Column Address) The Write with Auto-precharge command performs the Precharge operation automatically after the Write operation. This command must not be interrupted by any other commands.
Command
7.2.6 Read
(RAS =“H”, CAS =“L”, WE= “H”, BA0, BA1 = Bank, A10 = “L”, A0 to A8 = Column Address) The Read command performs a Read operation to the bank designated by BA. The read data are synchronized with both edges of DQS. The length of read data (Burst Length), Addressing Mode and CAS Latency (access time from CAS command in a clock cycle) must be programmed in the Mode Register at power-up prior to the Read operation.
7.2.7 Read with Auto-precharge Command
(RAS= “H”, CAS= ”L”,WE= ”H”, BA0, BA1 = Bank, A10 = ”H”, A0 to A8 = Column Address) The Read with Auto-precharge command automatically performs the Precharge operation after the Read operation.
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W9412G6IH-5