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SiRFatlasIV 资料

SiRFatlasIV 资料
SiRFatlasIV 资料

Datasheet

SiRFatlasIV

June 2010

Document Number: CS-106205-DS

Issue 5

O VERVIEW

T he SiRFatlasIV TM processor is the next generation in high performance and low cost navigation. Using advanced process technology and with a large number of hardware accelerators, SiRFatlasIV provides better system and GPS performances with a high-speed ARM?-1136 RISC processor core and a 16-bit DSP core. This state-of-the-art processor supports GPS baseband and higher bandwidth SDRAM memory controllers, offering powerful solutions for performance-intense navigation, multimedia and graphics applications.

F EATURES

?500MHz 32-bit RISC (ARM1136)

–16KB I-Cache

–16KB D-Cache

–16KB D-TCM

–16KB I-TCM

–Low Power advanced 65nm process ?250MHz 16-bit DSP

–With high performance hardware FFT

–Hardware Energy Peak Detection

(EPD)

–Idle mode

–12Kx24bit program memory

–20Kx16bit data memory

?Memory controller support:

– 1.8V 333MHz Mobile-DDR

– 2.5V 32-bit 400MHz DDR1

–Max. size 128MB

?64-channel GPS baseband with hardware match filter

?USB-2.0 Hi-Speed controller

–USB 2.0 High-Speed On-The-Go

(OTG) controller serves as either a

USB Host or a USB Device controller

with on-chip PHY

?8-bit NAND flash interface

–8-bit BCH Hardware ECC by 512 byte

–Direct boot from SLC or MLC NAND

Flash

–Supports page size 512 byte, 2K byte, and 4K byte ?8/16-bit Async-ROM interface for CPU interface LCD

–One address line

–FIFO mode operation

?4-slot SD/SDIO/MMC+ controller

–Direct boot from SD/MMC+ Managed NAND

–Four SDHC/SD 2.0/MMC4.2 ports

–SDIO support for WiFi, Bluetooth, and DVB-T/DVB-H/T-DMB/S-DMB

?8/16-bit LCD interface

?Video input port

–8/10-bit

–Raw RGB, RGB, YUV data format

–CCIR-601

–CCIR-656

?Audio CODEC interface

–AC97 V2.2 standard

–I2S master/slave mode

?One SPI port

?Two Universal Serial Ports (USP)

?Two UART ports

?Two I2C ports

?Four PWM pins

?12mmx12mm, 0.65mm pitch, 292-pin TFBGA package

B LOCK D IAGRAM

Figure 1: SiRFatlasIV Block Diagram

P ACKAGE AND P IN S PECIFICATION

Mechanical Drawing of Package

Figure 2: Top View

Figure 3: Side View

Figure 4: Bottom View

Figure 5: Notes for Package Information

Pin Sequence and Ball Assignment

Table 1: Pin Status

1 This pad can be used to output XIN or XINW. Refer to the register description of PWR_C TRL in the chapter of Pow er Management.

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