AK5393VSP-E2;中文规格书,Datasheet资料
n Ordering Guide
AK5393-VS –10 ~ +70°C28pin SOP
AKD5393AK5393 Evaluation Board
n Pin Layout
VREFR
GNDR
VCOMR
AINR+
AINR-
VA
AGND
BGND
TEST
HPFE
DFS
MCLK
FSYNC
SDATA
n Compatibility with AK5392
AK5392AK5393
Pin 18CMODE DFS
fs (max)54kHz108kHz
MCLK (DFS ="L"@fs=48kHz)256fs/384fs256fs
MCLK (DFS ="H"@fs=96kHz)N/A128fs
PIN/FUNCTION
14SCLK I/O Serial Data Clock Pin
Data is clocked out on the falling edge of SCLK.
Slave mode:
SCLK requires more than 48fs clock.
Master mode:
SCLK outputs a 128fs(DFS="L") or 64fs(DFS="H") clock.
SCLK stays "L" during reset.
15SDATA O Serial Data Output Pin
MSB first, 2's complement. SDATA stays "L" during reset.
16FSYNC I/O Frame Synchronization Signal Pin
Slave mode:
When "H", the data bits are clocked out on SDATA. In I2S mode, FSYNC is
don’t care.
Master mode:
FSYNC outputs 2fs clock. FSYNC stays "L" during reset.
17MCLK I Master Clock Input Pin
256fs at DFS="L", 128fs at DFS="H".
18DFS I Double Speed Sampling Mode Pin
"L": Normal Speed
"H": Double Speed
19HPFE I High Pass Filter Enable Pin
"L": Disable
"H": Enable
20TEST I Test Pin (pull-down pin)
Should be connected to GND.
21BGND-Substrate Ground Pin, 0V
22AGND-Analog Ground Pin, 0V
23VA-Analog Supply Pin, 5V
24AINR-I Rch Analog negative input Pin
25AINR+I Rch Analog positive input Pin
26VCOMR O Rch Common Voltage Pin, 2.75V
27GNDR-Rch Reference Ground Pin, 0V
28VREFR O Rch Reference Voltage Pin, 3.75V
Normally connected to GNDR with a 10μF electrolytic capacitor and a 0.1μF
ceramic capacitor
Note: All digital inputs should not be left floating.
ABSOLUTE MAXIMUM RATINGS
(AGND,BGND,DGND=0V; Note 1)
Parameter Symbol min max Units
Power Supplies: Analog
Digital
|BGND-DGND| (Note 2)
VA
VD
?GND
-0.3
-0.3
-
6.0
6.0
0.3
V
V
V
Input Current, Any Pin Except Supplies IIN-±10mA Analog Input Voltage VINA-0.3VA+0.3V Digital Input Voltage VIND-0.3VD+0.3V Ambient Temperature (power applied)Ta-1070°C Storage Temperature Tstg-65150°C Notes: 1. All voltages with respect to ground.
2. AGND, BGND and DGND must be connected to the same analog ground plane.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AGND,BGND,DGND=0V; Note 1)
Parameter Symbol min typ max Units
Power Supplies: Analog (Note 3) Digital VA
VD
4.75
3.0
5.0
3.3
5.25
5.25
V
V
Notes: 1. All voltages with respect to ground.
3. The power up sequence between VA and VD is not critical.
* AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
ANALOG CHARACTERISTICS
(Ta=25°C; VA=5.0V; VD=3.3V; AGND,BGND,DGND=0V; fs=48kHz; Signal Frequency=1kHz;
24bit Output; Measurement frequency=10Hz~20kHz; unless otherwise specified)
Parameter min typ max Units Resolution 24Bits Analog Input Characteristics:
fs=48kHz-1dBFS
-20dBFS
-60dBFS 98
-
-
105
94
54
dB
dB
dB
S/(N+D)
fs=96kHz BW=40kHz -1dBFS
-20dBFS
-60dBFS
96
-
-
103
85
45
dB
dB
dB
Dynamic Range (-60dBFS with A-Weighted )112117dB S/N ( A-Weighted )112117dB Interchannel Isolation110120dB Interchannel Gain Mismatch0.10.5dB Gain Drift150ppm/°C
Offset Error after calibration, HPF=OFF
after calibration, HPF=ON ±200
±1
±1000LSB24
LSB24
Offset Drift (HPF=OFF)-±10-LSB24/°C Offset Calibration Range (HPF=OFF)±50mV Input Voltage (AIN+)-(AIN-)±2.3±2.45±2.6V Input Impedance 2.44k?Power Supplies
Power Supply Current
VA
VD (fs=48kHz; DFS="L") (fs=96kHz; DFS="H")90
6
9
130
9
14
mA
mA
mA
Power Dissipation470680mW Power Supply Rejection (Note 4)70dB
Note: 4. DC to 26kHz. 110dB(typ) beyond 26kHz.
FILTER CHARACTERISTICS(fs=48kHz)
(Ta=25°C; VA=5.0V±5%; VD=3.0~5.25V; fs=48kHz, DFS="L")
Parameter Symbol min typ max Units ADC Digital Filter(Decimation LPF):
Passband (Note 5)PB021.768kHz Stopband (Note 5)SB26.232kHz Passband Ripple PR±0.001dB Stopband Attenuation (Note 6)SA110dB Group Delay Distortion?GD0us Group Delay (Note 7)GD38.71/fs ADC Digital Filter(HPF):
Frequency response (Note 5)-3dB
-0.1dB FR 1.0
6.5
Hz
Hz
FILTER CHARACTERISTICS(fs=96kHz)
(Ta=25°C; VA=5.0V±5%; VD=3.0~5.25V; fs=96kHz, DFS="H")
Parameter Symbol min typ max Units ADC Digital Filter(Decimation LPF):
Passband (Note 5)PB043.536kHz Stopband (Note 5)SB52.464kHz Passband Ripple PR±0.003dB Stopband Attenuation (Note 8)SA110dB Group Delay Distortion?GD0us Group Delay (Note 7)GD38.81/fs ADC Digital Filter(HPF):
Frequency response (Note 5)-3dB
-0.1dB FR 2.0
13.0
Hz
Hz
Notes: 5. The passband and stopband frequencies scale with fs.
6. The analog modulator samples the input at 6.144MHz for an output word rate of 48kHz.
There is no rejection of input signals which are multiples of the sampling frequency
(that is: there is no rejection for n x 6.144MHz ± 21.768kHz, where n=1,2,3···).
7. The calculating delay time which occurred by digital filtering. This time is from the input of analog signal
to setting the 24bit data of both channels to the output register.
40.7/fs(DFS="L"),40.8/fs(DFS="H")typ. at HPF:ON.
8. The analog modulator samples the input at 6.144MHz for an output word rate of 96kHz.
There is no rejection of input signals which are multiples of the sampling frequency
(that is: there is no rejection for n x 6.144MHz ± 43.536kHz, where n=1,2,3···).
DIGITAL CHARACTERISTICS
(Ta=25°C; VA=5.0V±5%; VD=3.0 ~ 5.25V)
Parameter Symbol min typ max Units
High-Level Input Voltage Low-Level Input Voltage VIH
VIL
70%VD
-
-
-
-
30%VD
V
V
High-Level Output Voltage Iout=-20μA Low-Level Output Voltage Iout=20μA VOH
VOL
VD-0.1
-
--
0.1
V
V
Input Leakage Current Iin--±10μA
SWITCHING CHARACTERISTICS
Notes: 9. Refer to Serial Data interface.
10. Specified LRCK edges not to coincide with the rising edges of SCLK.
11. The number of the LRCK rising edges after RST brought high at DFS="L". The value is in master mode.
In slave mode it becomes one LRCK clock(1/fs) longer. When DFS="H", tRCF=17408 and tRTV=17920.
n Timing Diagram
LRCK
SCLK
SDATA
Serial Data Timing (Slave Mode, FSYNC="H")
LRCK
SCLK
SDATA
FSYNC
Serial Data Timing (Slave Mode)
LRCK
SCLK
SDATA
Serial Data Timing (I 2S Slave Mode, FSYNC = Don't Care)
LRCK
SCLK
SDATA
FSYNC
Serial Data Timing (Master Mode & I 2S Master Mode, DFS ="L")
RST
SDATA
CAL
Reset & Calibration Timing
分销商库存信息: AKM
AK5393VSP-E2