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cc2541 datasheet

CC2541

https://www.sodocs.net/doc/9f4508631.html, SWRS110A–JANUARY2012–REVISED FEBRUARY2012 2.4-GHz Bluetooth?low energy and Proprietary System-on-Chip

Check for Samples:CC2541

FEATURES

?RF?Microcontroller

– 2.4-GHz Bluetooth low energy Compliant–High-Performance and Low-Power8051 and Proprietary RF System-on-Chip Microcontroller Core With Code Prefetch –Supports250-kbps,500-kbps,1-Mbps,–In-System-Programmable Flash,128-or 2-Mbps Data Rates256-KB

–Excellent Link Budget,Enabling–8-KB RAM With Retention in All Power Long-Range Applications Without External Modes

Front End–Hardware Debug Support –Programmable Output Power up to0dBm–Extensive Baseband Automation,Including –Excellent Receiver Sensitivity(–94dBm at Auto-Acknowledgment and Address 1Mbps),Selectivity,and Blocking Decoding

Performance–Retention of All Relevant Registers in All –Suitable for Systems Targeting Compliance Power Modes

With Worldwide Radio Frequency?Peripherals

Regulations:ETSI EN300328and EN300–Powerful Five-Channel DMA

440Class2(Europe),FCC CFR47Part15

–General-Purpose Timers(One16-Bit,Two (US),and ARIB STD-T66(Japan)

8-Bit)

?Layout

–IR Generation Circuitry –Few External Components

–32-kHz Sleep Timer With Capture –Reference Design Provided

–Accurate Digital RSSI Support –6-mm×6-mm QFN-40Package

–Battery Monitor and Temperature Sensor –Pin-Compatible With CC2540(When Not

–12-Bit ADC With Eight Channels and Using USB or I2C)

Configurable Resolution

?Low Power

–AES Security Coprocessor –Active-Mode RX Down to:17.9mA

–Two Powerful USARTs With Support for –Active-Mode TX(0dBm):18.2mA Several Serial Protocols

–Power Mode1(4-μs Wake-Up):270μA–23General-Purpose I/O Pins

–Power Mode2(Sleep Timer On):1μA(21×4mA,2×20mA)

–Power Mode3(External Interrupts):0.5μA–I2C interface

–Wide Supply-Voltage Range(2V–3.6V)–2I/O Pins Have LED Driving Capabilities ?TPS62730Compatible Low Power in Active–Watchdog Timer

Mode

–Integrated High-Performance Comparator –RX Down to:14.7mA(3-V supply)

?Development Tools

–TX(0dBm):14.3mA(3-V supply)

–CC2541Evaluation Module Kit

(CC2541EMK)

–CC2541Mini Development Kit

(CC2541DK-MINI)

–SmartRF?Software

–IAR Embedded Workbench?Available

Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

is a trademark of Bluetooth SIG,Inc..

ZigBee is a registered trademark of ZigBee Alliance.

PRODUCTION DATA information is current as of publication date.Copyright?2012,Texas Instruments Incorporated Products conform to specifications per the terms of the Texas

Instruments standard warranty.Production processing does not

necessarily include testing of all parameters.

CC2541

SWRS110A–JANUARY2012–REVISED https://www.sodocs.net/doc/9f4508631.html, SOFTWARE FEATURES CC2541WITH TPS62730

?Bluetooth v4.0Compliant Protocol Stack for?TPS62730is a2-MHz Step-Down Converter Single-Mode BLE Solution With Bypass Mode

–Complete Power-Optimized Stack,?Extends Battery Lifetime by up to20% Including Controller and Host?Reduced Current in All Active Modes

–GAP–Central,Peripheral,Observer,or?30-nA Bypass Mode Current to Support Broadcaster(Including Combination Low-Power Modes

Roles)?RF Performance Unchanged –ATT/GATT–Client and Server?Small Package Allows for Small Solution Size –SMP–AES-128Encryption and?CC2541Controllable

Decryption

–L2CAP DESCRIPTION

–Sample Applications and Profiles The CC2541is a power-optimized true

system-on-chip(SoC)solution for both Bluetooth low –Generic Applications for GAP Central

energy and proprietary 2.4-GHz applications.It and Peripheral Roles

enables robust network nodes to be built with low –Proximity,Accelerometer,Simple Keys,total bill-of-material costs.The CC2541combines the and Battery GATT Services excellent performance of a leading RF transceiver –More Applications Supported in BLE with an industry-standard enhanced8051MCU,

in-system programmable flash memory,8-KB RAM, Software Stack

and many other powerful supporting features and –Multiple Configuration Options

peripherals.The CC2541is highly suited for systems –Single-Chip Configuration,Allowing where ultralow power consumption is required.This is Applications to Run on CC2541specified by various operating modes.Short transition

times between operating modes further enable low –Network Processor Interface for

power consumption.

Applications Running on an External

Microcontroller The CC2541is pin-compatible with the CC2540in

the6-mm×6-mm QFN40package,if the USB is not –BTool–Windows PC Application for

used on the CC2540and the I2C/extra I/O is not used Evaluation,Development,and Test

on the https://www.sodocs.net/doc/9f4508631.html,pared to the CC2540,the

CC2541provides lower RF current consumption.The APPLICATIONS

CC2541does not have the USB interface of the ? 2.4-GHz Bluetooth low energy Systems CC2540,and provides lower maximum output power

in TX mode.The CC2541also adds a HW I2C ?Proprietary2.4-GHz Systems

interface.

?Human-Interface Devices(Keyboard,Mouse,

Remote Control)The CC2541is pin-compatible with the CC2533

RF4CE-optimized IEEE802.15.4SoC.

?Sports and Leisure Equipment

The CC2541comes in two different versions:?Mobile Phone Accessories

CC2541F128/F256,with128KB and256KB of flash ?Consumer Electronics

memory,respectively.

For the CC2541block diagram,see Figure1.

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P2_4P2_3P2_2P2_1P2_0

P1_4P1_3P1_2P1_1P1_0P1_7P1_6P1_5P0_4P0_3P0_2P0_1P0_0

P0_7P0_6P0_5XOSC_XOSC_SDA SCL

CC2541

https://www.sodocs.net/doc/9f4508631.html,

SWRS110A –JANUARY 2012–REVISED FEBRUARY 2012

This integrated circuit can be damaged by ESD.Texas Instruments recommends that all integrated circuits be handled with appropriate precautions.Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure.Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

Figure 1.Block Diagram

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CC2541

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ABSOLUTE MAXIMUM RATINGS(1)

over operating free-air temperature range(unless otherwise noted)

MIN MAX UNIT Supply voltage All supply pins must have the same voltage–0.3 3.9V Voltage on any digital pin–0.3VDD+0.3≤3.9V Input RF level10dBm Storage temperature range–40125°C

All pins,excluding pins25and26,according to human-body

2kV

model,JEDEC STD22,method A114

All pins,according to human-body model,JEDEC STD22,

ESD(2)1kV

method A114

According to charged-device model,JEDEC STD22,method

500V

C101

(1)Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.These are stress ratings

only,and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)CAUTION:ESD sesnsitive device.Precautions should be used when handling the device in order to prevent permanent damage. RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range(unless otherwise noted)

MIN NOM MAX UNIT Operating ambient temperature range,T A–4085°C Operating supply voltage2 3.6V ELECTRICAL CHARACTERISTICS

Measured on Texas Instruments CC2541EM reference design with T A=25°C and VDD=3V,

1Mbps,GFSK,250-kHz deviation,Bluetooth low energy mode,and0.1%BER

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

RX mode,standard mode,no peripherals active,low MCU

17.9

activity

RX mode,high-gain mode,no peripherals active,low MCU

20.2

activity

TX mode,–20dBm output power,no peripherals active,low

16.8

MCU activity

TX mode,0dBm output power,no peripherals active,low

18.2

MCU activity

Power mode1.Digital regulator on;16-MHz RCOSC and

I core Core current consumption

32-MHz crystal oscillator off;32.768-kHz XOSC,POR,BOD270

and sleep timer active;RAM and register retention

Power mode2.Digital regulator off;16-MHz RCOSC and

μA

32-MHz crystal oscillator off;32.768-kHz XOSC,POR,and1

sleep timer active;RAM and register retention

Power mode3.Digital regulator off;no clocks;POR active;

0.5

RAM and register retention

Low MCU activity:32-MHz XOSC running.No radio or

6.7mA

peripherals.Limited flash access,no RAM access.

Timer1.Timer running,32-MHz XOSC used90

Timer2.Timer running,32-MHz XOSC used90 Peripheral current consumption Timer3.Timer running,32-MHz XOSC used60μA I peri(Adds to core current I core for each

Timer4.Timer running,32-MHz XOSC used70 peripheral unit activated)

Sleep timer,including32.753-kHz RCOSC0.6

ADC,when converting 1.2mA

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GENERAL CHARACTERISTICS

Measured on Texas Instruments CC2541EM reference design with T A=25°C and VDD=3V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT WAKE-UP AND TIMING

Digital regulator on,16-MHz RCOSC and32-MHz crystal

Power mode1→Active4μs

oscillator off.Start-up of16-MHz RCOSC

Digital regulator off,16-MHz RCOSC and32-MHz crystal

Power mode2or3→Active120μs

oscillator off.Start-up of regulator and16-MHz RCOSC

Crystal ESR=16?.Initially running on16-MHz RCOSC,

500μs

with32-MHz XOSC OFF

Active→TX or RX

With32-MHz XOSC initially on180μs

Proprietary auto mode130

RX/TX turnaroundμs

BLE mode150

RADIO PART

RF frequency range Programmable in1-MHz steps23792496MHz

2Mbps,GFSK,500-kHz deviation

2Mbps,GFSK,320-kHz deviation

1Mbps,GFSK,250-kHz deviation

Data rate and modulation format1Mbps,GFSK,160-kHz deviation

500kbps,MSK

250kbps,GFSK,160-kHz deviation

250kbps,MSK

RF RECEIVE SECTION

Measured on Texas Instruments CC2541EM reference design with T A=25°C,VDD=3V,f c=2440MHz PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

2Mbps,GFSK,500-kHz Deviation,0.1%BER

Receiver sensitivity–90dBm Saturation BER<0.1%–1dBm Co-channel rejection Wanted signal at–67dBm–9dB ±2MHz offset,0.1%BER,wanted signal–67dBm–2

In-band blocking rejection±4MHz offset,0.1%BER,wanted signal–67dBm36dB ±6MHz or greater offset,0.1%BER,wanted signal–67dBm41

Including both initial tolerance and drift.Sensitivity better than–67dBm,

Frequency error tolerance(1)–300300kHz 250byte payload.BER0.1%

Symbol rate error Maximum packet length.Sensitivity better than–67dBm,250byte

–120120ppm tolerance(2)payload.BER0.1%

2Mbps,GFSK,320-kHz Deviation,0.1%BER

Receiver sensitivity–86dBm Saturation BER<0.1%–7dBm Co-channel rejection Wanted signal at–67dBm–12dB ±2MHz offset,0.1%BER,wanted signal–67dBm–1

In-band blocking rejection±4MHz offset,0.1%BER,wanted signal–67dBm34dB ±6MHz or greater offset,0.1%BER,wanted signal–67dBm39

Including both initial tolerance and drift.Sensitivity better than–67dBm,

Frequency error tolerance(1)–300300kHz 250byte payload.BER0.1%

Symbol rate error Maximum packet length.Sensitivity better than–67dBm,250byte

–120120ppm tolerance(2)payload.BER0.1%

(1)Difference between center frequency of the received RF signal and local oscillator frequency

(2)Difference between incoming symbol rate and the internally generated symbol rate

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RF RECEIVE SECTION(continued)

Measured on Texas Instruments CC2541EM reference design with T A=25°C,VDD=3V,f c=2440MHz PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

1Mbps,GFSK,250-kHz Deviation,Bluetooth low energy Mode,0.1%BER

High-gain mode–94

Receiver sensitivity(3)(4)dBm Standard mode–88

Saturation(4)BER<0.1%5dBm Co-channel rejection(4)Wanted signal–67dBm–6dB ±1MHz offset,0.1%BER,wanted signal–67dBm–2

±2MHz offset,0.1%BER,wanted signal–67dBm26

In-band blocking rejection(4)dB ±3MHz offset,0.1%BER,wanted signal–67dBm34

>6MHz offset,0.1%BER,wanted signal–67dBm33

Minimum interferer level<2GHz(Wanted signal–67dBm)–21

Out-of-band blocking

Minimum interferer level[2GHz,3GHz](Wanted signal–67dBm)–25dBm rejection(4)

Minimum interferer level>3GHz(Wanted signal–67dBm)–7 Intermodulation(4)Minimum interferer level–36dBm

Including both initial tolerance and drift.Sensitivity better than-67dBm,

Frequency error tolerance(5)–250250kHz 250byte payload.BER0.1%

Symbol rate error Maximum packet length.Sensitivity better than–67dBm,250byte

–8080ppm tolerance(6)payload.BER0.1%

1Mbps,GFSK,160-kHz Deviation,0.1%BER

Receiver sensitivity(7)–91dBm Saturation BER<0.1%0dBm Co-channel rejection Wanted signal10dB above sensitivity level–9dB ±1-MHz offset,0.1%BER,wanted signal–67dBm2

±2-MHz offset,0.1%BER,wanted signal–67dBm24

In-band blocking rejection dB ±3-MHz offset,0.1%BER,wanted signal-–67dBm27

>6-MHz offset,0.1%BER,wanted signal–67dBm32

Including both initial tolerance and drift.Sensitivity better than–67dBm,

Frequency error tolerance(5)–200200kHz 250-byte payload.BER0.1%

Symbol rate error Maximum packet length.Sensitivity better than–67dBm,250-byte

–8080ppm tolerance(6)payload.BER0.1%

500kbps,MSK,0.1%BER

Receiver sensitivity(7)–99dBm Saturation BER<0.1%0dBm Co-channel rejection Wanted signal–67dBm–5dB ±1-MHz offset,0.1%BER,wanted signal–67dBm20

In-band blocking rejection±2-MHz offset,0.1%BER,wanted signal–67dBm27dB >2-MHz offset,0.1%BER,wanted signal–67dBm28

Including both initial tolerance and drift.Sensitivity better than–67dBm,

Frequency error tolerance–150150kHz 250-byte payload.BER0.1%

Maximum packet length.Sensitivity better than–67dBm,250-byte

Symbol rate error tolerance–8080ppm payload.BER0.1%

(3)The receiver sensitivity setting is programmable using a TI BLE stack vendor-specific API command.The default value is standard

mode.

(4)Results based on standard-gain mode.

(5)Difference between center frequency of the received RF signal and local oscillator frequency

(6)Difference between incoming symbol rate and the internally generated symbol rate

(7)Results based on high-gain mode.

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RF RECEIVE SECTION(continued)

Measured on Texas Instruments CC2541EM reference design with T A=25°C,VDD=3V,f c=2440MHz PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 250kbps,GFSK,160kHz Deviation,0.1%BER

Receiver sensitivity(8)–98dBm Saturation BER<0.1%0dBm Co-channel rejection Wanted signal-67dBm–3dB ±1-MHz offset,0.1%BER,wanted signal–67dBm23

In-band blocking rejection±2-MHz offset,0.1%BER,wanted signal–67dBm28dB >2-MHz offset,0.1%BER,wanted signal–67dBm29

Including both initial tolerance and drift.Sensitivity better than–67dBm,

Frequency error tolerance(9)–150150kHz 250-byte payload.BER0.1%

Symbol rate error Maximum packet length.Sensitivity better than–67dBm,250-byte

–8080ppm tolerance(10)payload.BER0.1%

250kbps,MSK,0.1%BER

Receiver sensitivity(11)–99dBm Saturation BER<0.1%0dBm Co-channel rejection Wanted signal-67dBm–5dB ±1-MHz offset,0.1%BER,wanted signal–67dBm20

In-band blocking rejection±2-MHz offset,0.1%BER,wanted signal–67dBm29dB >2-MHz offset,0.1%BER,wanted signal–67dBm30

Including both initial tolerance and drift.Sensitivity better than–67dBm,

Frequency error tolerance–150150kHz 250-byte payload.BER0.1%

Maximum packet length.Sensitivity better than–67dBm,250-byte

Symbol rate error tolerance–8080ppm payload.BER0.1%

ALL RATES/FORMATS

Spurious emission in RX.

f<1GHz–67dBm Conducted measurement

Spurious emission in RX.

f>1GHz–57dBm Conducted measurement

(8)Results based on standard-gain mode.

(9)Difference between center frequency of the received RF signal and local oscillator frequency

(10)Difference between incoming symbol rate and the internally generated symbol rate

(11)Results based on high-gain mode.

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CC2541

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RF TRANSMIT SECTION

Measured on Texas Instruments CC2541EM reference design with T A=25°C,VDD=3V and f c=2440MHz PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Delivered to a single-ended50-Ωload through a balun using

maximum recommended output power setting

Output power dBm

Delivered to a single-ended50-Ωload through a balun using

–20

minimum recommended output power setting

Programmable output power Delivered to a single-ended50-Ωload through a balun using20dB range minimum recommended output power setting

f<1GHz–52dBm Spurious emission conducted f>1GHz–48dBm measurement Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN300328and EN300440Class2(Europe),FCC CFR47Part15(US),and ARIB STD-T66(Japan)

Differential impedance as seen from the RF port(RF_P and RF_N)

Optimum load impedance70+j30Ω

toward the antenna

Designs with antenna connectors that require conducted ETSI compliance at64MHz should insert an LC resonator in front of the antenna https://www.sodocs.net/doc/9f4508631.html,e a1.6-nH inductor in parallel with a1.8-pF capacitor.Connect both from the signal trace to a good RF ground.

CURRENT CONSUMPTION WITH TPS62730

Measured on Texas Instruments CC2541TPA62730EM reference design with T A=25°C,VDD=3V and f c=2440MHz,

1Mbsp,GFSK,250-kHz deviation,Bluetooth?low energy Mode,1%BER(1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

RX mode,standard mode,no peripherals active,low MCU activity,MCU

14.7

at1MHz

RX mode,high-gain mode,no peripherals active,low MCU activity,MCU

16.7

at1MHz

Current consumption mA TX mode,–20dBm output power,no peripherals active,low MCU activity,13.1

MCU at1MHz

TX mode,0dBm output power,no peripherals active,low MCU activity,

14.3

MCU at1MHz

(1)0.1%BER maps to30.8%PER

32-MHz CRYSTAL OSCILLATOR

Measured on Texas Instruments CC2541EM reference design with T A=25°C and VDD=3V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Crystal frequency32MHz

Crystal frequency accuracy

–4040ppm requirement(1)

ESR Equivalent series resistance660?

C0Crystal shunt capacitance17pF

C L Crystal load capacitance1016pF

Start-up time0.25ms

The crystal oscillator must be in power down for a guard

time before it is used again.This requirement is valid for

Power-down guard time3ms

all modes of operation.The need for power-down guard

time can vary with crystal type and load.

(1)Including aging and temperature dependency,as specified by[1]

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32.768-kHz CRYSTAL OSCILLATOR

Measured on Texas Instruments CC2541EM reference design with T A=25°C and VDD=3V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Crystal frequency32.768kHz Crystal frequency accuracy requirement(1)–4040ppm ESR Equivalent series resistance40130k?

C0Crystal shunt capacitance0.92pF

C L Crystal load capacitance1216pF

Start-up time0.4s (1)Including aging and temperature dependency,as specified by[1]

32-kHz RC OSCILLATOR

Measured on Texas Instruments CC2541EM reference design with T A=25°C and VDD=3V.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Calibrated frequency(1)32.753kHz Frequency accuracy after calibration±0.2%

Temperature coefficient(2)0.4%/°C Supply-voltage coefficient(3)3%/V Calibration time(4)2ms

(1)The calibrated32-kHz RC oscillator frequency is the32-MHz XTAL frequency divided by977.

(2)Frequency drift when temperature changes after calibration

(3)Frequency drift when supply voltage changes after calibration

(4)When the32-kHz RC oscillator is enabled,it is calibrated when a switch from the16-MHz RC oscillator to the32-MHz crystal oscillator

is performed while SLEEPCMD.OSC32K_CALDIS is set to0.

16-MHz RC OSCILLATOR

Measured on Texas Instruments CC2541EM reference design with T A=25°C and VDD=3V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Frequency(1)16MHz Uncalibrated frequency accuracy±18%

Calibrated frequency accuracy±0.6%

Start-up time10μs Initial calibration time(2)50μs

(1)The calibrated16-MHz RC oscillator frequency is the32-MHz XTAL frequency divided by2.

(2)When the16-MHz RC oscillator is enabled,it is calibrated when a switch from the16-MHz RC oscillator to the32-MHz crystal oscillator

is performed while SLEEPCMD.OSC_PD is set to0.

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CC2541

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RSSI CHARACTERISTICS

Measured on Texas Instruments CC2541EM reference design with T A=25°C and VDD=3V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

2Mbps,GFSK,320-kHz Deviation,0.1%BER and2Mbps,GFSK,500-kHz Deviation,0.1%BER

Reduced gain by AGC algorithm64

Useful RSSI range(1)dB

High gain by AGC algorithm64

Reduced gain by AGC algorithm79

RSSI offset(1)dBm

High gain by AGC algorithm99

Absolute uncalibrated accuracy(1)±6dB Step size(LSB value)1dB

All Other Rates/Formats

Standard mode64

Useful RSSI range(1)dB

High-gain mode64

Standard mode98

RSSI offset(1)dBm

High-gain mode107

Absolute uncalibrated accuracy(1)±3dB Step size(LSB value)1dB (1)Assuming CC2541EM reference design.Other RF designs give an offset from the reported value.

FREQUENCY SYNTHESIZER CHARACTERISTICS

Measured on Texas Instruments CC2541EM reference design with T A=25°C,VDD=3V and f c=2440MHz

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

At±1-MHz offset from carrier–109

Phase noise,unmodulated carrier At±3-MHz offset from carrier–112dBc/Hz

At±5-MHz offset from carrier–119

ANALOG TEMPERATURE SENSOR

Measured on Texas Instruments CC2541EM reference design with T A=25°C and VDD=3V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Output148012-bit Temperature coefficient 4.5mv/°C Voltage coefficient10.1V

Measured using integrated ADC,internal band-gap voltage

reference,and maximum resolution

Initial accuracy without calibration±10°C Accuracy using1-point calibration±5°C Current consumption when enabled0.5mA COMPARATOR CHARACTERISTICS

T A=25°C,VDD=3V.All measurement results are obtained using the CC2541reference designs,post-calibration.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Common-mode maximum voltage VDD V

Common-mode minimum voltage–0.3

Input offset voltage1mV

Offset vs temperature16μV/°C

Offset vs operating voltage4mV/V

Supply current230nA

Hysteresis0.15mV

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ADC CHARACTERISTICS

T A=25°C and VDD=3V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Input voltage VDD is voltage on AVDD5pin0VDD V

External reference voltage VDD is voltage on AVDD5pin0VDD V

External reference voltage differential VDD is voltage on AVDD5pin0VDD V

Input resistance,signal Simulated using4-MHz clock speed197k?

Full-scale signal(1)Peak-to-peak,defines0dBFS 2.97V

Single-ended input,7-bit setting 5.7

Single-ended input,9-bit setting7.5

Single-ended input,10-bit setting9.3

Single-ended input,12-bit setting10.3

Differential input,7-bit setting 6.5

ENOB(1)Effective number of bits bits

Differential input,9-bit setting8.3

Differential input,10-bit setting10

Differential input,12-bit setting11.5

10-bit setting,clocked by RCOSC9.7

12-bit setting,clocked by RCOSC10.9 Useful power bandwidth7-bit setting,both single and differential0–20kHz

Single ended input,12-bit setting,–6dBFS(1)–75.2

THD Total harmonic distortion dB

Differential input,12-bit setting,–6dBFS(1)–86.6

Single-ended input,12-bit setting(1)70.2

Differential input,12-bit setting(1)79.3 Signal to nonharmonic ratio dB

Single-ended input,12-bit setting,–6dBFS(1)78.8

Differential input,12-bit setting,–6dBFS(1)88.9

Differential input,12-bit setting,1-kHz sine

CMRR Common-mode rejection ratio>84dB

(0dBFS),limited by ADC resolution

Single ended input,12-bit setting,1-kHz sine

Crosstalk>84dB

(0dBFS),limited by ADC resolution

Offset Midscale–3mV

Gain error0.68%

12-bit setting,mean(1)0.05

DNL Differential nonlinearity LSB

12-bit setting,maximum(1)0.9

12-bit setting,mean(1) 4.6

12-bit setting,maximum(1)13.3

INL Integral nonlinearity LSB

12-bit setting,mean,clocked by RCOSC10

12-bit setting,max,clocked by RCOSC29

Single ended input,7-bit setting(1)35.4

Single ended input,9-bit setting(1)46.8

Single ended input,10-bit setting(1)57.5

Single ended input,12-bit setting(1)66.6

SINAD

Signal-to-noise-and-distortion dB (–THD+N)Differential input,7-bit setting(1)40.7

Differential input,9-bit setting(1)51.6

Differential input,10-bit setting(1)61.8

Differential input,12-bit setting(1)70.8

7-bit setting20

9-bit setting36 Conversion timeμs

10-bit setting68

12-bit setting132

(1)Measured with300-Hz sine-wave input and VDD as reference.

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RESET

CC2541

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ADC CHARACTERISTICS(continued)

T A=25°C and VDD=3V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Power consumption 1.2mA

Internal reference VDD coefficient4mV/V

Internal reference temperature

0.4mV/10°C

coefficient

Internal reference voltage 1.15V CONTROL INPUT AC CHARACTERISTICS

T A=–40°C to85°C,VDD=2V to3.6V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

The undivided system clock is32MHz when crystal oscillator is used.

System clock,f SYSCLK

The undivided system clock is16MHz when calibrated16-MHz RC1632MHz

t SYSCLK=1/f SYSCLK oscillator is used.

See item1,Figure2.This is the shortest pulse that is recognized as

a complete reset pin request.Note that shorter pulses may be

RESET_N low duration1μs recognized but do not lead to complete reset of all modules within the

chip.

See item2,Figure2.This is the shortest pulse that is recognized as

Interrupt pulse duration20ns an interrupt request.

Figure2.Control Input AC Characteristics

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SCK

SSN

MOSI

MISO

T0478-01

CC2541

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SWRS110A –JANUARY 2012–REVISED FEBRUARY 2012

SPI AC CHARACTERISTICS

T A =–40°C to 85°C,VDD =2V to 3.6V

PARAMETER

TEST CONDITIONS

MIN TYP MAX

UNIT Master,RX and TX 250t 1

SCK period ns

Slave,RX and TX 250

SCK duty cycle

Master 50%

Master 63t 2SSN low to SCK ns Slave 63Master 63t 3SCK to SSN high ns Slave

t 4MOSI early out Master,load =10pF 7ns t 5MOSI late out Master,load =10pF 10

ns t 6MISO setup Master 90ns t 7MISO hold Master 10

ns SCK duty cycle Slave 50%

ns t 10MOSI setup Slave 35ns t 11MOSI hold Slave

ns t 9

MISO late out

Slave,load =10pF 95ns

Master,TX only

8Master,RX and TX 4Operating frequency

MHz

Slave,RX only 8Slave,RX and TX

Figure 3.SPI Master AC Characteristics

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T0479-01

SCK

SSN

MOSI

MISO

DEBUG _CLK

P2_2

T0436-01

CC2541

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Figure 4.SPI Slave AC Characteristics

DEBUG INTERFACE AC CHARACTERISTICS

T A =–40°C to 85°C,VDD =2V to 3.6V

PARAMETER

TEST CONDITIONS MIN TYP MAX UNIT f clk_dbg Debug clock frequency (see Figure 5)12

MHz t 1Allowed high pulse on clock (see Figure 5)35ns t 2Allowed low pulse on clock (see Figure 5)

35ns EXT_RESET_N low to first falling edge on debug clock (see t 3167ns Figure 7)

t 4Falling edge on clock to EXT_RESET_N high (see Figure 7)83ns t 5EXT_RESET_N high to first debug command (see Figure 7)83ns t 6Debug data setup (see Figure 6)2ns t 7Debug data hold (see Figure 6)4

t 8

Clock-to-data delay (see Figure 6)

Load =10pF

30ns

Figure 5.Debug Clock –Basic Timing

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RESET _N

DEBUG _CLK

P2_2

T0437-01

DEBUG _CLK

P2_2

DEBUG _DATA DEBUG _DATA CC2541

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SWRS110A –JANUARY 2012–REVISED FEBRUARY 2012

Figure 6.Debug Enable Timing

Figure 7.Data Setup and Hold Timing

TIMER INPUTS AC CHARACTERISTICS

T A =–40°C to 85°C,VDD =2V to 3.6V

PARAMETER

TEST CONDITIONS

MIN TYP

MAX

UNIT Synchronizers determine the shortest input pulse that can be Input capture pulse duration

recognized.The synchronizers operate at the current system 1.5

t SYSCLK

clock rate (16MHz or 32MHz).

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CC2541RHA Package (Top View)

P 0_1

R E S E T _N

P 2_3 / O S C 32K _Q 2

A V D D 6

NC R_BIAS P 0_2

P 0_0

AVDD4P 0_3

AVDD1P 0_4

AVDD2P 0_5

RF_N P 0_6

RF_P P 0_7

AVDD3XOSC_Q1P 1_0

XOSC_Q2AVDD5

P 2_2

P 2_4 / O S C 32K _Q 1

SCL P 2_1

SDA P 2_0

GND P 1_7

P1_5P 1_6

P1_4D V D D 1

P1_3P1_1D C O U P L

P1_2DVDD2

CC2541

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DC CHARACTERISTICS

T A =25°C,VDD =3V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT Logic-0input voltage 0.5

V Logic-1input voltage 2.4V Logic-0input current Input equals 0V –5050nA Logic-1input current

Input equals VDD

–50

nA I/O-pin pullup and pulldown resistors 20

k ?Logic-0output voltage,4-mA pins Output load 4mA 0.5V Logic-1output voltage,4-mA pins Output load 4mA 2.5

V Logic-0output voltage,20-mA pins Output load 20mA 0.5

V Logic-1output voltage,20-mA pins

Output load 20mA

2.5V

DEVICE INFORMATION

PIN DESCRIPTIONS

The CC2541pinout is shown in Figure 8and a short description of the pins follows.

NOTE:The exposed ground pad must be connected to a solid ground plane,as this is the ground connection for the chip.

Figure 8.Pinout Top View

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PIN DESCRIPTIONS

PIN NAME PIN PIN TYPE DESCRIPTION

AVDD128Power(analog)2-V–3.6-V analog power-supply connection

AVDD227Power(analog)2-V–3.6-V analog power-supply connection

AVDD324Power(analog)2-V–3.6-V analog power-supply connection

AVDD429Power(analog)2-V–3.6-V analog power-supply connection

AVDD521Power(analog)2-V–3.6-V analog power-supply connection

AVDD631Power(analog)2-V–3.6-V analog power-supply connection

DCOUPL40Power(digital) 1.8-V digital power-supply decoupling.Do not use for supplying external circuits.

DVDD139Power(digital)2-V–3.6-V digital power-supply connection

DVDD210Power(digital)2-V–3.6-V digital power-supply connection

GND1Ground pin Connect to GND

GND—Ground The ground pad must be connected to a solid ground plane.

NC4Unused pins Not connected

P0_019Digital I/O Port0.0

P0_118Digital I/O Port0.1

P0_217Digital I/O Port0.2

P0_316Digital I/O Port0.3

P0_415Digital I/O Port0.4

P0_514Digital I/O Port0.5

P0_613Digital I/O Port0.6

P0_712Digital I/O Port0.7

P1_011Digital I/O Port1.0–20-mA drive capability

P1_19Digital I/O Port1.1–20-mA drive capability

P1_28Digital I/O Port1.2

P1_37Digital I/O Port1.3

P1_46Digital I/O Port1.4

P1_55Digital I/O Port1.5

P1_638Digital I/O Port1.6

P1_737Digital I/O Port1.7

P2_036Digital I/O Port2.0

P2_1/DD35Digital I/O Port2.1/debug data

P2_2/DC34Digital I/O Port2.2/debug clock

P2_3/33Digital I/O,Analog I/O Port2.3/32.768kHz XOSC

OSC32K_Q2

P2_4/32Digital I/O,Analog I/O Port2.4/32.768kHz XOSC

OSC32K_Q1

RBIAS30Analog I/O External precision bias resistor for reference current

RESET_N20Digital input Reset,active-low

RF_N26RF I/O Negative RF input signal to LNA during RX

Negative RF output signal from PA during TX

RF_P25RF I/O Positive RF input signal to LNA during RX

Positive RF output signal from PA during TX

SCL2I2C clock or digital I/O Can be used as I2C clock pin or digital I/O.Leave floating if not used.If grounded

disable pull up

SDA3I2C clock or digital I/O Can be used as I2C data pin or digital I/O.Leave floating if not used.If grounded

disable pull up

XOSC_Q122Analog O32-MHz crystal oscillator pin1

XOSC_Q223Analog O32-MHz crystal oscillator pin2

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P2_4P2_3P2_2P2_1P2_0

P1_4P1_3P1_2P1_1P1_0P1_7P1_6P1_5P0_4P0_3P0_2P0_1P0_0

P0_7P0_6P0_5XOSC_XOSC_SDA SCL

CC2541

SWRS110A –JANUARY 2012–REVISED FEBRUARY 2012

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BLOCK DIAGRAM

A block diagram of the CC2541is shown in Figure 9.The modules can be roughly divided into one of three categories:CPU-related modules;modules related to power,test,and clock distribution;and radio-related modules.In the following subsections,a short description of each module is given.

Figure https://www.sodocs.net/doc/9f4508631.html,2541Block Diagram

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BLOCK DESCRIPTIONS

A block diagram of the CC2541is shown in Figure9.The modules can be roughly divided into one of three categories:CPU-related modules;modules related to power,test,and clock distribution;and radio-related modules.In the following subsections,a short description of each module is given.

CPU and Memory

The8051CPU core is a single-cycle8051-compatible core.It has three different memory access busses(SFR, DATA,and CODE/XDATA),a debug interface,and an18-input extended interrupt unit.

The memory arbiter is at the heart of the system,as it connects the CPU and DMA controller with the physical memories and all peripherals through the SFR bus.The memory arbiter has four memory-access points,access of which can map to one of three physical memories:an SRAM,flash memory,and XREG/SFR registers.It is responsible for performing arbitration and sequencing between simultaneous memory accesses to the same physical memory.

The SFR bus is drawn conceptually in Figure9as a common bus that connects all hardware peripherals to the memory arbiter.The SFR bus in the block diagram also provides access to the radio registers in the radio register bank,even though these are indeed mapped into XDATA memory space.

The8-KB SRAM maps to the DATA memory space and to parts of the XDATA memory spaces.The SRAM is an ultralow-power SRAM that retains its contents even when the digital part is powered off(power mode2and mode3).

The128/256KB flash block provides in-circuit programmable non-volatile program memory for the device,and maps into the CODE and XDATA memory spaces.

Peripherals

Writing to the flash block is performed through a flash controller that allows page-wise erasure and4-bytewise programming.See User Guide for details on the flash controller.

A versatile five-channel DMA controller is available in the system,accesses memory using the XDATA memory space,and thus has access to all physical memories.Each channel(trigger,priority,transfer mode,addressing mode,source and destination pointers,and transfer count)is configured with DMA descriptors that can be located anywhere in memory.Many of the hardware peripherals(AES core,flash controller,USARTs,timers, ADC interface,etc.)can be used with the DMA controller for efficient operation by performing data transfers between a single SFR or XREG address and flash/SRAM.

Each CC2541contains a unique48-bit IEEE address that can be used as the public device address for a Bluetooth device.Designers are free to use this address,or provide their own,as described in the Bluetooth specfication.

The interrupt controller services a total of18interrupt sources,divided into six interrupt groups,each of which is associated with one of four interrupt priorities.I/O and sleep timer interrupt requests are serviced even if the device is in a sleep mode(power modes1and2)by bringing the CC2541back to the active mode.

The debug interface implements a proprietary two-wire serial interface that is used for in-circuit debugging. Through this debug interface,it is possible to erase or program the entire flash memory,control which oscillators are enabled,stop and start execution of the user program,execute instructions on the8051core,set code breakpoints,and single-step through instructions in the https://www.sodocs.net/doc/9f4508631.html,ing these techniques,it is possible to perform in-circuit debugging and external flash programming elegantly.

The I/O controller is responsible for all general-purpose I/O pins.The CPU can configure whether peripheral modules control certain pins or whether they are under software control,and if so,whether each pin is configured as an input or output and if a pullup or pulldown resistor in the pad is connected.Each peripheral that connects to the I/O pins can choose between two different I/O pin locations to ensure flexibility in various applications.

The sleep timer is an ultralow-power timer that can either use an external32.768-kHz crystal oscillator or an internal32.753-kHz RC oscillator.The sleep timer runs continuously in all operating modes except power mode 3.Typical applications of this timer are as a real-time counter or as a wake-up timer to get out of power mode1 or mode2.

A built-in watchdog timer allows the CC2541to reset itself if the firmware hangs.When enabled by software, the watchdog timer must be cleared periodically;otherwise,it resets the device when it times out.

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CC2541

SWRS110A–JANUARY2012–REVISED https://www.sodocs.net/doc/9f4508631.html, Timer1is a16-bit timer with timer/counter/PWM functionality.It has a programmable prescaler,a16-bit period value,and five individually programmable counter/capture channels,each with a16-bit compare value.Each of the counter/capture channels can be used as a PWM output or to capture the timing of edges on input signals.It can also be configured in IR generation mode,where it counts timer3periods and the output is ANDed with the output of timer3to generate modulated consumer IR signals with minimal CPU interaction.

Timer2is a40-bit timer.It has a16-bit counter with a configurable timer period and a24-bit overflow counter that can be used to keep track of the number of periods that have transpired.A40-bit capture register is also used to record the exact time at which a start-of-frame delimiter is received/transmitted or the exact time at which transmission ends.There are two16-bit output compare registers and two24-bit overflow compare registers that can be used to give exact timing for start of RX or TX to the radio or general interrupts.

Timer3and timer4are8-bit timers with timer/counter/PWM functionality.They have a programmable prescaler, an8-bit period value,and one programmable counter channel with an8-bit compare value.Each of the counter channels can be used as PWM output.

USART0and USART1are each configurable as either an SPI master/slave or a UART.They provide double buffering on both RX and TX and hardware flow control and are thus well suited to high-throughput full-duplex applications.Each USART has its own high-precision baud-rate generator,thus leaving the ordinary timers free for other uses.When configured as SPI slaves,the USARTs sample the input signal using SCK directly instead of using some oversampling scheme,and are thus well-suited for high data rates.

The AES encryption/decryption core allows the user to encrypt and decrypt data using the AES algorithm with 128-bit keys.The AES core also supports ECB,CBC,CFB,OFB,CTR,and CBC-MAC,as well as hardware support for CCM.

The ADC supports7to12bits of resolution with a corresponding range of bandwidths from30-kHz to4-kHz, respectively.DC and audio conversions with up to eight input channels(I/O controller pins)are possible.The inputs can be selected as single-ended or differential.The reference voltage can be internal,AVDD,or a single-ended or differential external signal.The ADC also has a temperature-sensor input channel.The ADC can automate the process of periodic sampling or conversion over a sequence of channels.

The I2C module provides a digital peripheral connection with two pins and supports both master and slave operation.I2C support is compliant with the NXP I2C specification version2.1and supports standard mode(up to 100kbps)and fast mode(up to400kbps).In addition,7-bit device addressing modes are supported,as well as master and slave modes.

The ultralow-power analog comparator enables applications to wake up from PM2or PM3based on an analog signal.Both inputs are brought out to pins;the reference voltage must be provided externally.The comparator output is connected to the I/O controller interrupt detector and can be treated by the MCU as a regular I/O pin interrupt.

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cc2541 datasheet

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