A Dynamic Reconfiguration Run-Time System 1

A Dynamic Reconfiguration Run-Time System 1

Jim Burns, Adam Donlin, Jonathan Hogg, Satnam Singh, Mark de Wit

The Department of Computing Science

The University of Glasgow Glasgow G12 8RZ, United Kingdom

{jim,adam,jonathan,satnam,dew}@https://www.sodocs.net/doc/975973816.html,

1.This research is supported in part by UK EPSRC grant

number GR/K82055

Abstract

The feasibility of run-time reconfiguration of FPGAs has been established by a large number of case studies. However,these systems have typically involved an ad hoc combination of hardware and software. The software that manages the dy-namic reconfiguration is typically specialised to one applica-tion and one hardware configuration. We present three different applications of dynamic reconfiguration, based on research activities at Glasgow University, and extract a set of common requirements. We present the design of an extensible run-time system for managing the dynamic reconfiguration of FPGAs, motivated by these requirements. The system is called RAGE, and incorporates operating-system style serv-ices that permit sophisticated and high level operations on circuits.

1Introduction

Dynamic reconfiguration of FPGAs has recently become viable with the introduction of devices that allow high speed partial reconfiguration, e.g., the Xilinx XC6200 series [14].Dynamic reconfiguration is usually performed by a software system that decides when to reprogram part of the FPGA and with what. The simplest kind of run-time software simply selects a precompiled circuit and transmits the programming data directly to the FPGA.

At the University of Glasgow’s Department of Comput-ing Science, the Reconfigurable Architecture Group (RAGE)has a number of projects examining applications of dynamic reconfiguration. These applications have highlighted the need for a more complex run-time system. Rather than devel-oping different run-time systems for each application, as is common, we have extracted a set of common requirements from several applications. This has formed the basis of the design of a proposed, core, run-time system, able to support all of these applications. There are many parallels that can be drawn between this design and conventional operating system design—as the techniques used to manage conven-tional resources, such as memory and the CPU, are also applicable to the management of FPGAs.

The next section of this paper describes three applica-tions of dynamic reconfiguration and their requirements, and draws from these a set of core requirements. We follow this with an overview of the proposed system, and more detailed discussions of the r?les of the identified system components.We close with a discussion of how our system might support other applications in the field.

2

Case Studies

2.1

The FPGA/PS Project

The FPGA/PS project aims to exploit the dynamic reconfig-urability of FPGAs to accelerate PostScript? rendering. The bulk of PostScript? rendering is still performed on a host computer, but the time consuming rendering of graphics for high quality printing (thousands of dots per inch) is acceler-ated by circuits realised on an Xilinx XC6200-based FPGA sub-system. When a different rendering operation is required (e.g. line or arc rendering), it is dynamically swapped onto the FPGA. We call this technique of swapping circuits on and off FPGAs ‘virtual hardware ’ [8]. Although this technology is being developed to support PostScript? rendering, the gen-eral architecture is of relevance to a much wider class of applications.

Figure 1 Xilinx XC6216 PCI Board

A collection of pre-routed and placed circuits reside in the main memory of the host system, ready for rapid down-load onto the FPGA over a PCI bus. The FPGA is housed on the board shown in Figure 1. At pre-defined intervals during PostScript? rendering, data and operation codes are passed as parameters to the virtual hardware run-time system. The system then swaps an appropriate circuit onto the FPGA and also preloads circuit input registers with values passed from the application.

As results are generated by the circuit, the application is interrupted allowing it to fetch the relevant data from some known memory location. Only one working circuit is resident on the chip at any time. Unlike other similar reconfigurable systems, our proposed system aims to factor out such common run-time support operations rather than hard-coding them into the application.

To ease memory mapping between the FPGA, the RAGE system, and the FPGA/PS application, circuits can be organ-ised in the following ways:

1.Some circuitry is held static on the FPGA and serves as

input and output ports for the dynamic circuitry. For instance, a circle rendering circuit needs (x, y) coordi-nates for the centre and a radius value. These static input registers would be reused when the next rendering circuit is swapped in. This policy reduces the number of cells to be configured, but makes circuit placing less flexible. 2.The input and output ports of the circuit representation

are tied to the working circuit itself, and the circuit is swapped onto a pre-determined location on the FPGA. 3.The circuits are able to be placed anywhere (within

known boundaries) and the RAGE system organises the mapping of circuit registers into host memory transpar-ently. To the application, these registers are at a well known address.

Circuits which need no run-time place and route can be rep-resented very simply, as address/data pairs which form the FPGA programming information. There is no need to have an internal representation of the FPGA itself, because no place and route need take place.

If, however, more complex swapping is required (cases 2 and 3 above) some run-time place and route is required. A full representation of all the muxes and configuration memory on the chip is maintained by the run-time system. The internal representation of circuits needs to be richer too, encompass-ing knowledge of ports, hierarchical circuit blocks, etc.

The circuit swapper has access to a library of circuits, and passes the programming data to the device driver. When a circuit is being swapped, it is important that the behaviour of the system is predictable. The circuit swapping mechanism should either isolate the on-chip static circuitry, or be aware that spurious results may be produced whilst swapping is in progress. 2.2Partial Evaluation

Partial evaluation provides a methodology for reducing the resource requirements of, possibly otherwise unimplementa-ble, circuits by utilising the nature of some circuit inputs to remain static for long periods of time relative to the other inputs. An example of this is a circuit which multiplies a stream of numbers by a constant—a situation often found in digital signal processing applications. In this example, the constant value would normally be given as an input to the cir-cuit because, while it is a constant number for a particular stream, it may change for another. However, this requires the number to be routed through the circuit and a general multi-plier to be implemented. By specialising the multiplier for a particular number, the routing resources required to feed in that constant are freed and components with now static func-tionality can be simplified or removed [10].

Partial evaluation is already a common technique in soft-ware compilation and execution, particularly in the field of functional programming. Here, the source text is analysed for static expressions which can be evaluated at compile-time. However, the traditional flow from hardware description to implementation involves going through hardware compilers and a generally lengthy place-and-route phase where the gates of the compiled hardware description are arranged according to the available FPGA resources. It is not feasible to do such work at run-time when a constant value is changed. As much as possible, the work of generating specialised cir-cuits should be moved to the initial compile-time rather than run-time. This can be achieved by symbolic partial evalua-tion, where inputs are tagged as static, but their values are not defined. These inputs are traced through the circuit to see which components of the circuit are functionally dependant on them. Case analysis of these components can then be used to determine the different possibilities for different inputs [4].

Figure 2 Symbolic partial evaluation by case analysis

This results in a tree of possible circuit components as

shown in Figure 2. For any particular values of the partially

x

static inputs, the appropriate leaves of this tree will yield the components of a specialised circuit for those values. In order to be able to quickly build specialised circuits at run-time, the components at the leaves of the tree should be pre-placed-and-routed. This allows the components to be made resident in the appropriate combination, requiring only routing between components to be done at run-time.

Generating such a tree of components is not an easy task and represents on-going research in the group. Different branches of the tree must be inter-changeable for each other and thus must have similar FPGA footprints. This is achieved by manipulating designs given in the Ruby hardware descrip-tion language [11]. Specifications in Ruby encode the layout as well as the behaviour of the circuit. The symbolic partial evaluation process transforms these specifications such that the areas of reconfiguration are localised, and the overall layout is retained as much as possible. These transformed specification trees must be placed-and-routed to produce a tree of FPGA-level components which have controlled foot-prints allowing them to be interchanged. Unfortunately, no automatic tool exists that is capable of doing such directed place-and-route. However, existing tools capable of doing partial place-and-routes can be utilised by judicious use of placement constraints.

2.3Reconfigurability by Design

For circuits which are inherently reconfigurable, a large pro-portion of the physical design is functionally static. A few well defined regions of the design, however, are identified as being reconfigurable. By effecting changes solely in these areas, the functionality of the overall circuit is modified within some restricted overall area of operation. For example, a multiplier does not turn into a VRAM circuit, but a *3 mul-tiplier may become a *7 multiplier. This effectively consti-tutes fine grain inherent reconfigurability at gate level as opposed to large scale reconfigurations used in the FPGA/PS project.

An important requirement in the context of fine grain reconfiguration is to have a high level representation of the circuit that in itself identifies areas of reconfigurability sym-bolically. This representation is submitted to the system and the corresponding circuit is made resident on the board. Later, we refer to the reconfigurable areas of the circuit by their symbolic name. By passing this symbolic reference to the system with the circuit with which it is to be substituted, we can effect the desired style of reconfiguration.

In detailed terms, the circuit representation passed to the system must therefore be at least a CAL file (a file containing a circuit representation at a low-level/device programming interface level) and some higher level symbolic representa-tion of the circuit itself. A layer generated/imposed by the system provides a mapping between these representations—effectively fusing them together. Furthermore, the mapping must be invertible between representations. The circuit will most likely be modified by the system upon submission. We recognise that dataflow in the system may not entirely flow downwards. The system must also be able to direct upflowing results and configuration data to the appropriate application entity. To allow the enforcement of more complex applica-tion level reasoning the application may acquire knowledge of the transformed state of its submitted circuit. A circuit may be transformed and made resident, but in its modified form would fail to fulfil application specific criteria. The detailed judgement of such criteria is beyond the scope of our pro-posed system, but may be suitably placed at application levels.

An optimisation to the submission of both CAL and sym-bolic representations is that the application submit only a symbolic representation of a pre-placed and routed circuit and allow the system to generate the programming stream level circuit representation. It is known that stream generation is a relatively simple task and can be performed rapidly. The main benefit is that the complexity of the application inter-face is reduced from the users point of view.

2.3.1Example: Systolic FIR

As an example of a design which has real world practical application, we consider an n-tap systolic implementation of a finite impulse response (FIR) filter. The basic structure of a systolic FIR, shown in Figure 3, is a series of processing ele-ments interconnected in a regular, linear fashion [6,7]. The systolic FIR we consider utilises Kean’s inherently reconfig-urable multiplier design [5].

Figure 3 Systolic Array Structure

The basis behind Kean’s multiplier relies on the ability to split an m-bit multiplication (with a 2m bit result) into two -bit multiplications. These subsequent multiplications are realised by two independent look up tables (LUTs) which are each configured to produce the multiplied value of the free coefficient by the upper and lower halves of the constant coefficient respectively. These two partial results are recon-

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ciled by a 16 bit adder circuit to produce the final 2m-bit result.

The lookup tables are arranged to make them easy to dynamically reconfigure. Every cell in columns 0, 2, 4 and 6 is a 2 input to one output gate which encodes four columns of the truth table of a single-bit multiplier. At run-time the host makes a calculation to decide for a given 12-bit coefficient what the values of these gates should be. There are 48 cells for each 4-bit by 12-bit multiplier, giving a total of 96 cells to be reconfigured. The functionality of an individual cell is defined by a single byte. As four such elements may be passed in a single configuration cycle, the total number of cycles required, in the worst case scenario, is 24. Given a 33MHz programming interface, an entire LUT could be com-pletely reconfigured in 1.45 μs including setup costs.

Figure 4 Reconfigurable multiplier dataflow for a*x=c

The systolic array is realised effectively on the XC6200 architecture because of the use of dynamically reconfigurable LUTs in such ‘divide and conquer’ m-bit multiplication. The final on-chip layout of a processing element of the ilk described is shown in Figure 5. The reconfigurable LUTs are vertically interleaved (columns 0 to 6) to facilitate the addi-tion of the partial results (a 12bit adder appears in columns. 7 and 8). Finally, the result of the multiplication is accumulated with the PE’s incoming y value by a 16-bit adder (cols. 9 and 10).

We now address how the proposed runtime system will support the inherently reconfigurable systolic array. The application levels submit template systolic array symbolic circuit. Such a design would most likely be preconfigured to some initial or default set of taps. Upon receiving this design, the system begins the process of making the circuit resident on the reconfigurable resource. The Virtual Hardware (VH) Manager attempts to ensure the co-existence with other resi-dent circuits. At this point, the array may be transformed and is, in effect, being denied its default orientation, location or both. The Transformation Services would then provide any necessary modifications to the circuit topology as dictated to it by the VH Manager. At this stage, the full range of geomet-ri c a n d r e pla c e m en t/r e-r o ut i n g f a c i l i t i e s o f t h e Transformation manager may be called upon.

Under the instruction of the VH Manager (and after any initial transformation), the array may be made resident by the configuration manager, which rapidly converts the symbolic circuit representation to a programming stream. This stream is directed towards the low level device driver which interacts directly with the hardware to physically configure the FPGA.

At this point, the application may submit a series of re-configuration requests, specifying the areas of the submitted circuit symbolically. With fine grain elements of reconfigura-bility, such as gate level in the multiplier LUTs, there is no need for transformation services. Additional write cycles may be used to update functionality. For coarser grain inherently reconfigurable designs, transformations may need to be applied. It is unlikely that an application supplied circuit would be immediately applicable in a circuit which has itself been transformed.

Given that the array is now resident, the remaining two main events involve the supply and recovery of data. Down-flow of data to the array may be managed as a style of reconfiguration. Application supplied data is likely to be retained in registers of the submitted design. Registers have state i.e. configuration. Therefore, just as topology reconfig-urations are submitted, so are register state reconfigurations. Utilisation of features such as map-registers may be possible if symbolic representations are rich enough to allow the run-time system to identify such features. Applications may refer symbolically to register “bar”, and supply a configuration for it. The symbolic register identification is interpreted in the VH Manager which then directs the configuration manager to effect the desired state change.

Figure 5 Layout of systolic PE

Upflow of information, likewise, may be done symboli-cally. Just as an application is aware of the symbolic representation of its transformed design, it may also enquire as to the configuration state of a symbolically named register. The VH Manager once again interprets the symbolic identi-fier and directs the configuration manager to acquire the current configuration of the appropriate register components. The VH Manager, upon receipt of configuration state, replies to the application levels appropriately.

We recognise that circuits may not always be passive entities and may themselves actively seek communication with the application levels. To facilitate this, we propose an exception mechanism which allows the on-chip circuits raise, possibly parameterised, exceptions in the application levels. The VH Manager itself may be aware of circuit exceptions through symbolically defined exception register regions in the circuit.

2.4Summary

The objective of our dynamic reconfiguration run-time system is to provide a high level interface to applications that wish to perform complex reconfiguration and circuit manip-ulation tasks. We view our run-time system as an operating system for the FPGA which executes on the host computer. From the case studies above, we derive the following general requirements:

?The ability to reconfigure an FPGA and access board-level resources (e.g. clocks) without directly communi-cating with a device-driver.

?The ability to reserve a chunk of FPGA resource. This allows one FPGA to be shared amongst several tasks and applications.

?The ability to transform a circuit e.g. change it’s orienta-tion or translate its position.

? A rich high level symbolic representation for circuits retaining the ability to quickly effect changes in the rep-resentation and transform the representation into device specific programming data.

?An architecturally correct representation of the FPGA device to support core algorithmic operations within var-ious entities of the proposed system.

These requirements have influenced the design, in the follow-ing sections, of more detailed aspects of the proposed system. 3System Overview

Figure 6 illustrates the data flow through the RAGE run-time reconfiguration system. The virtual hardware manager coordinates the execution of the other system components. This component is further described in section 4. The device driver hides the programming interface of the FPGA and PCI board (Figure 1) and presents a low level foundation on which more complex functionality is built. It virtualises the board’s I/O ports and FPGA’s configuration memory, enforc-ing mutual exclusion and also maps the configuration memory into the host’s address space. The device driver is described in section 7. The configuration manager, described in section 6, links the virtual hardware manager and the device driver. A programming stream is generated and this is mapped transparently to the programming memory of the FPGA.

Figure 6 The RAGE System Dataflow.

The proposed system is designed initially to specifically operate with Xilinx XC6200 FPGAs [14]. This limits the direct applicability of our approach to one particular series of FPGAs. Despite this, the system has been designed to ensure many of the services make sense in other SRAM based FPGAs. We believe that one should gain experience in designing a good system for one device, and then try and gen-eralise for other FPGAs. We expect much of the system to be applicable to the Atmel 6000 series/National Semiconductor CLAy FPGAs.

The XC6200 series of FPGAs are based on a grid of cells (48x48, 64x64, 96x96 or 128x128) each of which can realise routing, any one or two input logic function or a 2-to-1 mul-tiplexor. These functions can be combined with a register. Cells may communicate with their neighbours, or to cells fur-ther away using a hierarchical routing system based on blocks of size 4, 16 and 64. It is possible to reprogram individual bits of configuration memory, or to program 4 cells in one 32-bit write cycle (more cells can be reconfigured at once if there is any regularity in the design). The programming interface runs at 20MHz. A key feature of the XC6200 architecture, which is exploited by our system, is the ability to read and write directly to cells configured as registers on the FPGA. This

Applications

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means that inputs do not need to be explicitly routed to cir-cuits from I/O pads, and provides a very powerful location transparency which allows us to realise relocatable circuits. 4Virtual Hardware Manager

The virtual hardware (VH) manager provides the main inter-face between the application and the run-time system. Calls are made to the VH manager to make a circuit resident, com-municate with that circuit, and free its resources afterwards.

A typical sequence of events might be:

?Application submits circuit in an external representation to the VH manager which converts this into an internal circuit data structure which is put into the circuit store.?Application requests circuit to be made resident.

?VH manager checks current resource utilisation and finds

a location for circuit, possibly after having to pass it to

the transformation manager for translation.

?VH manager passes the, possibly transformed, circuit to the configuration manager for conversion to program-

ming data and download to FPGA via device driver.?Application provides circuit input data to VH manager and requests execution.

?VH manager downloads the data to the circuit, sets up interrupt handlers for completion and signals the circuit to begin execution (all through the configuration man-

ager/device driver).

?On completion interrupt, the VH manager reads back the result data and passes it up to the application.?Application signals that the circuit is no longer required.?VH manager marks circuit resources as free and updates the configuration manager.

During this sequence of events, the application might make other requests to partially reconfigure the circuit or download other circuits. Such requests are done at a high-level using symbolic components and circuits. The VH manager main-tains a map of the FPGA usage in terms of these high-level circuit blocks, relying upon the configuration manager to map these to actual FPGA cells. For example, the VH manager might refer to a register of a circuit as counter.preload whereas the configuration manager would understand this as being cells 4-20 of column 12 on the FPGA.

5Transformation Manager

We cannot rely on a circuit always being suitable for resi-dence on the reconfigurable device. Allowing the reconfig-urable device to be shared amongst circuits means that the ‘default position’ of one circuit may already be in use by another. To facilitate a flexible virtual hardware system, cir-cuits themselves must be flexible elements. If a circuit cannot be placed in its desired default position, then the virtual hard-ware system must be able to somehow transform the circuit into a state in which it can be made resident in some other sec-tion of the reconfigurable device. The entity which is respon-sible for providing these facilities is the Transformation Manager.

5.1Transformation Services

RAGE transformation services use a subset of two dimen-sional graphical transformations. These include translation, rotation, mirroring and scaling. Used as a set of primitive operations, it is possible to construct complex compound transformations which allow an entity to be manoeuvred around a two dimensional space. Furthermore we identify the usefulness of composition transformations such as “join” and “slice”.

Our system holds a conceptual model of a 2D reconfig-urable area and hence the standard 2D geometric transformations are directly relevant.

Figure 7 Transformations to support efficient device usage Consider, for example, the use of geometric transformations to place the circuit A, in Figure 7. It is clear that there is in fact no space readily available for the circuit to occupy. By imposing a translation and rotation transformation, it is pos-sible to have the circuit resident in the area of free space marked X. Without such functionality, the circuit could not have been made resident on the FPGA in its current state. The alternatives would have been either to deny service to the application requesting that the circuit be placed on the FPGA, or to allow the runtime system to remove resident circuits from the FPGA.

Evicting a circuit is a viable alternative to transforma-tions and may be less expensive in terms of raw costs. Since circuits rely on uninterrupted slots of residency to reach cost/ benefit break even points, transformations are however more attractive and less disruptive. By composing transformations the cost may be reduced to a level lower than that of pre-emption.

5.2Transform Support Issues

We have identified a use and justified a need for transforma-tion services within the context of our runtime system sup-porting virtual hardware. In this section we consider some of

the issues involved with supporting a set of 2D geometric transformations within the context of our system.

At some later point, within the configuration manager, this transformed symbolic circuit representation is translated into FPGA specific programming information. The effect of transformations, therefore, is to modify the contents of a sym-bolic data structure representing a routable circuit. A netlist style representation which is also capable of explicitly defin-ing routing information and indicating placement positions is used for this purpose.

We recognise that transformations may require modifi-cations to the routing and/or placement decisions made at circuit compile time. The resources available on the Xilinx XC6200 are generally regular, but possess some irregular, asymmetric, features. Compile-time routing makes decisions based on a particular placement of the current circuit and assurances of the availability of resources and the general “lay of the land” upon which the circuit will be made resident. Transformations at runtime are likely to invalidate some of these assurances. In such situations, the circuit will most likely become invalid and, if made resident on the board, fail to perform its intended function. Indeed, the circuit may pos-sibly interfere with the operation of other resident circuits as the routing bounding box is known to exceed the placement bounding box of a circuit in some instances (this is an issue for the virtual hardware manager, however, which has to decide what constitutes the footprint of a circuit.).

We believe that re-routing parts of a circuit at runtime is likely to be necessary on the Xilinx XC6200. Consider a cir-cuit of dimensions 3x4 located at position (0,0) on the device. If this circuit were to be translated to position (1,1) on the board, then its internal routing would have to be routed across a series of switching matrices that exist on the boundaries of every group of 4x4 cells. These switching matrices facilitate access to the hierarchical routing resources that are particular and novel to the XC6200. It is clear that the internal routing details of the circuit now have to be adjusted.

Irregularities in the resources in the target FPGA also introduce other scenarios which must somehow be dealt with. The XC6200 architecture possesses a series of “hidden”inverting multiplexors. These features constitute an irregular-ity in the resource and a circuit designed, placed and routed at position (10,20) may not be placed at (21,10) as the irregular features present at (10,20) are not present at (21,10). The res-olution of such resource clashes, for the XC6200 architecture, involve introducing new components into the circuit. Intro-ducing new components into a circuit, however, may have a knock on effect on the placement and the availability of rout-ing resources for other components.

To resolve these problems, we identify three possibili-ties, all of which rely on the ability of the system to detect when a circuit transformation will invalidate the circuit. The first resolution is stringent and involves refusing the current set of transformation requests. At first glance this system may appear pointless, and all flexibility may appear to have been lost. It is possible, however, for the system to operate within this framework if the use of transforms is restricted to adhere to the symmetry and regularity of those available resources. If this convention is followed, then the circuit shown in Figure 8, above, would never be translated a the position in which its internal routing would have needed to be altered. Using this method, we can extend the applicability of a pre-placed and pre-routed circuit, but at the cost of granularity of placement and therefore, overall, at some cost to the flexibil-ity of the system as a whole. Similar restrictions can be applied to the other transformations.

Alternatively, and at the opposite extreme, the system may actively attempt to re-route and/or re-place components as required to overcome the resource clash. Runtime full place and route is likely to be unfeasibly slow. Rather than attempting to support a full place and route engine, we sug-gest a bounded runtime place and route which attempts to localise changes to placement and routing. Through a process of localisation and problem minimisation the duration of runtime place and route on a symbolic circuit representation may be greatly reduced. Additional mechanisms to reduce the duration of runtime fitting onto the reconfigurable resource would be to abandon the search for an optimal solution to the placement or routing of a particular circuit. By taking only those transformational steps which make the circuit valid for residence and no more, it is possible to simplify runtime place and route. Furthermore, it may be possible to gradually evolve a better routed/placed circuit during the course of the application's lifespan.

In theoretical terms, just as a program in memory exhib-its locality of execution and locality of reference, some circuits in a system will show locality of placement and there-fore locality of routing. Given the possibility of this behaviour, evolutionary runtime placement and routing would preserve maximum flexibility of the overall system

before transform after transform

dynamic re-route

required

Figure 8 Circuit Invalidation by Transformations

and work towards reducing the transformation service over-heads to a relatively acceptable minimum.

6Configuration Manager

Device drivers need to be lean and use as few resources as possible. They provide a high degree of device independence but software layers built on top, usually code libraries, pro-vide the final device abstraction. Similarly, the configuration manager of the RAGE system acts as the final abstraction layer, providing a device independent interface to the VH manager. Here is a partial list of the services to be provided by the configuration manager:

?Configure a circuit;

?Partially reconfigure an existing circuit;

?Load data, passed from the application, though the VH manager, to registers in an circuit resident on the FPGA;?Pass state information, provided by the device driver, to the VH manager, e.g. an interrupt message if the FPGA device overheats;

The symbolic representation of circuits must be converted to the programming stream for the FPGA concerned. Likewise, the data to be loaded into the circuit registers must be in the correct format. To this effect, the configuration manager must preserve a mapping between the two representations. This allows a request from the VH manager to be converted into the correct programming data for the FPGA. Similarly, state data from the device driver, such as interrupts, may be passed back to the VH manager using a message indicating that the counter circuit had run for the requested number clock ticks.

Rather than waste valuable programming cycles query-ing the FPGA to obtain configuration and state data, the configuration manager maintains an image of the FPGA con-figuration and state. It provides a query service to the virtual Hardware Manager.

7Device Driver

The device driver provides a set of functions which enable the configuration manager to program the FPGA device and communicate with a PCI board containing one or more FPGAs. The required functionality includes:

?Writing and reading the PCI board SRAM;

?Writing and reading FPGA cell programming data;?Interrupting the host when certain board generated events occur;

?Setting the FPGA clocking frequency;

?Monitoring the current drawn by the FPGA;?Clocking FPGA circuits with individual, continuous, or a preset number of clock cycles.

Both the FPGA programming interface and the SRAM are transparently mapped into the host processor’s memory space. Programming the FPGA and writing to SRAM are simple programming language assignment operations.

The SRAM programming interface provides a fast cache which can be used by both the host and the FPGA. There are two banks of SRAM and although a bank cannot be shared between host and FPGA, ownership of a bank can be switched by the device driver to permit data sharing.

A total of three interrupts can be generated by the PCI board. The first interrupt is triggered when the current drawn by the FPGA exceeds a predefined threshold. The second is triggered when the last in a preset sequence of clock cycles has elapsed. The third interrupt can be requested by the FPGA for any reason. The device driver is interrupted, and may either handle the interrupt or pass relevant information to higher layers of software allowing the application to take appropriate action.

8Application-System Level Interface

The system entities we described in earlier sections do not cover all possible application level requirements. Rather than being inflexible, however, our proposed runtime system is intended to provide a general foundation, applicable to many general application contexts. Our system can be extended by inserting application specific entities as mediators between our proposed basic system and the application.

Figure 9 Core System Extension by Application-Context Specific

Module.

An example of such system functionality extension would be partial evaluation, as discussed in section 2.2. An alternative and simpler example is a Specialisation Module effecting constant propagation—a standard optimisation per-formed at compile time [13]. Known inputs are fed through the circuit and logic optimisation is performed e.g. an AND gate with one high input can be replaced by a wire driven by the second input. Although this not core system functionality, it may be profitable, in some application contexts, to perform this kind of optimisation at run-time for dynamically recon-figurable FPGAs. This is especially true if the specialised circuit will be used many times, thus recouping the run-time Core Dynamic Reconfiguration

Runtime System

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cost of calculating it. For example, consider the AND cell in Figure 10(i) with a constant high input which, after some cal-culation, can be optimised to Figure 10(ii).

A Specialisation Module would take a circuit description and a set of protected input-register values and propagate the values of these ‘constant’ registers throughout the circuit.Propagation stops when an output register is encountered, or a flip-flop or asynchronous feedback path is found.

An important consideration, at this point, is the means by which an Extension Module communicates with the core sys-tem. The core system presents a simplified interface to applications. A privileged interface, which is a superset of the application interface, would allow Extension Modules medi-ated and controlled access to internal runtime system data structures. By this means, an Extension Module may acquire detailed information about the transformed state of a previ-ously submitted circuit as well as having fast access to data structures.

Figure 10 Simple constant propagation of logical “And”

9Related Systems

At present there are very few FPGA run-time reconfiguration systems. All available systems are highly specialised to par-ticular applications or groups of applications. RAGE is a more generic system and is tied to no particular set of appli-cations. Applications using RAGE must be designed with the system in mind but are not tied to specialised development tools. The RAGE system can be used by simply linking its exported functionality to a library of functions. RAGE is not a development system. It allows access to the FPGA hard-ware using a high level interface. The goal is that the design is sufficiently flexible to support other applications outside of the ones being examined by the RAGE group. In the follow-ing sub-sections, we discuss how our proposed system applies to other applications in the field.

9.1The Dynamic Instruction Set Computer (DISC)The Dynamic Instruction Set Computer (DISC) developed at Brigham Young University [12] exploits FPGA reconfigura-tion to dynamically supplement its fixed instruction set. Each instruction or circuit module can be swapped on and off the CLAy31 FPGA as the running application demands. Like the RAGE system, DISC maintains a library of circuits and DISC circuits are designed with a global context (the system’s view

of the FPGA) which allows them to operate at any vertical position on the FPGA. Circuits designed for RAGE, however,can be placed anywhere on the FPGA. Dynamic reconfigura-tion on DISC is achieved by a reconfiguration controller which executes on the FPGA. In contrast, the RAGE system runs entirely on the host machine which allowing easier debugging. Software/hardware co-design with DISC requires the use of lcc, a retargetable C compiler. The RAGE system provides a higher level interface for hardware/software co-design. Programs using virtual hardware need only call the system functions, which are linked in to the application pro-gram.

Despite these differences, most applications running on DISC could be easily adapted to RAGE by providing a group of circuits placed and routed for the Xilinx FPGA and by including library function calls within application code.9.2

The Run-Time Reconfigurable Neural Network (RRANN)

RRANN [2] uses dynamic FPGA reconfiguration to imple-ment the three stages of the neural network backpropogation algorithm. Each stage of the algorithm is represented by a cir-cuit module which is swapped on and off the FPGA hardware as demanded by the application. Only one circuit module is resident on the hardware at a given time. Some static circuitry is resident; this controls dataflow and the sequencing of exe-cution of the dynamic modules.

RRANN2 [3] takes this simple swapping of circuits one stage further by using swapping at finer granularity. By max-imising the static circuitry, less time is spent reconfiguring circuits, and system efficiency is increased. Smaller circuit elements are reconfigured, for example a counter is shaved from 11 to 8 bits, and the rest of the circuit remains unchanged.

Either of these applications can be easily adapted to use RAGE. By creating a library of circuits known to operate on the Xilinx FPGA and by writing code in any language from which Windows DLL functions can be called, the application can have access to the virtual hardware without resorting to recompiling the whole program.9.3

Fast Reconfigurable Crossbar Switching in FPGAs

This technology, developed at the Department of Electrical and Electronic Engineering in the University of Strathclyde [1] implements a fast reconfigurable crossbar switch on an Atmel AT6005 FPGA. The switch is part of an ultrasonic imaging system which is highly time dependent. The circuit design is tailored specifically for the Atmel FPGA.

This application’s dependence on the Atmel FPGA may preclude its implementation on the Xilinx FPGAs. RAGE,however, will eventually support a variety of FPGA architec-tures and so it is likely that this application could be adapted to run on RAGE. The dynamic circuit reconfiguration would

1

a

a

(i)

(ii)

logic AND

FN Unit

be handled by the virtual hardware manager using pre-placed and routed alternative circuits from the circuit store or may employ the services of the RAGE transformation manager. 10Summary

As more applications take advantage of dynamically recon-figurable FPGA-based hardware, there is a need for software support to facilitate dynamic reconfiguration and to provide high level abstractions of hardware which allow it to be shared amongst many tasks. We have described the architec-ture of a proposed run-time system that meets these objec-tives whose design was motivated by our own experiences and applications of dynamic reconfiguration.

We wish to acknowledge the support of Xilinx Corp. for software, hardware and technical support.

This research is supported in part by UK EPSRC grant number GR/K82055.

References

[1]H. Eggers, P. Lysaght. H. Dick and G. McGregor, Fast

Reconfigurable Crossbar Switching in FPGAs. In, R.

W. Hartenstein, M. Glesner (Eds.) Field-Programmable Logic—Smart Applications, New Paradigms and Com-pilers, Springer Verlag, Germany, 1996, pp. 297-306.

[2]James G. Eldridge, Brad L. Hutchings. RRANN: The

Run-Time Reconfiguration Artificial Neural Network.

IEEE Custom Integrated Circuits Conference. 1994. [3]J. D. Hadley, B. L. Hutchings. Design Methodologies

for Partially Reconfigured Systems. FCCM’95. IEEE Computer Society, 1995.

[4]J. Hogg. A Dynamic Hardware Generation Mechanism.

In, M. Sheeran, S. Singh (Eds) Designing Correct Cir-cuits, Electronic Workshops in Computing, Springer Verlag, 1996.

[5]T. Kean, B. New, B. Slous. A Multiplier for the XC6200.

Sixth International Workshop on Field Programmable Logic and Applications. Darmstadt, 1996.

[6]H. T. Kung. Why Systolic Architecture s. IEEE Compu-

ter. January 1982.

[7]Charles E. Leiserson. Systolic and Semisystolic Design.

IEEE Conference on Computer Design/VLSI In Com-puters (ICCD’83). 1983.

[8]Satnam Singh and Pierre Bellec. Virtual Hardware for

Graphics Applications using FPGAs. FCCM’94. IEEE Computer Society, 1994.

[9]Satnam Singh. Architectural Descriptions for FPGA

Circuits. FCCM’95. IEEE Computer Society. 1995. [10]Satnam Singh, Jonathan Hogg and Derek McAuley. Ex-

pressing Dynamic Reconfiguration by Partial Evalua-tion. FCCM’96. IEEE Computer Society. 1996. [11]M. Sheeran, G. Jones. Circuit Design in Ruby. Formal

Methods for VLSI Design, J. Stanstrup, North Holland,

1992.

[12]Michael J. Wirthlin and Brad L. Hutchings. A dynamic

instruction set computer. FCCM’95. IEEE Computer Society. 1995.

[13]Michael J. Wirthlin, Brad L. Hutchings. Improving

functional density through run-time constant propaga-tion. To be published in FPGA’97.

[14]Xilinx. XC6200 FPGA Family Data Sheet. Xilinx Inc.

1995.

前台新进员工带教手册(V11)

前台新进员工带教手册 目录 一、海友酒店介绍 1.1品牌故事 1.2产品特征 1.3目标客户群 二、海友酒店前台交接班制度 2.1 交接班准备 2.2 交接事项 2.3 填写交接班本 2.4 接班事项 2.5 交接班签名 三、海友酒店前台员工带教计划 3.1 带教目的 3.2 带教内容 一、海友酒店介绍： 1.1品牌故事 海友酒店是华住酒店集团（原汉庭酒店集团）旗下的风格经济型酒店连锁品牌，致力于为有预算要求 的客人提供“欢乐、超值”的住宿产品。 我们全情投入，与顾客真诚沟通，分享快乐，为客人提供愉快、舒适的住宿体验。一切从我们的“HI”开始。。。。。。 2005年初，华住在中国正式创立，同年8月，第1家门店开业，2006年底，旗下的汉庭酒店第34 家开业。2007年7月，华住以股权融资8500万美元创下中国服务行业首轮融资的新纪录，2007年底，汉庭酒店第74家开业。2008年初，汉庭在全国签约门店数达到180家，完成了全国主要城市的布局，并重 点在长三角、环渤海湾、珠三角和中西部发达城市形成了密布的酒店网络，成为国内成长最快的连锁酒店品牌之一。2008年4月，汉庭已开业酒店超过100家，出租率、经营业绩各项指标均在业内处于领先地位。 2008年2月，华住酒店集团正式成立，是国内第一家多品牌的酒店集团。华住致力于实现“中国服务”的理想，即打造世界级的中国服务品牌。华住的愿景是“成为世界住宿业领先品牌集团”，为此，我们将不断追求精细化的管理，实施标准化的体系和流程，更全面、更迅速地推进集团化发展。华住酒店集团旗下目前拥有禧玥酒店、星程酒店、汉庭酒店、全季酒店、海友酒店五个系列品牌，我们将坚持时尚现代、便捷舒适、高性价比的优势特点，塑造中国酒店的典范。

中华淘金网商业计划书--商业计划书

中华淘金网商业计划书--商业计划书 第一部分网页提案 目录 1、策略综述 2、意念的引入 3、站点基本描述 4、功能的实现以及费用的预算 5、项目进度安排 6、维护与升级 7、未来扩展项目 8、附录 1、意念的引入 在当前的网络社会中,由于技术上的原因,当前网民在网络中的自由受到诸多的限制。我们不妨将当前的网络世界比做人类社会发展史上的原始社会,当中的网民犹如原始社会中的原始人,在他们力所能及的网络空间内进行一系列的采集-狩猎活动。面对这些原始人,我们只能以非常简单的思维模式去考虑他们在网络空间的行为。 如何吸引他们到我们的网站进行采集--狩猎活动？ 人类的需要是多元化的。按马斯洛对人类需要的分层,结合当前网络社会的特点分析上网的人,他们在现实世界已解决了最基本生理需要,包括避免饥饿,逃避危险等,在网上虚拟的空间他们所追求,将是较高层次的多元化需求,如获得爱与尊重,实现自我价值。 如何才能满足网民高层次多元化需求的满足呢？ 一方面是简单的思维与行为模式,一方面是高层次多元化需求的满足。如何把这两方面有效的结合起来将是我们的网站成功的关键。 2、策略综述 利而诱之是我们的第一个策略。 综观当前的各类网站,主要为网民提供了各种各样的服务,包括提供各类的新闻、图片资讯;让网民注册,申请电子邮箱,免费主页空间,进行聊天;有的甚至提供物品的拍卖,网上购物服务,归根结底,他们就是要吸引网民的注意力,让他们在网站进行采集--狩猎活动。我们也将采取这一策略,但侧重于网络派钱的概念。 强调商业操作是我们的第二个策略

考察各种大众媒体工具(mass media)的发展史,我们可以看到每一种大众媒体工具（如广播,报纸,电视广播）的背后都有一套完善的商业操作,以及有效的资金来源支撑着。网络营运也必须找到它的资金来源。 在当今网络原始时代,众人都希望在网络营运中找到那只会下金蛋的母鸡。我们也不例外,一系列的商业操作（那只会下金蛋的母鸡）将是我们网站生存的关键。 倡导创意将是我们的第三个策略。 人是一种狡猾的动物,在原始本能驱动下所产生的动机,往往要堂而皇之地掩饰一番。为扩大我们网站的受众,提高我们网站的品位,倡导创意将是必不可少的。创意正是根源人类具有不安守本份的本能冲动。满足了人类这一本能冲动的网站将是成功的。 倡导多元化是我们的第四个策略 世界在网络的联结下变得越来越小,网络空间所聚集的人来自不同的国家地区,有着不同的需求。我们并不幻想以单一的网站满足网民的所有需要,但我们会以一系列网群的策划来实现多元化。 3、站点基本描述 A、站点结构概念 多面体两层结构:固定的STATION WEB SITE与流动的TOPIC WEB SITE,最大限度地网罗资讯与网民。我们所重视不是单一网站的概念,我们的视线亦将不再是局限于单一网站的建设,我们倡导网站群的概念,从整体上来规划一系列的网站。 我们这些单独网站之间的有机连接将形成一个以中华淘金网为首的网站群。 我们的网站群分为两类: 一类是两个固定的STATION WEB SITE,特点是长期存在,规模大,交互功能强,是进行BtoC、BtoB的服务界面。我们将设置一个主要的网站:面对网民和面对企业的的淘金网。 一类是一系列流动的TOPIC WEB SITE。特点是主题鲜明,内容简洁,规模小,极具娱乐性、艺术性与时效性,存在时间根据其主题以及赞助商来定,一般不超过一年。 固定的网站在一系列小型流动的网站包围下,互相进行功能的互补,分工是十分明确的。我们的设想是以淘金网为主导,通过淘金网进行一系列的市场营销活动以及市场调研活动,另一方面,淘金网又以有偿定向投稿的方式为一系列的流动主题网站提供源源不断的资讯更新。而流动主题网站则通过鲜明的主体吸引广大的网民进行浏览,以及引导网民进入我们的淘金网,负起扩大淘金网与外界联系的功能。

基于因子分析法的我国2012年各类型商业银行的经营业绩及排名

理学院课程项目 课程名称： 数据分析 题 目： 基于因子分析法的我国2012年各类型 商业银行的经营业绩及排名 班 级： 信科112 姓名学号： 冯力 11480010242 指导教师： 梁方楚 2014年5月30日

目录 摘要 (1) 1 问题的提出 (1) 2 研究背景 (1) 3 因子分析法的数学模型 (2) 3.1因子分析法的概念 (2) 3.2因子分析的计算步骤 (2) 4 样本的选择和指标体系的建立 (4) 4.1 样本的选择 (4) 4.2 我国上市银行经营绩效评价的指标选取 (4) 5 各类银行因子分析及其结果 (5) 5.1 数据查找 (5) 5.2数据处理 (5) 6 结论 (10) 7 参考文献 (11) 8 课程小结体会 (12) 附录 (13)

摘要 报告选取了中国银行，工商银行，建设银行，交通银行，中国农业银行，中信银行，中国民生银行，招商银行，中国兴业银行等16家具有代表性的国内上市商业银行作为此次研究的样本，这16家商业银行中包括5家国有控股商业银行，11家大中小型股份制商业银行，然后通过借鉴我国现行的商业银行业绩评价体系，最终确定了总资产收益率、人均利润、成本收入比、营业收入利润率、资本充足率、不良贷款率、拨备覆盖率、流动比率、存贷比率、存款增长率和非利息收入增长率为评价的11个指标，从各个方面对商业银行的经营业绩进行评价。 关键词：商业银行评价指标经营业绩因子分析

1 问题的提出 商业银行是经营货币资金、授受信用的特殊企业，是现代金融体系的重要组成部分。高效健全的银行体系能够为社会提供方便快捷的服务，安全稳健的银行经营对国民经济发展具有重要意义，同时经营绩效的高低不但会关系到银行本身能否良好运作，而且对整个国家宏观经济运行有着重大影响。 2 研究背景 随着我国银行业的全面开放，国内银行将面临更大的挑战和考验，在日益激烈的竞争环境中，商业银行提高经营绩效，增强竞争力势在必行。在这种背景下，按照现代商业银行经营绩效管理的要求，对我国的商业银行进行科学全面的评价，发现现阶段商业银行经营管理中存在的不足并提出应对方法，从而提高商业银行经营的绩效，就不仅是商业银行自身发展的客观需要，更是商业银行应对国际挑战和竞争的现实需要。

新员工带教流程

新员工带教流程 第一天： 熟悉公司的作息时间，了解公司基本状况，基本服务礼仪与动作规范，学习做迎宾。 1、上班时间：10:00---19:30 12:00----21:00 （转正前） 10:00--16:00 14:30---21:00（转正后） 备注：时间根据季节调整。 2、管理手册：P1、江明商贸简介（了解即可，店长须以解说的方式进行）； 3、服务礼仪：1）仪容仪表标准； 2）服务动作规范（站姿、蹲姿、距离、手势、角度）； 3）学习做迎宾（声音、表情、语调、迎宾位置）； 4）电话礼仪； 第二天： 了解公司的考勤制度，产品的风格分类及陈列 1、相关制度的了解：《考勤制度及请假报批程序》《离职程序》； 2、产品风格分类（①以鞋来区分：男鞋、女鞋、童鞋②以季节来区分：春秋单鞋、夏季凉鞋、冬靴③以鞋头区分：尖头、圆头、方头④以鞋跟来区分：平跟3CM以下、中跟3.1CM--5CM、高跟5.1CM---8CM、特高跟8.1CM 以上⑤以鞋帮来区分：凉（拖）鞋、中空鞋、浅口鞋、满帮（低腰）鞋、短靴（筒高14CM以下）、中靴（筒高15--22CM）、长靴（筒高23--36CM）；（以店铺现有货品实物讲解方式进行带教） 3、了解什么是陈列，为什么做陈列、陈列标准及陈列原则。 第三天： 掌握《会员卡》的办理及使用规范，相关票据的填写及操作流程，鞋类产品从哪六个方面进行描述。 1、“会员卡”的申办标准及使用细则； 2、相关票据：《销售单、销售退货单》《调拨单》《会员单》正确填写； 3、鞋类产品从：楦型、皮料、底材、高度、风格、线条六方面描述(以实物操作讲解带教为标准）； 4、服务1--2步：细节重点的掌握及实操应用。 第四天： 了解鞋类基本皮料、材质的特性及打理保养方法，所属品牌货号含义，FABE\法则应用，服务三、 四步，轮流做迎宾。 1、皮料特征及打理方法、皮料的分类（牛、羊、猪、打蜡、漆皮、磨砂皮）；（以店铺现有货品实物讲解方式进行带教） 2、了解所属品牌货号的含义； 3、服务技巧之FABE、含义理解及应用； 4、服务三、四步的细节重点的掌握及实操应用。 第五天： 学习掌握公司销售技巧及服务规范流程和语言表达标准、掌握做报表及相关单据技能，初步了解库存及货品摆放位置，服务五、六步、协助做销售。 1、销售技巧：ＵＳＰ／ＡＩＤＡ的含义及实操应用（以场景模拟带教实操为主） AIDA A:注意（Attention） 1）商品陈列 2）导购员的仪容、仪表 3）精神奕奕热忱的招呼（三声） 4）卖场气氛 I：兴趣（Interest） 1）接近顾客了解顾客购物动机 2）让顾客触摸商品 3）有效介绍货品的特性及卖点 4）为顾客做参谋 5）邀请试穿 D：欲望（Desire） 1）介绍FAB及USB 2）强调物超所值不可代替 3）化解顾客疑虑及异议 A：行动（Action） 1）把握时机完成交易 2）介绍打理知识 3）介绍其他配成产品 4）付款过程快速 USP（Unique selling piont）独特销售点： 质料、设计款式、手工、处理方法、色彩、价钱 2、开放式与封闭式的语言技巧：产品推荐：O O C 促成销售： C O C 3、初步了解库存及货品的摆放位置、辅助老员工做销售 4、掌握报表的正确填写、各项单据的电脑操作

0027~0030-旅游投资的商业模式研究――3L坐标分析法

旅游投资的商业模式研究――3L坐标分析法 2005年12月5日第3506期2005年12月12日第3509期 2005年12月19日第3512期2005年12月26日第3515期 杨光林峰 一、3L坐标分析法 民间投资商，已经成为旅游产业发展的主力军。这些旅游投资人，对于如何锁定风景及土地资源、如何确定项目的主题与市场定位、如何建设出具有吸引力的产品、如何实施有效的营销，最为重要的是如何获取盈利，都在反复思考，并感到不易把握。 投资商最关心的，就是如何获取利润。 旅游产业的综合行太强，投入大而获利周期长，因此盈利方式很难用简单的算数进行计算。对盈利方式中的盈利时序、盈利大小、盈利结构没有搞明白时，投资的决心是很难下定的。如果此时投资进入运作，往往会形成“摸着石头过河”的局面，走一步看一步。结果一般都是：效率低下，大走弯路。 旅游开发所涉的层面很多，开发运作环节复杂，交叉联动行业多。明晰的商业模式可以让投资者透过错综复杂的表象，看清具体项目的关键问题所在，项目的风险和利润所在，在具体的运作中能够从容以对。 因此，借助专业机构的经验与技术，进行旅游项目开发的商业模式设计，是投资商借脑中最重要的一个环节。 旅游商业模式设计――全面综合的研究旅游项目开发，系统解决锁定资源、定位主题与市场、设计并成型产品、制定营销战略，清晰建构盈利模式。 设计合理的商业模式需要实用有效的技术工具，通过该工具可以将投资过程中可能涉及到的各个层面和问题加以考虑，找出最适合项目的解决方案。 我们为此长期研究旅游产业经济及具体投资项目，并逐步建立了一套旅游投资商业模式专用分析工具――3L坐标分析法（或三链坐标分析法）。 通过持续的具体项目实践和理论研究，我们发现，由三个角度出发的链条（旅游业价值链、旅游开发运作链、旅游产业联动链）构成的坐标系（如下图所示）。在旅游产业中所有可能的商业模式，都能在该坐标系中找到位置；而任何旅游产业的项目，都可以运用3L坐标进行分析，从而发现盈利点、盈利结构，并由此形成商业模式的构架；对于旅游企业或正在经营中的旅游景区，运用3L坐标进行分析，可以对企业或景区进行诊断，发现其原有商业模式的缺陷，找到新的盈利增长点，寻找出可持续扩展的盈利新模式。

前台新进员工带教手册

一、海友酒店介绍 1.1 品牌故事 1.2 产品特征 1.3目标客户群 二、海友酒店前台交接班制度 交接班准备 交接事项 填写交接班本 接班事项 交接班签名 海友酒店前台员工带教计划带教目的 带教内容 海友酒店介绍：前台新进员工带教手册 目录

1.1 品牌故事 海友酒店是华住酒店集团（原汉庭酒店集团）旗下的风格经济型酒店连锁品牌，致力于为有预算要求的客人提供“欢乐、超值”的住宿产品。 我们全情投入，与顾客真诚沟通，分享快乐，为客人提供愉快、舒适的住宿体验。一切从我们的“HI”开始。。。。。。 2005 年初，华住在中国正式创立，同年8 月，第1 家门店开业，2006 年底，旗下的汉庭酒店第34 家开业。2007 年7 月，华住以股权融资8500 万美元创下中国服务行业首轮融资的新纪录，2007 年底，汉庭酒店第74 家开业。2008 年初，汉庭在全国签约门店数达到180 家，完成了全国主要城市的布局，并重点在长三角、环渤海湾、珠三角和中西部发达城市形成了密布的酒店网络，成为国内成长最快的连锁酒店品牌之一。2008 年4 月，汉庭已 开业酒店超过100 家，出租率、经营业绩各项指标均在业内处于领先地位。 2008 年2 月，华住酒店集团正式成立，是国内第一家多品牌的酒店集团。华住致力于实现“中国服务”的理想，即打造世界级的中国服务品牌。华住的愿景是“成为世界住宿业领先品牌集团”，为此，我们将不断追求精细化的管理，实施标准化的体系和流程，更全面、更迅速地推进集团化发展。华住酒店集团旗下目前拥有禧玥酒店、 星程酒店、汉庭酒店、全季酒店、海友酒店五个系列品牌，我们将坚持时尚现代、便捷舒适、高性价比的优势特点，塑造中国酒店的典范。 1.2 产品特征 装饰风格简约时尚 公共区域提供免费网吧 全酒店无线覆盖 独立淋浴、写字桌、电视机 提供大毛巾 自助理念 1.3 目标客户群 有预算要求的商务客人、家庭型散客、青年群体、长住客、背包客二、海友酒店前台交接班制度：交班前准备整理前台物品; 检查必备品和表格；

营销六步法

营销六步法 区域市场的运作是一个公司整体营销战略规划的一个有机组成部份；也是营销战略规划在执行中的具体体现。可以说，区域市场的操作成败在很大程度上决定着公司的整体营销业绩。根据个人的实践经验和书籍的查阅我认为，可以采取以下六个步骤来开展区域市场的营销工作： 一、划分区域市场，确定策略目标 首先，确定范围，定位类型，区域营销策略具体化。 通常来讲，市场与销售的开拓，总是存在一个逐步扩展的过程，很少有哪一家公司一开始就齐头并进地开发全国范围的市场。这就要求不同规模、实力的企业，不同产品结构的企业，必须确定大小不同的目标区域市场的空间范围。 在具体确定了区域范围后，必须对区域市场进行分类定位，划分出不同的区域类型，如大本营区域、根据地区域、运动区域、游击区域。不同类型的区域，推行不同的营销策略： 1、大本营区域是公司绝对占领（市场占有率在60%以上）的区域，对这类区域公司必须确保投入，将营销分支机构建立到县级甚至乡镇市场层面进行深度分销，牢固地占领终端网络对区域市场进行精耕细作； 2、根据地区域是公司绝对控制（市场占有率在40%以上）的区域，对这类区域公司应该重点投入，采取经销商与终端相结合的渠道策略（30%投入花在经销商身上70%投入花在终端上），有重点、针对性地与竞争对手开展竞争； 3、运动区域是公司没有相应的投入在短期内不容易占据主导地位的区域，

因此，最好避实就虚与对手开展竞争，在渠道上以零售终端带动经销商上量为主（70%投入花在经销商身上30%投入花在终端上），力争将市场占有率控制在20%左右； 4、游击区域是公司还没有客户基础的市场，对这类区域公司没有必要投入人财物力，采取现款现货的营销模式即可。 其次，进行区域细分，确定每个分区的具体业务拓展目标。 在确定了区域范围后，再综合考虑行政区划、人口数量、消费水平、交通条件、客户分布、政策投入等相关因素，将该区域进一步细分为若干个分区。并具体确定每个分区的市场开发和产品推广进度、目标任务（含销售数量和销售金额）、目标市场占有率、目标经销商和零售终端等分销客户的名称。如某医药生产企业将全国分为华中、华南、华北、华东等大区；再进一步又将华中分为河南、江西、安徽、湖南、重庆、湖北六个分区；其中湖北分区以"九州通""新龙"等经销商、以"中联""马应龙""同济堂""三九"等零售终端为目标客户，力争在2004年年底前实现销售额500万元，市场份额达到50%以上。 二、深入实际调查，建立客户档案 虽然确定了分区内的目标经销商和零售终端等分销客户的名称，但此时我们可能对它还一无所知或知有不尽，这就要求我们的业务人员必须进一步开展深入实际的调查工作，详细、真实地了解它们的相关情况。通常的做法是建立目标客户档案。客户建档工作有三点值得注意： 第一，档案信息必须全面详细。客户档案所反应的客户信息，是我们对该客户确定一对一的具体销售政策的重要依据。因此，档案的建立，除了客户名称、地址、联系人、电话这些最基本的信息之外，还应包括它的经营特色、行业地位

旅游投资的商业模式研究：3L坐标分析法-绿维创景

旅游投资的商业模式研究 ——3L坐标分析法旅游与文化规划设计专家旅游与文化导向的区域综合开发服务商 北京绿维创景规划设计院 New Dimension Planning & Design Institute Ltd. 旅游运营网https://www.sodocs.net/doc/975973816.html,旅游景观设计网https://www.sodocs.net/doc/975973816.html, 创意建筑设计网https://www.sodocs.net/doc/975973816.html,旅游投融资网https://www.sodocs.net/doc/975973816.html, 版权声明：该报告知识产权归北京绿维创景规划设计院所有，未经允许，不得擅自篡改、挪用、从事盈利性宣传活动，违者将追究法律责任。

旅游运营网 https://www.sodocs.net/doc/975973816.html, 旅游投资的商业模式研究 ——3L 坐标分析法 北京绿维创景规划设计院 一、3L 坐标分析法 民间投资商，已经成为旅游产业发展的主力军。这些旅游投资人，对于如何锁定风景及土地资源、如何确定项目的主题与市场定位、如何建设出具有吸引力的产品、如何实施有效的营销，最为重要的是如何获取盈利，都在反复思考，并感到不易把握。 投资商最关心的，就是如何获取利润。 旅游产业的综合行太强，投入大而获利周期长，因此盈利方式很难用简单的算数进行计算。对盈利方式中的盈利时序、盈利大小、盈利结构没有搞明白时，投资的决心是很难下定的。如果此时投资进入运作，往往会形成“摸着石头过河”的局面，走一步看一步。结果一般都是：效率低下，大走弯路。 旅游开发所涉的层面很多，开发运作环节复杂，交叉联动行业多。明晰的商业模式可以让投资者透过错综复杂的表象，看清具体项目的关键问题所在，项目的风险和利润所在，在具体的运作中能够从容以对。 因此，借助专业机构的经验与技术，进行旅游项目开发的商业模式设计，是投资商借脑中最重要的一个环节。

商业项目招商的各种说法操作方法牢骚及案例

商业项目招商的各种说法操作方法牢骚及案例 Document serial number【UU89WT-UU98YT-UU8CB-UUUT-UUT108】

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或者最多，达到两页，你已经说了太多的历史了。要是公司有个特别精彩的经历，那也许可以作为一个特别的理由来囊括大段的历史，但无论如何都要简洁。 2.04业务的前景 说清楚公司的年次发展计划并指出其中的分界线。实际上，投资者需要了解你如何在五年内从现在所处的状况发展到你想要达到的状况。尽管计划书的这一部分必须要简洁，但在格式上有相当大的自由度。你可以简单地说明在接下来的五年里你打算继续生产你们的两种基本产品，到第三年的时候你将引入另一个类似的产品。依照这样的办法，你的业务的前景将会简洁而又切中要害。另外，如果你预料在达到稳定点前要经历许多变化，你应该指出会发生哪些变化。投资者需要准确地了解公司要获得成功必须做些什么。 2.05独特之处 给投资者的每份都应该有一些独特之处。管理层独特?产品或服务独特?生产过程独特?有独特的金融基础?所有的这些都可以囊括在内。重要的是要有一些东西使你的公司在和别的对投资者来说同样可得的投资机会的对比中凸现出来。投资者们不喜欢投资于“人云亦云”的公司。他们想要有独特的商业地位的公司。在一个像这样的单独的章节中，或是在整篇商业计划的各章节中，你要着重强调你公司的独特之处。如果你的业务里有一个新产品，一个生产的专利，或是别的特别不寻常的方面，那么应该像这样在单独一章里列出。除了要包括这部分之外，企业主还应在中间歇地突出公司。 2.06产品或服务 在这部分你要精确的描述你的产品或服务，要求是不给读者对于你所生产的或是计划生产的东西留下疑问。如果你有好几种产品或服务，用单独的段落来叙述其中的每一种。你应叙述产品的价格，价格如何确定以及毛利数目。企业主容易轻率地对待产品的定价。花足够的时间来考虑所有影响产品定价的因素，确信你能够用坦率而有逻辑的话来解释定价背后的道理。是因为竞争迫使价格趋向于那个方向吗?价格定得高是因为你能侥幸成功吗?你必须准备回答这些问题。

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新员工带教手册

新员工带教教程

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8）公司的文件、资料要妥善保管，严守秘密 9）工作时间不得接访亲友、朋友，可在休息时间接待 10）店内工作中不得使用手机闲聊或阅览网页及游戏 11）未经主管同意不得私自调班，未经批准不得不参加公司会议 12）必须按规定将货款交至收银台，自行收银店铺必须在规定时间内将货款存入公司规定银行账号，不得用职务之便私扣营业款 13）不得私自占有顾客遗失物品或损坏顾客财务 14）不得在公司或店铺内吵闹、粗言秽语和打架 15）不得将公司设备、财务、货品挪为私用，更不得偷盗或占为己有 16）货物盘点时如发现货品不正常流失，应第一时间向上级汇报； 17）不得私自为顾客打折 18）未经主管同意不得擅自为顾客换货、挑货、退货 19）员工之间互相帮助，团结友爱，有团队合作精神 2.服务行为规定 1）店内接待客人时应充分展示自身形象，严格按照公司《服务标准》执行，向客人树立良好的公司形象 2）柜台迎宾站姿端正，销售人员面带微笑 3）客人到柜及喊宾时，身体微鞠躬示意，声音适中，用好礼貌用语，为顾客提供超一流的服务 4）销售人员应积极主动给予顾客提供帮助，用语言引导顾客。 5）接待顾客过程中，注意语言行为应用，不要给客人留下不好印象 6）充分展示个人魅力，推广宣传自身品牌 7）销售人员应严格约束、自律、礼貌的为客人提供最优质的售后服务 3.柜台形象及卫生清洁责任制 1）按公司要求标准化陈列 2）内务货品摆放整洁，归纳清晰 3）私人物品摆放整洁 4）柜台所需设备及物品（税控机、POS机、扫码枪、生财物品及柜台陈列设施等）不得丢失及损坏 5）销售柜台坚决执行公司规定的清洁标准（1、柜台清洁无死角，灯箱明亮无损坏，光影投射位置准确，玻璃及陈列物品清洁无指纹及灰尘）（详见品牌形象篇） 6）柜台卫生监管制度为-当班值日员工做好柜台清洁后，填写店铺每日形象自查表，由店长或对班在检查人一栏签字确认 备注:具体员工准则参照《员工管理制度及行为规范》 3-2仪容仪表