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MSM6242B中文资料

? Semiconductor

MSM6242B

DESCRIPTION

The MSM6242B is a silicon gate CMOS Real Time Clock/Calendar for use in direct bus-connection M icroprocessor/M icrocomputer applications. An on-chip 32.768 KHz crystal oscillator time base is divided to provide ad-dressable 4-bit I/O data for SECONDS,MINUTES, HOURS, DAY OF WEEK, DATE,MONTH and YEAR. Data access is controlled by 4-bit address, chip selects (CSO , CS1),WRITE , READ , and ALE. Control Registers D, E and F provide for 30 SECOND error adjustment, INTERRUPT REQUEST (IRQ FLAG) and BUSY status bits, clock STOP,HOLD, and RESET FLAG bits, 4 selectable INTERRUPTS rates are available at the STD.P

? Semiconductor MSM6242B

DIRECT BUS CONNECTED CMOS REAL TIME CLOCK/CALENDAR

(STANDARD PULSE) output utilizing Con-trol Register inputs T0, T1 and the ITRPT/STND (INTERRUPT/STANDARD). M ask-ing of the interrupt output (STD.P) can be accomplished via the M ASK bit. The MSM6242B can operate in a 12/24 hour for-mat and Leap Year timing is automatic.The MSM6242B normally operates from a 5V ±10% supply at –40 to 85°C. Battery backup operation down to 2.0V allows continuation of time keeping when main power is off. The MSM6242B is offered in a 18-pin plastic DIP and a 24-pin plastic Small Outline package.

FEATURES

DIRECT MICROPROCESSOR/MICROCONTROLLER BUS CONNECTION TIME MONTH

DATE YEAR DAY OF WEEK

23:59:59

807

?4-bit data bus ?4-bit address bus

?READ , WRITE , ALE and CHIP SELECT

INPUTS

?Status registers – IRQ and BUSY ?Selectable interrupt outputs – 1/64

second, 1 second, 1 minute, 1 hour ?Interrupt masking

?32.768 KHz crystal controlled operation

?12/24 hour format ?Auto leap year

?±30 second error correction ?Single 5V supply

?Battery backup down to V DD = 2.0V ?

Low power dissipation:

20μW max at V DD = 2V 150μW max at V DD = 5V

?18 pin Plastic DIP (DIP18-P-300)

?24 Pin-V Plastic SOP (SOP24-P-430-VK)

元器件交易网https://www.sodocs.net/doc/ae368809.html,

FUNCTIONAL BLOCK DIAGRAM

18 pin Plastic DIP

118STD.P CS 0ALE A 0A 1A 2A 3GND

V DD CS 1XT 2173164155146137128119

24 pin Plastic Small Outline Package

PIN CONFIGURATION

RD D 0D 1D 2D 3XT WR

STD.P NC ALE NC NC A 0A 1A 2A 3GND V DD CS 1XT D 0D 1D 2D 3XT WR

NC NC NC CS 0RD 123456789101112242322212019181716151413A 0-A 3:D 0-D 3:CS O , CS 1:RD :ALE:STD.P:V DD:V SS:Address input Data input/output CHIP SELECTS 0,1READ enable WRITE enable

Address latch enable Standard pulse output

XTAL oscillator input/output +5V supply ground

WR :XT,XT :

Note 1)Note 2)Note 3)Note 4)

Address

Input Count value Description D 3REGISTER TABLE

012341-second digit register 10-second digit register 1-minute digit register 10-minute digit register 1-hour digit register 0 to 90 to 50 to 90 to 50 to 9ITRPT

/STND 0 to 2or 0 to 16789A B C

D E 5Address Input

Data

A 31-day digit register 10-day digit register 1-month digit register 10-month digit register 1-year digit register 10-year digit register Week register

Control Register D

Control Register E Control Register F

0 to 90 to 30 to 90 to 10 to 90 to 90 to 6

———

S 1S 10mi 1mi 10h 1

h 10d 1d 10mo 1MO 10y 1y 10w 1

HOLD MASK

REST

S 2S 20mi 2mi 20h 2h 20d 2d 20mo 2*y 2y 20w 2

BUSY STOP

S 4S 40mi 4mi 40h 4PM/

AM d 4*mo 4*y 4y 40w 4

IRQ FLAG

t 024/12

S 8*mi 8*h 8

TEST

d 8*mo 8*y 8y 80*30sec.ADJ

t 1S 1S 10MI 1MI 10H 1H 10D 1D 10MO 1MO 10Y 1Y 10W

C D

C E C F

D 2D 1D 0A 2A 1A 00000000011111

111

0000111100001

111

011

0011001100110

011

0101010101010

REST = RESET

ITRPT/STND = INTERRUPT/STANDARD Bit * does not exist (unrecognized during a write and held at "0" during a read).Be sure to mask the AM/PM bit when processing 10's of hour's data.

BUSY bit is read only. The IRQ FLAG bit can only be set to a "0". Setting the IRQ FLAG to a "1" is done by hardware.

PM at 1 and AM at 0 for PM / AM bit.

Figure 1. Register Table

PM/AM, 10-hour digit

OSCILLATOR FREQUENCY DEVIATIONS

-60

-40-20020

-100

-50

0Ta (°C)

?f /f (P

P M )

010

-1-2-3-4

V DD (V)

?f /f (P P M )

123456

Ta = 25°C

Figure 2. Frequency Deviation (PPM) vs Temperature

Figure 3. Frequency Deviation (PPM) vs Voltage

1. The graghs above showing frequency deviation vs temperature/voltage are primarily characteristic of the MSM6242B with the oscillation circuit described below.

Note:

Parameter

Symbol Condition

Rating Unit Power Supply Voltage Input Voltage Output Voltage Storage Temperature

Ta = 25°C ABSOLUTE MAXIMUM RATINGS

-0. 3 to 7-0.3 to V DD +0.3-0.3 to V DD +0.3-55 to +150

V DD V I V O T STG

V V V °C

Parameter

Symbol Condition

Rating Unit Power Supply Voltage Standby Supply Voltage Crystal Frequency Operating Temperature

OPERATING CONDITIONS

4 to 62 to 632.768-40 to +85

V DD V BAK f (XT)T OP

kHz °C ————

Parameter Condition

Min.Unit "H" Input Voltage "L" Input Voltage

Input Leak Current Input Leak Current "L" Output Voltage "H" Output Voltage "L" Output Voltage OFF Leak Current D.C. Characteristics

Current Con-sumption Current Con-sumption "H" Input Voltage "L" Input Voltage

Input Capacitance All input termin-als except CS 1, XT Input terminals other than D 0 ~ D 3, XT D 0 ~ D 3

D 0 ~ D 3

STD.P All input terminals V DD

CS 1

Applicable

Terminal ——

V I = V DD /0V

KHz

CS 1 0V DD =

5V V DD =2V

f (xt) =32.768Symbol V IH 1V IL 1

I LK 1

I LK 2V OL 1V OH V OL 2I OFFLK C I I DD 1I DD 2V IH 2V IL 2

I OL = 2.5mA I OH = -400μA I OL = 2.5mA V = V DD /0V V DD = 2 ~ 5.5V Input frequency

1MHz V

μA

V V μA μA

Typ.Max.2.2—

———2.4—————4/5V DD —

——

——————5———

—0.8

1/-1

10/-100.4—0.410—30

10—1/5V DD

(V DD = 5V ± 10%, T A = -40 ~ +85)

—~

Parameter Symbol Condition

Min.Unit

CS 1 Set up Time Address Set up Time Address Hold Time ALE Pulse Width ALE Before WRITE WRITE Pulse Width ALE After WRITE DATA Set up Time DATA Hold Time CS 1 Hold Time

RD / WR Recovery Time

—t C1S t AS t AH t AW t ALW t WW t WAL t DS t DH t C1H t RCV

ns (2) WRITE mode (With use of ALE)

(V DD = 5V ± 10%, Ta = -40 ~ +85°C)

Max.—————————————1000252540101202010010100060

———————

—

Parameter Symbol Condition Min.Unit

CS 1 Set up Time CS 1 Hold Time —SWITCHING CHARACTERISTICS

t C1S t C1H ns

(1) WRITE mode (ALE = V DD )

(V DD = 5V ± 10% Ta = -40 to +85°C)

Max.Address Stable Before

WRITE

Address Stable After WRITE

WRITE Pulse Width Data Set up Time Data Hold Time RD / WR Recovery Time

—————————————t AW t WA t WW t DS t DH t RCV

1000100020101201001060

—

Parameter Symbol Condition Min.Unit

CS 1 Set up Time CS 1 Hold Time —t C1S t C1H ns

(3) READ mode (ALE = V DD )

Max.Address Stable before READ

Address Stable after READ RD to Data Data Hold

RD / WR Recovery Time

———C L = 150pF

————

—120—t AR t RA t RD t DR t RCV

10001000200— 060

(V DD = 5V ± 10%, Ta = -40 to +85°C)

—

Parameter Symbol Condition Min.Unit

CS1 Set up Time Address Set up Time Address Hold Time ALE Pulse Width

ALE before READ

ALE after READ

RD to Data

DATA Hold

CS1 Hold Time

RD / WR Recovery Time

—

t C1S

t AS

t AH

t AW

t ALR

t RAL

t RD

t DR

t C1H

t RCV

(4) READ mode (With use of ALE)

(V DD = 5V ± 10%, Ta = -40 to +85°C)

Max.

—

C L = 150pF

—

120

—

—1000

—

1000

—

———

PIN DESCRIPTION

FUNCTIONAL DESCRIPTION OF REGISTERS

1, S

, MI

, H

, D

, MO

, Y

, W

a)These are abbreviations for SECOND1, SECOND10, MI NUTE1, MI NUTE10, HOUR1,

HOUR10, DAY1, DAY10, MONTH1, MONTH10, YEAR1, YEAR10, and WEEK. These values are in BCD notation.

b)All registers are logically positive. For example, (S8, S4, S2, S1) = 1001 which means 9

seconds.

c)If data is written which is out of the clock register data limits, it can result in erroneous clock

data being read back.

d)PM/AM, h

20, h

In the mode setting of 24-hour mode, PM/AM bit is ignored, while in the setting of 12-hour

mode h

20 is to be set. Otherwise it causes a discrepancy. In reading out the PM/AM bit in

the 24-hour mode, it is continuously read out as 0. I n reading out h

20 bit in the 12-hour mode,

0 is written into this bit first, then it is continuously read out as 0 unless 1 is being written

into this bit.

e)Registers Y1, Y10, and Leap Year. The MSM6242B is designed exclusively for the Christian

Era and is capable of identifying a leap year automatically. The result of the setting of a non-existant day of the month is shown in the following example: If the date February 29 or November 31, 1985, was written, it would be changed automatically to March 1, or December 1, 1985 at the exact time at which a carry pulse occurs for the day's digit.

f)The Register W data limits are 0 – 6 (Tabel 1 shows a possible data definition).

TABLE 1

w4 0 0 0 0 1 1 1w2

Day of Week

Sunday

Monday

Tuesday

Wednesday

Thursday

Friday

Saturday

CD REGISTER (Control D Register)a)

HOLD (D0) –

Setting this bit to a "1" inhibits the 1Hz clock to the S1 counter, at which time the Busy status bit can be read. When Busy = 0, register's S 1 ~ W can be read or written. During this procedure if a carry occurs the S1counter will be incremented by 1 second after HOLD = 0 (this condition is guaranteed as long as HOLD = 1 does not exceed 1 second in duration). If CS1 = 0 then HOLD = 0 irrespective of any condition.

b)BUSY (D1) –Status bit which shows the interface condition with microcontroller/

microprocessors. As for the method of writing into and reading from S 1 ~ W (address φ ~ C), refer to the flow chart described in Figure 10.

IRQ FLAG (D2) –This status bit corresponds to the output level of the STD.P output.

When STD.P = 0, then IRQ = 1; when STD.P = 1, then IRQ = 0. The IRQ FLAG indicates that an interrupt has occurred to the microcomputer if IRQ = 1. When D0 of register C E (MASK) = 0, then the STD.P output changes according to the timing set by D3 (t 1) and D2 (t 0) of register E.When D1 of register E (ITRPT/STND) = 1 (interrupt mode), the STD.P output remains low until the IRQ FLAG is written to a "0". When IRQ = 1 and timing for a new interrupt occurs, the new interrupt is ignored.When ITRPT/STND = 0 (Standard Pulse Output mode) the STD.P output remains low until either "0" is written to the I RQ FLAG;otherwise, the IRQ FLAG automatically goes to "0" after 7.8125ms.When writing the HOLD or 30 second adjust bits of register D, it is necessary to write the IRQ FLAG bit to a "1".

±30 ADJ (D3) –When 30-second adjustment is necessary, a "1" is written to bit D3

during which time the internal clock registers should not be read from or written to 125μs after bit D3 = 1 it will automatically return to a "0",and at that time reading or writing of registers can occur.

c)24/12 (D2) –This bit is for selection of 24/12 hour time modes. If D2 = 1–24 hour mode is selected and the PM/AM bit is invalid. If D2 = 0–12 hour mode is selected and the PM/AM bit is valid.

"24/HOUR/Setting of the 24/12 hour bit is as follows:12 HOUR"

1) REST bit = 1

2) 24/12 hour bit = 0 or 13) REST bit = 0

* REST bit must = 1 to write to the 24/12 hour bit.

d)TEST (D3) –

When the TEST flag is a "1", the input to the SECONDS counter comes from the counter/divider stage instead of the 15th divider stage. This makes the SECONDS counter count at 5.4163KHz instead of 1Hz. When TEST = 1 (Test Mode) the STOP & REST (Reset) flags do not inhibit internal counting. When Hold = 1 during Test (Test = 1) internal counting is inhibited; however, when the HOLD FLAG goes inactive (Hold = 0)

counter updating is not guaranteed.

d)The low-level pulse width of the fixed cycle waveform (ITRPT/STND = 0) is 7.8125ms independent of T0/T1 inputs.

e)The fixed cycle waveform mode can be used for adjustment of the oscillator frequency time base. (See Figure 14).

f)During ±30 second adjustment a carry can occur that will cause the STD.P output to go low when T0/T1 = 1,0 or 1,1. However, when T1/T0 = 0, 0 and ITRPT/STND = 0, carry does not occur and the STD.P output resumes normal operation.

g)The STD.P output is held (frozen) at the point at which STOP = 1 while ITRPT/STND = 0.h)No STD.P output change occurs as a result of writing data to registers S1 ~ H1.

C F REGISTER (Control F Register)a)

REST (D0) –This bit is used to clear the clock's internal divider/counter of less than a "RESET"second. When REST = 1, the counter is Reset for the duration of REST. In order to release this counter from Reset, a "0" must be written to the REST bit. If CSI = 0 then REST = 0 automatically.

STOP (D1) –

The STOP FLAG Only inhibits carries into the 8192Hz divider stage.There may be up to 122μs delay before timing starts or stops after changing this flag; 1 = STOP/0 = RUN.

TYPICAL APPLICATION INTERFACE WITH MSM6242B AND MICROCONTROLLERS

TYPICAL APPLICATIONS — INTERFACE WITH MSM80C49

2. Adjustment of Frequency

Set the current

time START

Power On

APPLICATION NOTE

1. Power Supply

TEST Bit ← 0REST Bit ← 024/12 Bit ← 1*STOP Bit ← 1

HOLD Bit ← 0STOP Bit ← 0

Start Operation

V DD = 5V

STD.P

Output = undifined

1* = 2*(1 or 0)

REST Bit ← 024/12 Bit ← 2*

3. CH 1 (Chip Select)

V IH and V IL of CH 1 has 3 functions.

a)To accomplish the interface with a microcontroller/microprocessor.

b)To inhibit the control bus, data bus and address bus and to reduce input gate pass

current in the stand-by mode.

c)To protect internal data when the mode is moved to and from standby mode.

To realize the above functions:

a)More than 4/5 V DD shoud be applied to the MSM6242B for the interface with a

microcontroller/microprocessor in 5V operation.

b)In moving to the standby mode, 1/5 V DD should be applied so that all data buses should

be disabled. In the standby mode, approx. 0V should be applied.c)To and from the standby mode, obey following Timing chart.

4. Set SDT.P at alarm mode

TYPICAL APPLICATION — POWER SUPPLY CIRCUIT

MSM6242B中文资料

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