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AM335x Chapter 10 Interconnects

Chapter10

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Interconnects

This chapter describes the interconnects of the device.

Topic Page

10.1Introduction (990)

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The system interconnect is based on a2-level hierarchical architecture(L3,L4)driven by system

performance.The L4interconnect is based on a fully native OCP infrastructure,directly complying with the OCPIP2.2reference standard.

10.1.1Terminology

The following is a brief explanation of some terms used in this document:

Initiator:Module able to initiate read and write requests to the chip interconnect(typically:processors, DMA,etc.).

Target:Unlike an initiator,a target module cannot generate read/write requests to the chip interconnect, but it can respond to these requests.However,it may generate interrupts or a DMA request to the system (typically:peripherals,memory controllers).Note:A module can have several separate ports;therefore,a module can be an initiator and a target.

Agent:Each connection of one module to one interconnect is done using an agent,which is an adaptation (sometimes configurable)between the module and the interconnect.A target module is connected by a target agent(TA),and an initiator module is connected by an initiator agent(IA).

Interconnect:The decoding,routing,and arbitration logic that enable the connection between multiple initiator modules and multiple target modules connected on it.

Data-flow Signal:Any signal that is part of a clearly identified transfer or data flow(typically:command, address,byte enables,etc.).Signal behavior is defined by the protocol semantics.

Sideband Signal:Any signal whose behavior is not associated to a precise transaction or data flow.

Command Slot:A command slot is a subset of the command list.It is the memory buffer for a single

command.A total of32command slots exist.

Out-of-band Error:Any signal whose behavior is associated to a device error-reporting scheme,as

opposed to in-band errors.Note:Interrupt requests and DMA requests are not routed by the interconnect in the device.

ConnID:Any transaction in the system interconnect is tagged by an in-band qualifier ConnID,which

uniquely identifies the initiator at a given interconnect point.A ConnID is transmitted in band with the

request and is used for error-logging mechanism.

10.1.2L3Interconnect

The L3high-performance interconnect is based on a Network-On-Chip(NoC)interconnect infrastructure.

The NoC uses an internal packet-based protocol for forward(read command,write command with data payload)and backward(read response with data payload,write response)transactions.All exposed

interfaces of this NoC interconnect,both for Targets and Initiators;comply with the OCPIP2.2reference standard.

10.1.2.1L3Topology

The L3topology is driven by performance requirements,bus types,and clocking structure.The main L3 paths are shown in Figure10-1.Arrows indicate the master/slave relationship not data flow.L3is

partitioned into two separate clock domains:L3F corresponds to L3Fast clock domain and L3S

corresponds to L3Slow clock domain.

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Figure 10-1.L3Topology

10.1.2.2L3Port Mapping

Each initiator and target core is connected to the L3interconnect through a Network Interface Unit (NIU).The NIUs act as entry and exit points to the L3Network on Chip –converting between the IP’s OCP protocol and the NoC’s internal protocol,and also include various programming registers.All ports are single threaded with tags used to enable pipelined transactions.The interconnect includes:Initiator Ports :?L3F

–Cortex A8MPUSS 128-bit initiator port0and 64-bit initiator port1–SGX530128-bit initiator port

–3TPTC 128-bit read initiator ports –3TPTC 128-bit write initiator ports –LCDC 32-bit initiator port

–2PRU-ICSS132-bit initiator ports

–2port Gigabit Ethernet Switch (2PGSW)32-bit initiator port –Debug Subsystem 32-bit initiator port ?L3S

–USB 32-bit CPPI DMA initiator port

–USB 32-bit Queue Manager initiator port –P150032-bit initiator port Target Ports :?L3F

–EMIF 128-bit target port

–3TPTC CFG 32-bit target ports –TPCC CFG 32-bit target port –OCM RAM064-bit target port –DebugSS 32-bit target port –SGX53064-bit target port –L4_FAST 32-bit target port ?L3S

–4L4_PER peripheral 32-bit target ports –GPMC 32-bit target port –McASP032-bit target port

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Introduction https://www.sodocs.net/doc/b85870508.html, –McASP132-bit target port

–ADC_TSC32-bit target port

–USB32-bit target port

–MMHCS232-bit target port

–L4_WKUP wakeup32-bit target port

10.1.2.3Interconnect Requirements

The required L3connections between bus masters and slave ports are shown in Table10-1.The L3

interconnect will return an address-hole error if any initiator attempts to access a target to which it has no connection.

Table10-1.L3Master—Slave Connectivity

Slaves

E O T T S E A S L L L L L G A U M L L D N

M C P P G x E H44444P D S M44e O

I M T C X p S A_____M C/B C__b C

F C C C5a0F P P P P C T C H W F u R

R03n a E E E E S F S K W g e

A–0s s R R R R C G2U S g Master ID Masters

M2i t P P P P P S i

C o o o o o s

F n r r r r t

G S t t t t e

l0123r

o s

0x00MPUSS M1(128-bit)R

0x00MPUSS M2(64-bit)R R R R R R R R R R R R R R R R R R 0x18TPTC0RD R R R R R R R R R R R R R

0x19TPTC0WR R R R R R R R R R R R R R R

0x1A TPTC1RD R R R R R R R R R R R R R

0x1B TPTC1WR R R R R R R R R R R R R R

0x1C TPTC2RD R R R R R R R R R R R R R

0x1D TPTC2WR R R R R R R R R R R R R R

0x24LCD Controller R R R

0x0E PRU-ICSS(PRU0)R R R R R R R R R R R R 0x0F PRU-ICSS(PRU1)R R R R R R R R R R R R 0x30GEMAC R R R

0x20SGX530R R R

0x34USB0DMA R R

0x35USB1Queue Mgr R R R

0x04EMU(DAP)R R R R R R R R R R R R R R R R R R 0x05IEEE1500R R R R R R R R R R R R R R R R R R

10.1.2.4ConnID Assignment

Each L3initiator includes a unique6-bit master connection identifier(MConnID)that is used to indentify the source of a transfer request.Since AM335x contains more than16unique masters some masters will appear identical to target firewalls.

Table10-2.MConnID Assignment

Initiator6-bit MConnID(Debug)Instrumentation Comment

MPUSS M1(128-bit)0x000Connects only to EMIF

MPUSS M2(64-bit)0x01SW

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Table10-2.MConnID Assignment(continued)

Initiator6-bit MConnID(Debug)Instrumentation Comment

DAP0x04SW

P15000x05SW

PRU-ICSS(PRU0)0x0E SW

PRU-ICSS(PRU1)0x0F SW

Wakeup M30x14SW Connects only to L4_WKUP TPTC0Read0x180

TPTC0Write0x19SW One WR port for data logging TPTC1Read0x1A0

TPTC1Write0x1B0

TPTC2Read0x1C0

TPTC2Write0x1D0

SGX5300x200

OCP WP Traffic Probe0x20(1)HW Direct connect to DebugSS

OCP WP DMA Profiling0x21(1)HW Direct connect to DebugSS

OCP-WP Event Trace0x22(1)HW Direct connect to DebugSS

LCD Ctrl0x240

GEMAC0x300

USB DMA0x340

USB QMGR0x350

Stat Collector00x3C HW

Stat Collector10x3D HW

Stat Collector20x3E HW

Stat Collector30x3F HW

(1)These MConnIDs are generated within the OCP-WP module based on the H0,H1,and H2configuration parameters.

NOTE:Instrumentation refers to debug type.SW instrumentation means that the master can write

data to be logged to the STM(similar to a printf()).HW indicates debug data captured

automatically by hardware.A'0'entry indicates no debug capability.

10.1.3L4Interconnect

The L4interconnect is a non-blocking peripheral interconnect that provides low latency access to a large number of low bandwidth,physically dispersed target cores.The L4can handle incoming traffic from up to four initiators and can distribute those communication requests to and collect related responses from up to 63targets.

AM335x provides three interfaces with L3interconnect for High Speed Peripheral,Standard Peripheral, and Wakeup Peripherals..Figure10-2shows the L4bus architecture and memory-mapped peripherals.

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Figure 10-2.L4Topology

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AM335x Chapter 10 Interconnects

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