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PT6880中文资料

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OLED Driver/Controller IC Description
Preliminary
PT6880
PT6880 is an OLED Driver/Controller IC utilizing CMOS Technology specially designed to display alphanumeric and Japanese kana characters as well as symbols and graphics. It can interface with either 4-bit or 8-bit Microprocessor and display up to one 8-character line or two 8-character lines. Display RAM, Character Generator, OLED Driver as well as a wide range of instruction functions such as Display Clear, Cursor Home, Display ON/OFF, Cursor ON/OFF, Display Character Blink, Cursor Shift, Display Shift are all incorporated into a single chip having the highest performance and reliability. Pin assignments and application circuit are optimized for easy PCB layout and cost saving advantages.
Features
CMOS Technology Low Power Consumption 4-Bit or 8-Bit MPU Interface High Speed MPU Interface: 2MHz (VDD =5V) 80 x 8-Bit Display RAM (80 characters max.) Auto Reset Function 5 x 8 and 5 x 10 Dot Matrix Built-in Oscillator with External Resistors Programmable Duty Cycle: - 1/8 Duty: (1 Display Line, 5 x 8 Dots with Cursor) - 1/11 Duty: (1 Display Line, 5 x 10 Dots with Cursor) - 1/16 Duty: (2 Display Lines, 5 x 8 Dots with Cursor) 9920-Bit Character Generator ROM (CGROM) - 208 Character Fonts (5 x 8 dot matrix) - 32 Character Fonts (5 x 10 dot matrix) 64 x 8-Bit Character Generator RAM (CGRAM) - 8 Character Fonts (5 x 8 dot matrix) - 4 Character Fonts ( 5 x 10 dot matrix) 16 Common x 40 Segment OLED Drivers Available in C.O.B. or QFP Package
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OLED Driver/Controller IC Applications
Cellular Phone Data Bank/Organizer Electronic Dictionary / Translator Information Appliance P.D.A. P.O.S. Car Audio Electronic Equipment with OLED Display
Preliminary
PT6880
PT6880 pre 1.1
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OLED Driver/Controller IC Block Diagram
DISB OSC1 OSC2 CL LAT
Preliminary
PT6880
RESET CIRCUIT
OSCILLATION CIRCUIT
TIMING GENERATOR COM1 16-BIT SHIFT REGISTER COMMON SIGNAL DRIVER COM2 COM15 COM16
RS R/WB E DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 8 INPUT/ OUTPUT BUFFER MPU INTERFACE 8
INSTRUCTION REGISTER
INSTRUCTION DECODER
SG1 ADDRESS COUNTER 7 7 DISPLAY DATA RAM (DDRAM) 80x8 BITS SG2 40-BIT SHIFT REGISTER 40-BIT LATCH CIRCUIT SEGMENT SIGNAL DRIVER
SG39 SG40
DATA REGISTER 8 8 8 CHARACTER GENERATOR ROM (CGROM) 9920 BITS CURSOR AND BLINK CONTROLLER OLED DRIVE VOLTAGE 40
D
BUSY FLAG
CHARACTER GENERATOR RAM (CGRAM) 64 BYTES
REFOUT V16 SEGG DVR BVR VDD GND
5
5 PARALLEL / SERIAL CONVERTER AND ATTRIBUTE CIRCUIT
PT6880 pre 1.1
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OLED Driver/Controller IC Pin Configuration
100 99 98 97 96 95 94 93 92 91 90 89 88
Preliminary
PT6880
SG39 SG40 V16 COM16 COM15 COM14 87 86 85
NC SG30 SG31 SG32 SG33 SG34 SG35 SG36 SG37 SG38
84 83 82 81
COM13 COM12 COM11 COM10
SG29 NC SG28 NC SG27 SG26 SG25 SG24 SG23 SG22 SG21 SG20 SG19 SG18 SG17 SG16 SG15 SG14 SG13 SG12 SG11 SG10 SG9 NC NC NC NC NC NC SG8
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 VSS 41 VSS 42 OSC1 43 OSC2 44 BVR 45 DVR 46 47 48 49 50
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
COM9 NC NC NC NC NC NC COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 VSS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 E R/WB NC RS NC D
Pin/Pad Description
PT6880 pre 1.1 Page 4 Mar. 2002
SG7 SG6 SG5 SG4 SG3 SG2 SG1 SEGG REFOUT V16
LAT CL VDD DISB

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OLED Driver/Controller IC
Pin Name SG40 ~ SG30 SG29, SG 28 SG27 ~ SG9 SG8 ~ SG1 SEGG REFOUT V16 VSS OSC1 OSC2 BVR DVR LAT CL VDD DISB D I/O
Preliminary
Description
PT6880
Pad/Pin No. 89 ~ 99 1,3 5 ~ 23 30 ~ 37 38 39 40, 88 41, 42, 65 43 44 45 46 47 48 49 50 51
O
Segment Driver Output Pins
O I O I I O O O O
OLED Drive Power Supply (0V) Reference Current Output Pin OLED Drive Power Supply (16V) Ground Pin (0V) Oscillator Input Pin Oscillator Output Pin Brightness Control Input Pin Precharge Time Control Input Pin Latch Clock Output Pin Shift Clock Output Pin Power Supply (2.7V to 5.5V) Reset Signal Output Pin Character Pattern Data Output Pin Register Select Input Pin When this pin is set to "0", it is used as an Instruction Register. When this pin is set to "1", it is used for as the Data Register. Read/Write Control Input Pin This pin is used to select either the Write or the Read Operation. If this pin is set to "0", then the Write Function is enabled. If this pin is set to "1", then the Read function is enabled. Data Read/Write Start Control Pin Low Order Bidirectional Data I/O Pins These pins are used for data transfer and reception between the MPU and PT6880. These
Page 5
RS
I
53
R/WB
I
55
E DB0 ~ DB3
I I/O
56 57 ~ 60
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OLED Driver/Controller IC
Preliminary
PT6880
pins are not used during a 4-bit operation. High Order Bidirectional Data I/O Pins These pins are used for data transfer and reception between the MPU and PT6880. D7 can be used as a Busy Flag. Common Driver Output Pins (see Note 1) No Connection
DB4 ~ DB7
I/O
61 ~ 64
COM1 ~ COM8 COM9 ~ COM16 NC
O -
66 ~ 73 80 ~ 87 2, 4, 24 ~ 29, 52, 54, 74 ~ 79, 100
Note: 1. COM1 to COM16 are used as the Common Output Driver Pins. However, when the pins are not in used, the respective common signals are transformed into non-selection waveforms. For example, under a 1/8 Duty Factors, the Common Driver Output Pins -- COM9 to COM16 are not used. Common Driver Output Pins -- COM12 to COM16 are not used during a 1/11 duty factor. Therefore, the common signals represented by aforementioned Unused Common Driver Output Pins are transformed into non-selection waveforms.
PT6880 pre 1.1
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OLED Driver/Controller IC Functional Description
Registers
Preliminary
PT6880
PT6880 provides two types of 8-bit registers, namely: Instruction Register (IR) and Data Register (DR). The register is selected using the RS Pin. When the RS pin is set to "0", the Instruction Register Type is selected. When RS pin is set to "1", the Data Register Type is selected. Please refer to the table below. RS 0 0 1 1 R/WB 0 1 0 1 Operation Instruction Register Write as an Internal Operation. Read Busy Flag (DB7) and Address Counter (DB0 to DB6) Data Register Write as an Internal Operation (DR to DDRAM or CGRAM) Data Register Read as an Internal Operation (DDRAM or CGRAM to DR)
INSTRUCTION REGISTER (IR) The Instruction Register is used to store the instruction code (i.e. Display Clear, Cursor Home and others), Display Data RAM (DDRAM) Address, and the Character Generator RAM (CGRAM) Address. Instruction register can only be written from the MPU. DATA REGISTER (DR) The Data Register is used as a temporary storage for data that are going to be written into the DDRAM or CGRAM as well as those data that are going to be read from the DDRAM or CGRAM.
BUSY FLAG (BF)
The Busy Flag is used to determine whether PT6880 is idle or internally operating. When PT6880 is performing some internal operations, the Busy Flag is set to "1". Under this condition, the no other instruction will not be accepted. When RS Pin is set to "0" and R/WB Pin is set to "1", the Busy Flag will be outputted to the DB7 pin. When PT6880 is idle or has completed its previous internal operation, the Busy Flag is set to "0". The next instruction can now be processed or executed.
PT6880 pre 1.1
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OLED Driver/Controller IC
ADDRESS COUNTER (AC)
Preliminary
PT6880
The address counter is used to assign the Display Data RAM (DDRAM) Address and the Character Generator RAM (CGRAM) Address. When an Address information is written into the Instruction Register (IR), this Address information is sent from the Instruction Register to the Address Counter. At the same time, the nature of the Address (either CGRAM or DDRAM) is determined by the instruction. After writing into or reading from the DDRAM or CGRAM, the Address Counter is automatically increased or decreased by 1 (for Write or Read Function). It must be noted that when the RS pin is set to "0" and R/WB is set to "1", the contents of the Address Counter are outputted to the pins -- DB0 to DB6.
DISPLAY DATA RAM (DDRAM)
The Display Data RAM (DDRAM) is used to store the Display Data which is represented as 8-bit character code. The Display Data RAM supports an extended capacity of 80 x 8-bits or 80 characters. The area in the DDRAM which are not used for display can be used as General Data RAM. For more details, please refer to the sections below. The Display Data RAM Address (ADD) is set in the Address Counter as a hexadecimal. High Order Bits Address Counter (hexadecimal ) Low Order Bits AC1 AC0
AC6 AC5 AC4 AC3 AC2
An example of a DDRAM Address = 4E is given below. DDRAM Address: 4E AC6 AC5 AC4 AC3 AC2 AC1 AC0 1 0 0 1 1 1 0
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OLED Driver/Controller IC
1-LINE DISPLAY (N=0)
Preliminary
PT6880
When the number of characters displayed is less than 80, the first character is displayed at the head position. The relationship between the DDRAM Address and position on the OLED Panel is shown below. Display Position (digit) DDRAM Address (hexadecimal) 1 00 2 01 3 02 4 03 …………. …………. 78 4D 79 4E 80 4F
For example, when only 8 characters are displayed in one Display Line, the relationship between the DDRAM Address and position on the OLED Panel is shown below. Display Position DDRAM Address Shift Left Shift Right 1 00 01 4F 2 01 02 00 3 02 03 01 4 03 04 02 5 04 05 03 6 05 06 04 7 06 07 05 8 07 08 06
2-LINE DISPLAY (N=1) Case 1: The Number of Characters displayed is less than 40 x 2 lines When the number of characters displayed is less than 40 x 2 lines, then the first character of the first and second lines are displayed starting from the head. It is important to note that the first line end address and the second line start address are not consecutive. Please refer the figure below. Display Position DDRAM Address (hexadecimal) 1 00 40 2 01 41 3 02 42 4 03 43 ………. ………. ………. 37 24 64 38 25 65 39 26 66 40 27 67
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OLED Driver/Controller IC
Preliminary
PT6880
To illustrate, for 2-line x 8 characters display, the relationship between the DDRAM address and position of the OLED panel is shown below. Display Position DDRAM Address 1 00 40 01 41 27 67 2 01 41 02 42 00 40 3 02 42 03 43 01 41 4 03 43 04 44 02 42 5 04 44 05 45 03 43 6 05 45 06 46 04 44 7 06 46 07 47 05 45 8 07 47 08 48 06 46
Shift Left
Shift Right
Case 2: 16-Character x 2 Lines Display PT6880 can be extended to display 16 characters x 2 lines by using the 40-output extension driver. When there is a Display Shift operation, the DDRAM Address is also shifted. Please refer to the example below. Display Position DDRAM Address Shift Left Shift Right 1 00 40 01 41 27 67 2 01 41 02 42 00 40 3 4 5 6 02 03 04 05 42 43 44 45 PT6880 Display 03 43 01 41 04 44 02 42 05 45 03 43 06 46 04 44 7 06 46 07 47 05 45 8 07 47 08 48 06 46 9 08 48 09 49 07 47 10 11 12 13 14 15 09 0A 0B 0C 0D 0E 49 4A 4B 4C 4D 4E Extension Driver Display 0A 0B 4A 4B 08 48 09 49 0C 0D 4C 4D 0A 0B 4A 4B 0E 4E 0F 4F 16 0F 4F 10 50 0E 4E
0C 0D 4C 4D
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OLED Driver/Controller IC
Character Generator ROM (CGROM)
Preliminary
PT6880
The Character Generator ROM (CGROM) is used to generate either 5 x 8 dots or 5 x 10 dots character patterns from 8-bit character codes. It can generate up to two hundred eight (208) 5 x 8 dot character patterns and thirty two (32) 5 x 10 dot character patterns. For user-defined character patterns, please contact PTC. CORRESPONDENCE BETWEEN THE CHARACTER CODES AND THE CHARACTER PATTERNS
UPPER BITS LOW ER BITS
0000
000
001
001
010
010
011
011
100
100
101
101
110
110
111
111
0000
CG RAM 1
0001
CG RAM 2
0010
CG RAM 3
0011
CG RAM 4
0100
CG RAM 5
0101
CG RAM 6
0110
CG RAM 7
0111
CG RAM 8
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1
1 1 1 1 1
1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1
1
1
1
1000
CG RAM 1
1 1
1 1 1 1 1 1 1 1 1
1
1
1 1 1 1 1 1
1
1001
CG RAM 2
1 1 1
1
1
1
1
1
1 1 1 1 1 1 1
1
1 1 1 1 1 1 1 1
1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1
1
1 1 1 1 1
1
1 1 1 1 1 1 1
1
1
1
1
1
1 1 1 1 1
1 1 1 1 1 1
1 1 1 1
1
1 1 1
1 1 1 1 1 1 1
1 1 1 1 1 1 1
1
1
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1
1010
CG RAM 3
1 1
1 1 1 1 1 1
1
1
1
1
1 1
1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1
1
1
1
1
1
1
1
1
1
1
1
1011
CG RAM 4
1
1
1 1 1 1 1
1
1
1 1 1 1
1 1 1 1
1 1 1 1 1 1 1
1 1 1 1 1 1 1
1 1 1 1 1 1 1
1
1
1
1
1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1
1
1 1 1 1 1
1
1 1
1 1 1 1 1 1
1
1
1
1
1
1
1
1
1 1 1 1 1 1
1
1
1
1
1
1
1 1 1 1 1 1
1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1
1 1
1100
CG RAM 5
1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1
1
1
1 1 1 1 1 1 1
1
1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1
1
1
1
1 1 1 1
1 1 1
1
1
1
1 1 1 1
1 1 1 1
1 1 1 1
1
1 1 1 1 1 1
1 1 1
1 1 1 1 1
1 1
1 1 1
1 1
1 1 1 1 1
1101
1
1 1
1 1
1 1
1 1
CG RAM 6
1
1
1
1
1 1
1 1 1 1 1 1 1
1 1 1 1
1
1 1 1 1 1 1 1
1
1
1
1
1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1
1 1
1110
1
CG RAM 7
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1
1 1 1
1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1
1
1 1
1 1
1
1
1 1 1 1 1
1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1
1
1 1
1 1 1 1 1 1
1
x
1 1 1
1
1 1 1 1 1 1 1 1 1
1
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1
1 1
1 1 1 1 1 1
1 1 1
1 1 1 1 1
1111
CG RAM 8
1 1 1 1 1 1
1 1
1 1
1
1
1
1
1
1
1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1
PT6880 pre 1.1
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OLED Driver/Controller IC
Preliminary
PT6880
6.
bits 0 to 4 is set to "1", the corresponding display location will light up regardless of the cursor position. When the Character Code Bits 4 to 7 are set to "0", then the CGRAM Character Pattern is selected. It must be noted that Character Code Bit 3 is not relevant and will not have any effect on the character display. Because of this, the first Character Pattern shown above ( R ) can be displayed when the Character Code is 00H or 08H.
RELATIONSHIP BETWEEN CGRAM ADDRESS, DDRAM CHARACTER CODE AND CGRAM CHARACTER PATTERNS (FOR 5 X10 DOT CHARACTER PATTERN)
Character Codes (DDRAM Data) 7 6 5 4 3 2 1 0 High Low 5 4 High CGRAM Address 3 2 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 1 0 0 1 1 0 Low 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 Character Patterns (CGRAM Data) 7 6 5 4 3 2 1 0 High Low * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 0 0 1 1 1 1 1 1 1 1 0 * * * * * * * * * * * * * * 0 0 0 1 0 0 1 0 0 0 0 * * * * * * * * * * * * * * 0 0 1 0 0 0 1 0 0 0 0 * * * * * * * * * * * * * * 0 0 1 0 0 0 1 0 0 0 0 * * * * * * * * * * * * * * 0 0 0 1 1 1 0 0 0 0 0 * * * * * * * * * * * * * *
0
0
0
0
*
0
0
*
0
0
Character Pattern
Cursor Position
0
0
0
0
*
1
1
*
1
1
Notes:
1. 2. 3. 4. 5.
* = Not Relevant The character pattern row positions correspond to the CGRAM data bits -- 0 to 4, where bit 4 is in the left position. Character Code Bits 1 and 2 correspond to the CGRAM Address Bits -- 4 and 5 respectively (2 bits : 4 types) If the CGRAM Data is set to "1", then the selection is displayed. If the CGRAM is set to "0", there no selection is made. The CGRAM Address Bits 0 to 3 are used to define the character pattern line position. The 11th line is the cursor position and its display is formed by the logical OR with the cursor.
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OLED Driver/Controller IC
Preliminary
PT6880
6.
The 11th line CGRAM data bits 0 to 4 must be set to "0". If any of the 11th line CGRAM data bits 0 to 4 is set to "1", the corresponding display location will light up regardless of the cursor position. When the Character Code Bits 4 to 7 are set to "0", then the CGRAM Character Pattern is selected. It must be noted that Character Code Bit -- 0 and 3 are not relevant and will not have any effect on the character display. Because of this, the Character Pattern shown above ( P ) can be displayed when the Character Code is 00H, 01H, 08H or 09H.
Timing Generation Circuit
The timing signals for the internal circuit operations (i.e. DDRAM, CGRAM, and CGROM) are generated by the Timing Generation Circuit. The timing signals for the MPU internal operation and the RAM Read for Display are generated separately in order to prevent one from interfering with the other. This means that, for example, when the data is being written into the DDRAM, there will be no unwanted interference such as flickering in areas other than the display area.
OLED Driver Circuit
PT6880 provides 16 Common Drivers and 40 Segment Driver Outputs. When a character font and the number of lines to be displayed have been selected, the corresponding Common Drivers output the drive waveform automatically. A non-selection waveform will be outputted by the rest of the Common Drivers. Serial data transmission always begins with the display data character pattern corresponding to the last Display Data RAM (DDRAM) Address. The serial data is latched when the display data character pattern corresponding to the starting address enters the internal shift register. Thus, PT6880 drives from the head display.
Cursor / Blink Control Circuit
The cursor or character blinking is generated by the Cursor / Blink Control Circuit.The cursor or the blinking will appear with the digit located at the Display Data RAM (DDRAM) Address Set in the Address Counter (AC). Address Counter AC6 0 AC5 0 AC4 0 AC3 1 AC2 0 AC1 0 AC0 0
CASE 1: FOR 1-LINE DISPLAY Example: When the Address Counter (AC) is set to 08H, the cursor position is displayed at DDRAM
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OLED Driver/Controller IC
Address 08H. Display Position DDRAM Address (hexadecimal) 1 00 2 01 3 02 4 03 5 04
Preliminary
PT6880
6 05
7 06
8 07
9 08
10 09
11 0A
| Cursor Position Note: The cursor or blinking appears when the Address Counter (AC) selects the Character Generator RAM (CGRAM). When the AC selects CGRAM Address, then the cursor or the blinking is displayed in a irrelevant and meaningless position.
CASE 2: FOR 2-LINE DISPLAY Example: When the Address Counter (AC) is set to 08H, the cursor position is displayed at DDRAM Address 08H. Display Position DDRAM Address (hexadecimal) 1 00 40 2 01 41 3 02 42 4 03 43 5 04 44 6 05 45 7 06 46 8 07 47 9 08 48 10 09 49 11 0A 4A
Cursor Position Note: The cursor or blinking appears when the Address Counter (AC) selects the Character Generator RAM (CGRAM). When the AC selects CGRAM Address, then the cursor or the blinking is displayed in a irrelevant and meaningless position.
Reset Function
INTERNAL RESET CIRCUIT INITIALIZATION When power is turned ON, PT6880 is initialized automatically by an internal reset circuit. The following instructions are executed during the initialization. 1. Display Clear 2. Function Set:
DL = "1" : 8-Bit Interface Data N = "0" : 1-Line Display F = "0": 5 x 8 Dot Character Font 3. Display ON/OFF Control: D = "0" : Display OFF
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OLED Driver/Controller IC
Preliminary
PT6880
4. Entry Mode Set:
C = "0" : Cursor OFF B = "0" : Blinking OFF I/D = "1" : Increment by 1 S = "0" : No Shift
The Busy Flag (BF) is in a busy state until the initialization is completed (BF="1"). The busy state will be in effect 10 ms after the VDD rises to 4.5 Volts. Please note that in order for the initialization by internal reset circuit to be successful, the electrical characteristic conditions listed in the Electrical Characteristics Section must be complied with. Otherwise, such initialization must be performed by instruction from the MPU.
Instructions
PT6880's Instruction Register (IR) and Data Register (DR) are the only registers that can be controlled by the MPU. Prior to the commencement of it internal operation, PT6880 temporarily stores the control information to its Instruction Register (IR) and Data Register (DR) in order to easily facilitate interface with various types of MPU. The internal operation of the PT6880 are determined by the signals (RS, R/WB, DB0 to DB7) that are sent from the MPU. These signals are categorized into 4 instructions types, namely: 1. 2. 3. 4. Function Setting Instructions (i.e. Display, Format, Data Length etc.) Internal RAM Address Setting Instructions Data Transfer with Internal RAM Instructions Miscellaneous Function Instructions
The generally used instructions are those that execute data transfers with the internal RAM. However, when the internal RAM addresses are auto incremented/decremented by 1 after each Data Write, the program load of the MPU is lightened. The Display Shift Instruction can be executed at the same time as the Display Data Write, thereby minimizing system development time with maximum programming efficiency. When an instruction is being executed for an internal operation, only the Busy Flag/Address Read Instruction can be performed. The other instructions are not valid. It should be noted that during the execution of an instruction, the Busy Flag is set to "1". The Busy Flag is set to "0" when the instructions are can be accepted and executed. Therefore, the Busy Flag should be checked to make certain that BF = "0" before sending another instruction from the MPU. If not, the time between the first instruction and the next instruction is longer than the time it takes to execute the instruction itself.
Instruction Code Description Max. Execution Time when
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OLED Driver/Controller IC
R S Clear Display 0 R/WB 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0
Preliminary
DB2 0 DB1 0 DB0 1
PT6880
fsp or fosc = 250kHz Clears entire display. Sets DDRAM Address 0 into the Address Counter Sets DDRAM Address 0 into the Address Counter. Returns shifted display to original position. DDRAM contents remain unchanged. Sets cursor move direction and specifies display shift. (These operations are performed during data write and read.) Sets entire Display (D) ON/OFF. Sets Cursor (C) ON/OFF. Sets Blinking(B) of Cursor Position Character. Moves cursor & shifts display without changing DDRAM contents. Sets interface data length (DL). Sets number of display lines (N). Sets Character Font (F). Sets CGRAM Address. CGRAM data is sent and received after this setting. Sets DDRAM Address. The DDRAM data Is sent and received after this setting. Reads Busy Flag (BF) indicating that internal operation is being performed. Reads Address Counter contents. Writes data into the CGRAM or DDRAM Read data from the CGRAM or DDRAM 1.52ms
Return Home
0
0
0
0
0
0
0
0
1
x
Entry Mode Set
0
0
0
0
0
0
0
1
I/D
S
37us
Display ON/OFF Control
0
0
0
0
0
0
1
D
C
B
37us
Cursor/ Display Shift Function Set Set CGRAM Address Set DDRAM Address Read Busy Flag & Address Write data into the CGRAM or DDRAM Read Data from the CGRAM
0
0
0
0
0
1
S/C
R/L
x
x
37us
0
0
0
0
1
DL
N
F
x
x
37us
0
0
0
1
ACG
ACG
ACG
ACG
ACG
ACG
37us
0
0
1
ADD
ADD
ADD
ADD
ADD
ADD
ADD
37us
0
1
BF
AC
AC
AC
AC
AC
AC
AC
0us
1
0
Write Data
37us tADD=4us* 37us tADD=4us*
1
1
Read Data
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OLED Driver/Controller IC
or DDRAM
Preliminary
PT6880
Notes:
1. 2.
x = Not Relevant * = After the CGRAM/DDRAM Read or Write Instruction has been executed, the RAM Address Counter is incremented or decremented by 1. After the Busy Flag is turned OFF, the RAM Address is updated. I/D = Increment / Decrement Bit I/D = "1" : Increment I/D = "0" : Decrement S = Shift Entire Display Control Bit BF = Busy Flag BF = "1" : Internal Operating in Progress BF ="0" : No Internal Operation is being executed, next instruction can be accepted. R/L = Shift Right / Left R/L = "1" : Shift to the Right R/L = "0" : Shift to the Left S/C = Display Shift / Cursor Move S/C = "1" : Display Shift S/C = "0" : Cursor Move DDRAM = Display Data RAM CGRAM = Character Generator RAM ACG =CGRAM Address ADD = Address Counter Address (corresponds to cursor address) AC = Address Counter (used for DDRAM and CGRAM Addresses) F = Character Pattern Mode F = "1" : 5 x 10 dots F = "0" : 5 x 8 dots N = Number of Lines Displayed N = "1" : 2 -Line Display N = "0" : 1-Line Display * = The time it takes to execute an instruction changes when the frequency changes. To illustrate an example: When fcp of fosc = 250 kHz, then
3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15.
the execution time = 37us x 270/250 = 40us 16. tADD is the time period starting when the Busy Flag is turned OFF up to the time the Address Counter is updated. Please refer to the diagram below.
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OLED Driver/Controller IC
BUSY SIGNAL (DB7)
Preliminary
PT6880
BUSY STATE
ADDRESS COUNTER (DB0 TO DB6)
A
A+1
tADD
where
1. tADD depends on the operation frequency and may be calculated using the following equation tADD = 1.5 / (fcp) seconds or tADD = 1.5 /(fosc) seconds
INSTRUCTION DESCRIPTION Clear Display Instruction RS R/WB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 1 This instruction is used to clear the Display Write Space 20H in all DDRAM Addresses. That is, the character pattern for the Character Code 20H must be a BLANK pattern. It then sets the DDRAM Address 0 into the Address Counter and reverts the display to its original state (if the display has been shifted). The display will be cleared and the cursor or blinking will go to the left edge of the display. If there are 2 lines displayed, the cursor or blinking will go to the first line 's left edge of the display. Under the Entry Mode, this instruction also sets the I/D to 1 (Increment Mode). The S Bit of the Entry Mode does not change. Return Home Instruction RS R/WB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 1 * Note: * = Not Relevant This instruction is used to set the DDRAM Address 0 into the Address Counter and revert the display to its original status (if the display has been shifted). The DDRAM contents do not change. The cursor or blinking will go to the left edge of the display. If there are 2 lines displayed, the cursor or blinking will go to the first line 's left edge of the display.
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Entry Mode Set Instruction
Preliminary
PT6880
The Entry Mode Set Instruction has two controlling bits: I/D and S. Please refer to the table below. RS R/WB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 1 I/D S I/D is the Increment / Decrement Bit. When I/D is set to "1". the DDRAM Address is incremented by "1" when a character code is written into or read from the DDRAM. An increment of 1 will move the cursor or blinking one step to the right. When the I/D is set to "0", the DDRAM is decremented by 1 when a character code is written into or read from the DDRAM. An decrement of 1 will move the cursor or blinking one step to the left. S : Shift Entire Display Control Bit This bit is used to shift the entire display. When S is set to "1", the entire display is shifted to the right (when I/D ="0") or left (when I/D ="1"). The display does not shift when reading from the DDRAM, writing into or reading from the CGRAM. When S is set to "0", the display is not shifted. Display ON / OFF Control Instruction The Display On / OFF Instruction is used to turn the display ON or OFF. The controlling bits are D, C and B. RS R/WB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 D C B D : Display ON /OFF Bit When D is set to "1", the display is turned ON. When D is set to "0", the display is turned OFF and the display data is stored in the DDRAM. The display data can be instantly displayed by setting D to "1". C : Cursor Display Control Bit When C is set to "1", the cursor is displayed. In a 5 x 8 dot character font, the cursor is displayed via the 5 dots in the 8th line. In a 5 x 10 dot character font , it is displayed via 5 dots in the 11th line. When C is set to "0", the cursor display is disabled.
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