STM32F051数据手册_英文
February 2012Doc ID 018746 Rev 21/1
STM32F051x4 STM32F051x6
STM32F051x8
Low- and medium-density advanced ARM?-based 32-bit MCU with
16 to 64 Kbytes Flash, timers, ADC, DAC and comm. interfaces
Features
■Operating conditions:
–Voltage range: 2.0V to 3.6V
■ARM 32-bit Cortex?-M0 CPU (48 MHz max)■
Memories
–16 to 64 Kbytes of Flash memory
–8 Kbytes of SRAM with HW parity checking ■CRC calculation unit
■
Clock management
– 4 to 32 MHz crystal oscillator
–32 kHz oscillator for RTC with calibration –Internal 8 MHz RC with x6 PLL option –Internal 40 kHz RC oscillator
■Calendar RTC with alarm and periodic wakeup from Stop/Standby
■
Reset and supply management
–Power-on/Power down reset (POR/PDR)–Programmable voltage detector (PVD)■Low power Sleep, Stop, and Standby modes ■V BAT supply for RTC and backup registers ■5-channel DMA controller
■
1 × 12-bit, 1.0 μs ADC (up to 16 channels)–Conversion range: 0 to 3.6V
–Separate analog supply from 2.4 up to 3.6■Two fast low-power analog comparators with programmable input and output ■One 12-bit D/A converter
■
Up to 55 fast I/Os
–All mappable on external interrupt vectors –Up to 36 I/Os with 5 V tolerant capability ■
Up to 18 capacitive sensing channels
supporting touchkey, linear and rotary touch sensors ■96-bit unique ID ■
Serial wire debug (SWD)
■
Up to 11 timers
–One 16-bit 7-channel advanced-control timer for 6 channels PWM output, with deadtime generation and emergency stop –One 32-bit and one 16-bit timer, with up to 4 IC/OC, usable for IR control decoding –One 16-bit timer, with 2 IC/OC, 1 OCN, deadtime generation and emergency stop –Two 16-bit timers, each with IC/OC and OCN, deadtime generation, emergency stop and modulator gate for IR control –One 16-bit timer with 1 IC/OC
–Independent and system watchdog timers –SysTick timer: 24-bit downcounter
–One 16-bit basic timer to drive the DAC ■Communication interfaces
–Up to two I 2C interfaces; one supporting Fast Mode Plus (1 Mbit/s) with 20 mA current sink, SMBus/PMBus, and wakeup from STOP
–Up to two USARTs supporting master synchronous SPI and modem control; one with ISO7816 interface, LIN, IrDA
capability, auto baud rate detection and wakeup feature
–Up to two SPIs (18 Mbit/s) with 4 to 16 programmable bit frame, 1 with I 2S interface multiplexed
–HDMI CEC interface, wakeup on header reception
Table 1.
Device summary
Reference
Part number
STM32F051x4STM32F051K4, STM32F051C4, STM32F051R4STM32F051x6STM32F051K6, STM32F051C6, STM32F051R6STM32F051x8
STM32F051C8, STM32F051R8, STM32F051K8
https://www.sodocs.net/doc/b39474797.html,
Contents STM32F051x
Contents
1Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1ARM? CortexTM-M0 core with embedded Flash and SRAM . . . . . . . . . 10
3.2Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.3Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 10
3.4Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.5Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 11
3.6Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . 11
3.7Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.8Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.9Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.9.1Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.9.2Power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.9.3Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.10Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.11Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 14
3.12Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.12.1Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.12.2General-purpose timers (TIM2..3, TIM1
4..17) . . . . . . . . . . . . . . . . . . . . 16
3.12.3Basic timer TIM6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.12.4Independent window watchdog (IWWDG) . . . . . . . . . . . . . . . . . . . . . . . 17
3.12.5System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.12.6SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.13Inter-integrated circuit interfaces (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.14Universal synchronous/asynchronous receiver transmitters (USART) . . . 18
3.15Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I2S) . 19
3.16High-definition multimedia interface (HDMI) - consumer electronics control
(CEC) 20
3.17General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.18Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2/3Doc ID 018746 Rev 2
STM32F051x Contents
3.19Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.19.1Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.19.2V BAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.20Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.21Fast low power comparators and reference voltage . . . . . . . . . . . . . . . . . 22
3.21.1Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.1Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
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List of tables STM32F051x List of tables
Table 1.Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2.STM32F051xx family device features and peripheral counts. . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3.Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table https://www.sodocs.net/doc/b39474797.html,parison of I2C analog and digital filters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 5.STM32F051xx I2C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 6.STM32F051xx USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 7.STM32F051x SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 8.Capacitive sensing GPIOs available on STM32F051x devices . . . . . . . . . . . . . . . . . . . . . 20 Table 9.No. of capacitive sensing channels available on STM32F051xx devices. . . . . . . . . . . . . . 21 Table 10.Legend/abbreviations used in the pinout table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 11.Pin definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 12.Alternate functions selected through GPIOA_AFR registers for port A . . . . . . . . . . . . . . . 29 Table 13.Alternate functions selected through GPIOB_AFR registers for port B . . . . . . . . . . . . . . . 30 Table 14.STM32F051x peripheral register boundary addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 15.LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data. . . . . . . . . . 35 Table 16.LQFP48 – 7 x 7mm, 48-pin low-profile quad flat package mechanical data. . . . . . . . . . . . 36 Table 17.UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package (5x5),
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 18.Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4/4Doc ID 018746 Rev 2
STM32F051x List of figures List of figures
Figure 1.Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 2.Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 3.LQFP64 64-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 4.LQFP48 48-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 5.UFQFPN32 32-pin package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 6.STM32F051x memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 7.LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 35 Figure 8.Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 9.LQFP48 – 7 x 7mm, 48-pin low-profile quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 10.Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 11.UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package outline (5x5). . . . . . 37 Figure 12.UFQFPN32 recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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Description STM32F051x 1 Description
The STM32F051xx family incorporates the high-performance ARM Cortex?-M0 32-bit
RISC core operating at a 48 MHz frequency, high-speed embedded memories (Flash
memory up to 64 Kbytes and SRAM up to 8 Kbytes), and an extensive range of enhanced
peripherals and I/Os. All devices offer standard communication interfaces (up to two I2Cs,
two SPIs, one I2S, one HDMI CEC, and up to two USARTs), one 12-bit ADC, one 12-bit
DAC, up to five general-purpose 16-bit timers, a 32-bit timer and an advanced-control PWM
timer.
The STM32F051xx family operates in the -40 to +85 °C and -40 to +105 °C temperature
ranges, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving modes
allows the design of low-power applications.
The STM32F051xx family includes devices in three different packages ranging from 32 pins
to 64 pins. Depending on the device chosen, different sets of peripherals are included. The
description below provides an overview of the complete range of peripherals proposed in
this family.
These features make the STM32F051xx microcontroller family suitable for a wide range of
applications such as application control and user interfaces, handheld equipment, A/V
receivers and digital TV, PC peripherals, gaming and GPS platforms, industrial applications,
PLCs, inverters, printers, scanners, alarm systems, video intercoms, and HVACs.
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STM32F051x Description
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Table 2.
STM32F051xx family device features and peripheral counts
Peripheral STM32F051Kx STM32F051Cx
STM32F051Rx
Flash (Kbytes)16
32
6416
32
6416
32
64SRAM (Kbytes)
4
8
48
4
8
Timers
Advanced control
1 (16-bit)General purpose 5 (16-bit)1 (32-bit) Basic 1 (16-bit)
Comm. interfaces
SPI (I2S)(1)
1(1)(2)2(1)1(1)(2)2(1)1(1)(2)2(1)I 2C 1(3)2
1(3)
2
1(3)
2USART 1(4)
2
1(4)
2
1(4)
2
CEC
1
12-bit synchronized ADC
(number of channels)1
(10 ext. + 3 int.)
1
(16 ext. + 3 int.)
GPIOs
273955Capacitive sensing channels
14
1718
12-bit DAC
(number of channels)1(1)Analog comparator 2Max. CPU frequency 48 MHz Operating voltage
2.0 to
3.6 V Operating temperature Ambient operating temperature: -40 °C to 85 °C / -40 °C to 105 °C
Junction temperature: -40 °C to 125 °C Packages
UFQFPN32
LQFP48
LQFP64
1.The SPI1 interface can be used either in SPI mode or in I2S audio mode.
2.SPI2 is not present
3.I2C2 is not present
https://www.sodocs.net/doc/b39474797.html,ART2 is not present
Device overview STM32F051x
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2 Device overview
STM32F051x Device overview
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Functional overview STM32F051x
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3 Functional overview
3.1 ARM ? Cortex TM -M0 core with embedded Flash and SRAM
The ARM Cortex?-M0 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.The ARM Cortex?-M0 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices.
The STM32F051xx family has an embedded ARM core and is therefore compatible with all ARM tools and software.Figure 1 shows the general block diagram of the device family.
3.2 Memories
The device has the following features:
●
Up to 8 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0
wait states and featuring embedded parity checking with exception generation for fail-critical applications.
●
The non-volatile memory is divided into two arrays:–16 to 64 Kbytes of embedded Flash memory for programs and data –
Option bytes
The option bytes are used to write-protect the memory (with 4 KB granularity) and/or readout-protect the whole memory with the following options:–Level 0: no readout protection
–Level 1: memory readout protection, the Flash memory cannot be read from or written to if either debug features are connected or boot in RAM is selected –
Level 2: chip readout protection, debug features (Cortex-M0 serial wire) and boot in RAM selection disabled
3.3 Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 96-bit data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location.
STM32F051x Functional overview
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3.4 Direct memory access controller (DMA)
The 5-channel general-purpose DMAs manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers.
The DMA supports circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent.
DMA can be used with the main peripherals: SPI, I2S, I2C, USART, all TIMx timers (except TIM14), DAC and ADC.
3.5 Nested vectored interrupt controller (NVIC)
The STM32F051xx family embeds a nested vectored interrupt controller able to handle up to 32 maskable interrupt channels (not including the 16 interrupt lines of Cortex?-M0) and 16 priority levels.
●Closely coupled NVIC gives low latency interrupt processing ●Interrupt entry vector table address passed directly to the core ●Closely coupled NVIC core interface ●Allows early processing of interrupts
●Processing of late arriving higher priority interrupts ●Support for tail-chaining
●Processor state automatically saved
●
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt latency.
3.6 Extended interrupt/event controller (EXTI)
The external interrupt/event controller consists of 24 edge detector lines used to generate
interrupt/event requests and wake-up the system. Each line can be independently
configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the internal clock period. Up to 55 GPIOs can be connected to the 16 external interrupt lines.
Functional overview STM32F051x
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3.7 Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example on failure of an indirectly used external crystal, resonator or oscillator).
Several prescalers allow the application to configure the frequency of the AHB and the APB domains. The maximum frequency of the AHB and the APB domains is 48 MHz.
3.8 Boot modes
At startup, the boot pin and boot selector option bit are used to select one of three boot
options:
●Boot from User Flash ●Boot from System Memory ●
Boot from embedded SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART1.
3.9 Power management
3.9.1
Power supply schemes
●V DD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.
Provided externally through V DD pins.
●
V DDA = 2.0 to 3.6 V: external analog power supply for ADC, Reset blocks, RCs and PLL (minimum voltage to be applied to V DDA is 2.4 V when the ADC and DAC are used). The V DDA voltage level must be always greater or equal to the V DD voltage level and must be provided first.
●
V BAT = 1.6 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when V DD is not present.
For more details on how to connect power pins, refer to Figure 9: Power supply scheme .
3.9.2 Power supply supervisors
The device has integrated power-on reset (POR) and power-down reset (PDR) circuits. They are always active, and ensure proper operation above a threshold of 2 V . The device remains in reset mode when the monitored supply voltage is below a specified threshold, V POR/PDR , without the need for an external reset circuit.
●The POR monitors only the V DD supply voltage. During the startup phase it is required that V DDA should arrive first and be greater than or equal to V DD .
●
The PDR monitors both the V DD and V DDA supply voltages, however the V DDA power supply supervisor can be disabled (by programming a dedicated Option bit) to reduce the power consumption if the application design ensures that V DDA is higher than or equal to V DD .
STM32F051x Functional overview
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The device features an embedded programmable voltage detector (PVD) that monitors the V DD power supply and compares it to the V PVD threshold. An interrupt can be generated when V DD drops below the V PVD threshold and/or when V DD is higher than the V PVD
threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
3.9.3 Voltage regulator
The regulator has three operating modes: main (MR), low power (LPR) and power down.
●MR is used in normal operating mode (Run)
●LPR can be used in Stop mode where the power demand is reduced
●
Power down is used in Standby mode: the regulator output is in high impedance: the
kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost)
This regulator is always enabled after reset. It is disabled in Standby mode, providing high impedance output.
3.10 L
ow-power modes
The STM32F051xx family supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:
●
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.
●
Stop mode
Stop mode achieves very low power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low power mode.
The device can be woken up from Stop mode by any of the EXTI lines. The EXTI line source can be one of the 16 external lines, the PVD output, RTC alarm, COMPx, I2C1, USART1 or the CEC.
The I2C1, USART1 and the CEC can be configured to enable the HSI RC oscillator for processing incoming data. If this is used, the voltage regulator should not be put in the low-power mode but kept in normal mode.
●
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a rising edge on the WKUP pins, or an RTC alarm occurs.
Note:
The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode.
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3.11 Real-time clock (RTC) and backup registers
The RTC and the 5 backup registers are supplied through a switch that takes power either on V DD supply when present or through the V BAT pin. The backup registers are five 32-bit registers used to store 20 bytes of user application data when V DD power is not present. They are not reset by a system or power reset, or when the device wakes up from Standby mode.
The RTC is an independent BCD timer/counter. Its main features are the following:
●Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format.
●Automatically correction for 28, 29 (leap year), 30, and 31 day of the month.●Programmable alarm with wake up from Stop and Standby mode capability. ●On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock.
●Digital calibration circuit with 1ppm resolution, to compensate for quartz crystal inaccuracy.
● 2 anti-tamper detection pins with programmable filter. The MCU can be woken up from Stop and Standby modes on tamper event detection.
●
Timestamp feature which can be used to save the calendar content. This function can triggered by an event on the timestamp pin, or by a tamper event. The MCU can be woken up from Stop and Standby modes on timestamp event detection.The RTC clock sources can be:
● A 32.768 kHz external crystal ● A resonator or oscillator
●The internal low-power RC oscillator (typical frequency of 40 kHz) ●
The high-speed external clock divided by 32.
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3.12 Timers and watchdogs
The STM32F051xx family devices include up to six general-purpose timers, one basic timer and an advanced control timer.
Table 3 compares the features of the advanced-control, general-purpose and basic timers.
3.12.1 Advanced-control timer (TIM1)
The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable inserted dead times. It can also be seen as a complete general-purpose timer. The 4 independent channels can be used for:
●Input capture ●Output compare
●PWM generation (edge or center-aligned modes)●
One-pulse mode output
If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If configured as the 16-bit PWM generator, it has full modulation capability (0-100%). The counter can be frozen in debug mode.
Many features are shared with those of the standard timers which have the same
architecture. The advanced control timer can therefore work together with the other timers via the Timer Link feature for synchronization or event chaining.
Table 3.
Timer feature comparison
Timer type
Timer
Counter resolution Counter type Prescaler factor DMA request generation Capture/compare channels Complementary outputs
Advanced
control
TIM1
16-bit
Up, down, up/down Any integer between 1 and 65536Y es
4
Y es
General purpose
TIM2 32-bit Up, down, up/down Any integer between 1 and 65536Y es 4No
TIM316-bit Up, down, up/down
Any integer between 1 and 65536Y es 4No
TIM1416-bit Up Any integer between 1 and 65536No 1No
TIM1516-bit Up Any integer between 1 and 65536Y es 2Y es
TIM16, TIM17
16-bit Up Any integer between 1 and 65536Y es 1Y es
Basic TIM616-bit Up Any integer between 1 and 65536
Y es 0No
Functional overview STM32F051x
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3.12.2 General-purpose timers (TIM2..3, TIM1
4..17)
There are six synchronizable general-purpose timers embedded in the STM32F051xx
devices (see Table 3 for differences). Each general-purpose timer can be used to generate PWM outputs, or as simple time base.
TIM2, TIM3
STM32F051xx devices feature two synchronizable 4-channel general-purpose timers. TIM2 is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TIM3 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. They feature 4 independent channels each for input capture/output compare, PWM or one-pulse mode output. This gives up to 12 input captures/output compares/PWMs on the largest packages.
The TIM2 and TIM3 general-purpose timers can work together or with the TIM1 advanced-control timer via the Timer Link feature for synchronization or event chaining.TIM2 and TIM3 both have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors.Their counters can be frozen in debug mode.
TIM14
This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM14 features one single channel for input capture/output compare, PWM or one-pulse mode output.
Its counter can be frozen in debug mode.
TIM15, TIM16 and TIM17
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM15 has two independent channels, whereas TIM16 and TIM17 feature one single channel for input capture/output compare, PWM or one-pulse mode output.
The TIM15, TIM16 and TIM17 timers can work together, and TIM15 can also operate with TIM1 via the Timer Link feature for synchronization or event chaining.TIM15 can be synchronized with TIM16 and TIM17.
TIM15, TIM16, and TIM17 have a complementary output with dead-time generation and independent DMA request generation Their counters can be frozen in debug mode.
3.12.3 Basic timer TIM6
This timer is mainly used for DAC trigger generation. It can also be used as a generic 16-bit time base.
STM32F051x Functional overview
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3.12.4 Independent window watchdog (IWWDG)
The independent window watchdog is based on an 8-bit prescaler and 12-bit downcounter with user-defined refresh window. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby
modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.
3.12.5 System window watchdog (WWDG)
The system window watchdog is based on a 7-bit downcounter that can be set as free
running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the APB clock (PCLK). It has an early warning interrupt capability and the counter can be frozen in debug mode.
3.12.6 SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
● A 24-bit down counter ●Autoreload capability
●Maskable system interrupt generation when the counter reaches 0.●
Programmable clock source (HCLK or HCLK/8)
3.13 Inter-integrated circuit interfaces (I 2C)
Up to two I 2C interfaces (I2C1 and I2C2) can operate in multimaster or slave modes. Both
can support Standard mode (up to 100 kbit/s) or Fast mode (up to 400 kbit/s) and I2C1 supports also Fast Mode Plus (up to 1 Mbit/s) with 20 mA output drive.
Both support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2
addresses, 1 with configurable mask). They also include programmable analog and digital noise filters.
Table 4.
Comparison of I2C analog and digital filters
Analog filter
Digital filter
Pulse width of
suppressed spikes ≥ 50 ns
Programmable length from 1 to 15 I2C peripheral clocks Benefits
Available in Stop mode 1. Extra filtering capability vs. standard requirements.2. Stable length
Drawbacks
Variations depending on
temperature, voltage, process
Disabled when Wakeup from Stop mode is enabled
Functional overview STM32F051x
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In addition, I2C1 provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts
verifications and ALERT protocol management. I2C1 also has a clock domain independent from the CPU clock, allowing the I2C1 to wake up the MCU from Stop mode on address match.
The I2C interfaces can be served by the DMA controller.Refer to T able 5 for the differences between I2C1 and I2C2.
3.14
Universal synchronous/asynchronous receiver transmitters (USART)
The device embeds up to two universal synchronous/asynchronous receiver transmitters (USART1 and USART2), which communicate at speeds of up to 6 Mbit/s.
They provide hardware management of the CTS, RTS and RS485 DE signals,
multiprocessor communication mode, master synchronous communication and single-wire half-duplex communication mode. The USART1 supports also SmartCard communication (ISO 7816), IrDA SIR ENDEC, LIN Master/Slave capability, auto baud rate feature and has a clock domain independent from the CPU clock, allowing the USART1 to wake up the MCU from Stop mode.
The USART interfaces can be served by the DMA controller.Serial peripheral interface (SPI).
Refer to T able 6 for the differences between USART1 and USART2.
Table 5.
STM32F051xx I 2C implementation
I2C features (1)
1.X = supported.
I2C1I2C27-bit addressing mode X X 10-bit addressing mode X X Standard mode (up to 100 kbit/s)X X Fast mode (up to 400 kbit/s)
X X
Fast Mode Plus with 20mA output drive I/Os (up to 1 Mbit/s)X Independent clock X SMBus
X Wakeup from STOP
X
STM32F051x
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3.15
Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I 2S)
Up to two SPIs are able to communicate up to 18 Mbits/s in slave and master modes in full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits.
One standard I 2S interface (multiplexed with SPI1) supporting four different audio standards can operate as master or slave at simplex communication mode. It can be configured to transfer 16 and 24 or 32 bits with16-bit or 32-bit data resolution and synchronized by a specific signal. Audio sampling frequency from 8 kHz up to 192 kHz can be set by 8-bit programmable linear prescaler. When operating in master mode it can output a clock for an external audio component at 256 times the sampling frequency.Refer to T able 7 for the differences between SPI1 and SPI2.
Table 6.
STM32F051xx USART implementation
USART modes/features (1)
1.X = supported.
USART1
USART2
Hardware flow control for modem X X Continuous communication using DMA X X Multiprocessor communication X X Synchronous mode X X
Smartcard mode
X Single-wire half-duplex communication X X
IrDA SIR ENDEC block X LIN mode
X Dual clock domain and wakeup from Stop mode X Receiver timeout interrupt X Modbus communication X Auto baud rate detection X Driver Enable
X
X
Table 7.
STM32F051x SPI/I2S implementation
SPI features (1)
1.X = supported.
SPI1SPI2Hardware CRC calculation X X Rx/Tx FIFO X X NSS pulse mode X X
I2S mode X TI mode
X
X
Functional overview STM32F051x
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3.16 High-definition multimedia interface (HDMI) - consumer
electronics control (CEC)
The device embeds a HDMI-CEC controller that provides hardware support for the Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard).This protocol provides high-level control functions between all audiovisual products in an environment. It is specified to operate at low speeds with minimum processing and memory overhead. It has a clock domain independent from the CPU clock, allowing the HDMI_CEC controller to wakeup the MCU from Stop mode on data reception.
3.17 General-purpose inputs/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions.
The I/O configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.
3.18 Touch sensing controller (TSC)
The device has an embedded independent hardware controller (TSC) for controlling touch sensing acquisitions on the I/Os.
Up to 18 touch sensing electrodes can be controlled by the TSC. The touch sensing I/Os are organized in 6 acquisition groups, with up to 4 I/Os in each group.
Table 8.
Capacitive sensing GPIOs available on STM32F051x devices
Group
Capacitive sensing
signal name Pin name Group
Capacitive sensing
signal name
Pin name 1
TSC_G1_IO1
P A04TSC_G4_IO1P A9TSC_G1_IO2P A1TSC_G4_IO2P A10TSC_G1_IO3P A2TSC_G4_IO3P A11TSC_G1_IO4P A3TSC_G4_IO4P A122
TSC_G2_IO1
P A45TSC_G5_IO1PB3TSC_G2_IO2P A5TSC_G5_IO2PB4TSC_G2_IO3P A6TSC_G5_IO3PB6TSC_G2_IO4P A7TSC_G5_IO4PB73
TSC_G3_IO1
PB06TSC_G6_IO1PB11TSC_G3_IO2PB1TSC_G6_IO2PB12TSC_G3_IO3PB2TSC_G6_IO3PB13TSC_G3_IO4
PC5
TSC_G6_IO4
PB14