FPGA可编程逻辑器件芯片XC2VP4-6FF672C中文规格书
Table 35:Recommended Operating Conditions for User I/Os Using Single-Ended Standards
Signal Standard (IOSTANDARD)
V CCO V REF V IL V IH Min (V)Nom (V)Max (V)Min (V)Nom (V)Max (V)Max (V)Min (V)
GTL(3)–––0.740.80.86V REF – 0.05V REF + 0.05 GTL_DCI– 1.2–0.740.80.86V REF – 0.05V REF + 0.05 GTLP(3)–––0.881 1.12V REF – 0.1V REF + 0.1 GTLP_DCI– 1.5–0.881 1.12V REF – 0.1V REF + 0.1 HSLVDCI_15 1.4 1.5 1.6–0.75–V REF – 0.1V REF + 0.1 HSLVDCI_18 1.7 1.8 1.9–0.9–V REF – 0.1V REF + 0.1 HSLVDCI_25 2.3 2.5 2.7– 1.25–V REF – 0.1V REF + 0.1 HSLVDCI_33 3.0 3.3 3.465– 1.65–V REF – 0.1V REF + 0.1 HSTL_I, HSTL_I_DCI 1.4 1.5 1.60.680.750.9V REF – 0.1V REF + 0.1 HSTL_III,
HSTL_III_DCI 1.4 1.5 1.6
–0.9–V REF – 0.1V REF + 0.1
HSTL_I_18,
HSTL_I_DCI_18 1.7 1.8 1.90.80.9 1.1V REF – 0.1V REF + 0.1 HSTL_II_18,
HSTL_II_DCI_18 1.7 1.8 1.9
–0.9–V REF – 0.1V REF + 0.1
HSTL_III_18,
HSTL_III_DCI_18 1.7 1.8 1.9
– 1.1–V REF – 0.1V REF + 0.1 LVCMOS12 1.14 1.2 1.3–––0.37V CCO0.58V CCO LVCMOS15,
LVDCI_15,
LVDCI_DV2_15
1.4 1.5 1.6–––0.30V CCO0.70V CCO
LVCMOS18,
LVDCI_18,
LVDCI_DV2_18
1.7 1.8 1.9–––0.30V CCO0.70V CCO
LVCMOS25(4,5),
LVDCI_25,
LVDCI_DV2_25(4)
2.3 2.5 2.7–––0.7 1.7
LVCMOS33,
LVDCI_33,
LVDCI_DV2_33(4)
3.0 3.3 3.465–––0.8 2.0 LVTTL 3.0 3.3 3.465–––0.8 2.0
PCI33_3(7) 3.0 3.3 3.465–––0.30V CCO0.50V CCO SSTL18_I,
SSTL18_I_DCI 1.7 1.8 1.90.8330.9000.969V REF – 0.125V REF + 0.125 SSTL18_II 1.7 1.8 1.90.8330.9000.969V REF – 0.125V REF + 0.125 SSTL2_I,
SSTL2_I_DCI 2.3 2.5 2.7 1.15 1.25 1.35V REF – 0.15V REF + 0.15 SSTL2_II,
SSTL2_II_DCI 2.3 2.5 2.7 1.15 1.25 1.35V REF – 0.15V REF + 0.15 Notes:
1.Descriptions of the symbols used in this table are as follows:
V CCO – the supply voltage for output drivers as well as LVCMOS, LVTTL, and PCI inputs
V REF – the reference voltage for setting the input switching threshold
V IL – the input voltage that indicates a Low logic level
V IH – the input voltage that indicates a High logic level
2.For device operation, the maximum signal voltage (V IH max) may be as high as V IN max. See Table28.
3.Because the GTL and GTLP standards employ open-drain output buffers, V CCO lines do not supply current to the I/O circuit, rather this current is
provided using an external pull-up resistor connected from the I/O pin to a termination voltage (V TT). Nevertheless, the voltage applied to the associated V CCO lines must always be at or above V TT and I/O pad voltages.
4.There is approximately 100mV of hysteresis on inputs using LVCMOS25 or LVCMOS33 standards.
5.All dedicated pins (M0-M2, CCLK, PROG_B, DONE, HSWAP_EN, TCK, TDI, TDO, and TMS) use the LVCMOS standard and draw power from the
V CCAUX rail (2.5V). The dual-purpose configuration pins (DIN/D0, D1-D7, CS_B, RDWR_B, BUSY/DOUT, and INIT_B) use the LVCMOS standard before the user mode. For these pins, apply 2.5V to the V CCO Bank 4 and V CCO Bank 5 rails at power-on and throughout configuration. For information concerning the use of 3.3V signals, see 3.3V-T olerant Configuration Interface, page47.
6.The Global Clock Inputs (GCLK0-GCLK7) are dual-purpose pins to which any signal standard can be assigned.
7.For more information, see XAPP457.
Table 46:Timing for the IOB Three-State Path
Symbol Description Conditions Device
Speed Grade
Units -5-4
Max(3)Max(3)
Synchronous Output Enable/Disable Times
T IOCKHZ Time from the active transition at the
OTCLK input of the Three-state Flip-Flop
(TFF) to when the Output pin enters the
high-impedance state LVCMOS25, 12mA
output drive, Fast slew
rate
All0.740.85ns
T IOCKON(2)Time from the active transition at TFF’s
OTCLK input to when the Output pin drives
valid data
All0.720.82ns Asynchronous Output Enable/Disable Times
T GTS Time from asserting the Global Three State
(GTS) net to when the Output pin enters the
high-impedance state LVCMOS25, 12mA
output drive, Fast slew
rate
XC3S200
XC3S400
7.718.87ns
XC3S50
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
8.389.63ns
Set/Reset Times
T IOSRHZ Time from asserting TFF’s SR input to when
the Output pin enters a high-impedance
state LVCMOS25, 12mA
output drive, Fast slew
rate
All 1.55 1.78ns
T IOSRON(2)Time from asserting TFF’s SR input at TFF
to when the Output pin drives valid data XC3S200
XC3S400
2.24 2.57ns
XC3S50
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
2.91
3.34ns
Notes:
1.The numbers in this table are tested using the methodology presented in Table48 and are based on the operating conditions set forth in
T able32 and Table35.
2.This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data
Output. When this is true, add the appropriate Output adjustment from Table47.
3.For minimums, use the values reported by the Xilinx timing analyzer.
Table 47:Output Timing Adjustments for IOB
Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the Following Signal Standard (IOSTANDARD)Add the Adjustment Below
Units Speed Grade
-5-4
Single-Ended Standards
GTL00.02ns GTL_DCI0.130.15ns GTLP0.030.04ns GTLP_DCI0.230.27ns HSLVDCI_15 1.51 1.74ns HSLVDCI_180.810.94ns
Table 52:CLB Distributed RAM Switching Characteristics
Symbol Description
-5-4
Units Min Max Min Max
Clock-to-Output Times
T SHCKO Time from the active edge at the CLK input to data appearing on
the distributed RAM output
– 1.87– 2.15ns Setup Times
T DS Setup time of data at the BX or BY input before the active
transition at the CLK input of the distributed RAM
0.46–0.52–ns
T AS Setup time of the F/G address inputs before the active transition
at the CLK input of the distributed RAM
0.46–0.53–ns
T WS Setup time of the write enable input before the active transition at
the CLK input of the distributed RAM
0.33–0.37–ns Hold Times
T DH, T AH, T WH Hold time of the BX, BY data inputs, the F/G address inputs, or
the write enable input after the active transition at the CLK input
of the distributed RAM
0–0–ns
Clock Pulse Width
T WPH, T WPL Minimum High or Low pulse width at CLK input0.85–0.97–ns Table 53:CLB Shift Register Switching Characteristics
Symbol Description
-5-4
Units Min Max Min Max
Clock-to-Output Times
T REG Time from the active edge at the CLK input to data appearing on
the shift register output
– 3.30– 3.79ns Setup Times
T SRLDS Setup time of data at the BX or BY input before the active
transition at the CLK input of the shift register
0.46–0.52–ns Hold Times
T SRLDH Hold time of the BX or BY data input after the active transition at
the CLK input of the shift register
0–0–ns Clock Pulse Width
T WPH, T WPL Minimum High or Low pulse width at CLK input0.85–0.97–ns