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BK1086-88E Datasheet v1.2

BK1086/88E

Rev.1.2 Copyright?2012 by Beken Corporation BK1086/88 E

Beken Confidential. Information contained herein is covered under non-disclosure agreement (NDA).

B ROADCAST AM/FM/SW/LW R ADIO R ECEIVER

Features

? Worldwide 64~108 MHz FM band

support

? Worldwide 520~1710kHz AM band

support

? SW band support(2.3-21.85MHz,

BK1088E only)

? LW band support(153-279kHz,BK1088E

only)

? Automatic gain control(AGC)

? Automatic frequency control(AFC) ? Digital FM stereo decoder

? Automatic FM stereo/mono blend ? Automatic noise suppression ? 50us/75us de-emphasis ? RDS/RBDS decoder

? 2.4 ~ 5.5 V supply voltage

? Wide range reference clock support ? 32.768KHz crystal oscillator

? 4x4 mm 24-pin QFN package and SSOP

20-pin package

Applications

? Table and portable radios ? CD/DVD players ? Modules

General Description

The BK1086/88E AM/FM receiver employs a low-IF architecture, mixed signal image rejection and all digital demodulation technology. The station scan of BK1086/88 searches radio stations based on both the channel RSSI estimation and signal quality assessment, increases the number of receivable stations while avoids false stops. BK1086/88E enables FM/AM/SW/LW radio reception with low power, small board space and minimum number of external component.

GND FMI RFGND

AMI GND GND

SCLK

SDIO

RCLK

VIO

VD GND ROUT LOUT GND

VA G P I O 3

G P I O 2E X T L N A

R I N L I N

G N D

QFN 24 Pin Assignments (Top View)

Functional Block Diagram

M U

1 Table of Contents

1 Table of Contents (2)

2 Functional Description (3)

2.1 FM Receiver (3)

2.2 AM Receiver (3)

2.3 Interface Bus (4)

2.3.1 I2C bus mode (4)

2.4 Stereo Audio Processing (4)

2.5 Seek/Tune System (5)

2.6 GPIO output (6)

2.7 RDS Processor (6)

2.8 Reference Clock (6)

2.9 Initialization Sequence (6)

3 Design Specification (8)

3.1 Recommended Operating Conditions (8)

3.2 Power Consumption Specification (8)

3.3 Receiver Characteristics (9)

3.4 I2C Control Interface Characteristics (11)

4 Register Definition (12)

5 Pin Assignment (22)

6 Typical Application Schematic (24)

7 Package information (26)

8 Solder Reflow Profile (29)

9 Order information (30)

10 Additional Reference Resource (31)

11 Revision History (32)

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2 Functional Description

C O N T R O L I N T E R F A C E

ROUT

VIO

SCLK SDIO GPIO

BK1086/88E

FM/SW ANT

DAC

Figure1. Functional Block Diagram

2.1 FM Receiver

The receiver employs a digital low-IF architecture that reduces external components, and integrates a low noise amplifier (LNA) supporting the worldwide FM broadcast band (64 to 108MHz), an automatic gain control (AGC) circuit controls the gain of the LNA to optimize sensitivity and rejection of strong interferers, an image-reject mixer down converts the RF signal to low-IF, The mixer output is amplified by a programmable gain control (PGA), and digitized by a high resolution analog-to-digital converters (ADCs). An audio DSP finishes the channel selection, FM demodulation, stereo MPX decoder and output audio signal. The MPX decoder can autonomous switch from stereo to mono to limit the output noise.

2.2 AM Receiver

BK1086/88E supports worldwide AM band reception by a digital low-IF architecture with minimum number of external components. This architecture allows for high-precision filtering, offering excellent selectivity and noise suppression. Similar to the FM receiver, the integrated LNA and AGC optimize sensitivity and rejection of strong interferers allowing better reception of weak stations. The BK1086/88E provides highly accurate digital AM tuning without factory adjustments. To offer maximum flexibility, the receiver supports a wide range of ferrite loop sticks from 180–600 μH for MW band..

2.3 Interface Bus

The BK1086/88E supports I2C control interface, with up to 2.5 MHz clock speed.

BK1086/88E always latches data at the SCLK rising edge and outputs its data at SCLK falling edge. For MCU, data should be always written at the falling edge of SCLK, and read out at the rising edge of SCLK.

2.3.1 I2C bus mode

I2C bus mode only uses SCLK and SDIO pins. A transaction begins with the start condition, which occurs when SDIO falls while SCLK is high. Next, user drivers an 8-bit device ID serially on SDIO, which is captured by BK1086/88E at the rising edge of SCLK. The device ID of BK1086/88E is 0x80. After driving the device ID, user drives an 8-bit control word on SDIO. The control word consists of a 7-bit start register address, followed by a read/write bit (read = 1, write = 0).

For I2C host reading, the host must give an ACK to BK1086/88E after each byte access, and should give a NACK to BK1086/88E after last byte read out. For stable communication, the rising edge time of SCLK should be less than 200ns.

Figure 2. I2C Interface Diagram

2.4 Stereo Audio Processing The output of the FM demodulator is a stereo multiplexed (MPX) signal. MPX signal format consists of left + right (L+R) audio, left – right (L–R) audio, a 19 kHz pilot tone, and RDS data.

The BK1086/88E has integrated stereo decoder automatically decodes the MPX signal. The 0 to 15 kHz (L+R) signal is the mono output of the FM tuner. Stereo is generated from the (L+R), (L-R), and a 19 kHz pilot tone. The pilot tone is used as a reference to recover the (L-R) signal. Separate left and right channels are obtained by adding and subtracting the (L+R) and (L-R) signals, respectively. Adaptive noise suppression

is employed to gradually combine the stereo left and right audio channels to a mono (L+R) audio signal as the signal quality degrades to maintain optimum sound fidelity under varying reception conditions. The signal level range over which the stereo to mono blending occurs can be adjusted by setting the BLNDADJ [1:0] register. Stereo/mono status can be monitored with the ST register bit and mono operation can be forced with the MONO register bit and stereo operation can be forced with the STEREO register bit.

BK1086/88E uses pre-emphasis and de-

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emphasis to improve the signal-to-noise ratio of FM receivers by reducing the effects of high frequency interference and noise. When the FM signal is transmitted, a pre-emphasis filter is applied to accentuate the high audio frequencies. All FM receivers incorporate a de-emphasis filter which attenuates high frequencies to restore a flat frequency response. Two time constants, 50 or 75μs, are used in various regions. The de-emphasis time constant is programmable with the DE bit. High-fidelity stereo digital-to-analog converters (DACs) drive analog audio signals onto the LOUT and ROUT pins. The audio output may be muted with the DMUTE bit. Volume can be adjusted digitally with the VOLUME [4:0] bits. The soft mute feature is available to attenuate the audio outputs and minimize audible noise in very weak signal conditions. The soft mute attack and decay rate can be adjusted with the SMUTER [1:0] bits where 00 is the fastest setting. The soft mute attenuation level can be adjusted with the SMUTEA [1:0] bits where 00 is the most attenuated. The soft mute disable (DSMUTE) bit may be set high to disable this feature.

2.5 Seek/Tune System

In FM mode, channel spacing of 10， 50, 100 or 200 kHz is selected with bits SPACE [1:0]. The channel is selected with bits CHAN [14:0]. The bottom of the band is set to 64 MHz, 76 MHz or 87 MHz with the bits BAND [1:0]. The tuning operation begins by setting the TUNE bit. After tuning completes, the seek/tune complete (STC) bit will be set and the RSSI level is available by reading bits RSSI [6:0]. The TUNE bit must be set low after the STC bit is set high in order to prepare for the next tune operation and clear the STC bit. Seek tuning searches up or down for a channel with RSSI greater than the seek threshold set with the SEEKTH [6:0] bits and SNR greater than the SNR threshold set with the SKSNR [6:0] bits. In addition, an optional AFCRL and/or impulse noise detector may be used to qualify valid stations. The AFCRL detector is set by SKAFCRL and the SKCNT [3:0] bits set the impulse noise threshold. Using the extra seek qualifiers can reduce false stops and, in combination with lowering the RSSI seek threshold, increase the number of found stations. Two seek modes are available. If the seek mode (SKMODE) bit is low when seeking process is initiated, the device seeks through the band, wraps from one band edge to the other, and continues seeking. If the seek operation was unable to find a channel, the seek failure/band limit (SF/BL) bit will be set high and the device will return to the channel selected before the seek operation began. If the SKMODE bit is high when seeking process is initiated, the device seeks through the band until the band limit is reached and the SF/BL bit will be set high. A seek operation is initiated by setting the SEEKUP and SEEK bits. After the seek operation completes, the STC bit will be set, and the RSSI level as well as the tuned channel number are available by reading bits RSSI [7:0] and bits READCHAN [14:0]. During a seek operation READCHAN [14:0] is also updated and may be read to supervise the seeking progress. The STC bit is set after the seek operation completes. The channel is valid if the seek operation completes and the SF/BL bit is set low. Note that if the AFCRL bit is set or the

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SNR and RSSI are lower than the thresholds, the audio output is muted as

in the soft mute case discussed in stereo audio processing section. The SEEK bit should be set low after the STC bit is set high in order to prepare for the next seek operation as well as clearing the STC and SF/BL bits. The device can be configured to generate an interrupt on GPIO2 when a tune or seek operation completes. Setting the seek/tune complete (STCIEN) bit and GPIO2 [1:0]

= 01 will configure GPIO2 for a 5 ms low interrupt when the STC bit is set by the device.

The AM mode tuning system algorithm

is same as FM mod

2.6 GPIO output

The BK1086/88E has two GPIO pins. The function of GPIO pins could be programmed with bits GPIO2 [1:0], GPIO3 [1:0], GPIO2/3 pins can be used as interrupt request pins for the seek/tune

or RDS ready functions and as a stereo/mono indicator respectively.

GPIO functionality is available regardless of the state of the VA and VD supplies, or the ENABLE and DISABLE bits.

2.7 RDS Processor

The BK1086/88E implements an RDS processor for symbol decoding, block synchronization, error detection, and error correction. Set the RDSEN=1 will enable RDS reception, and set RDSDEC=1 will enable automatic error correction. After error check and processing, if a correct RDS frame is received, the received block will be placed at RDSA, RDSB, RDSC and RDSD registers and RDS ready bit RDSR will be set. When RDSIEN is enabled, a 5 ms active low interrupt will be issued on GPIO2.

2.8 Reference Clock

The BK1086/88E accepts wide range, from 32.768 kHz to 38.4 MHz, reference clock input to the RCLK pin. For frequency less than 4 MHz, it must be multiplier of 32.768 KHz. The BK1086/88E also support 32.768KHz crystal oscillator. Low quality reference clock with 100ppm is acceptable.

2.9 Initialization Sequence

To initialize BK1086/88E:

1.Supply VIO.

2.Supply VA and VD. Note that VA

and VD could be supplied at the

same time of VIO supplied.

3.Provide RCLK.

4.Set the ENABLE bit high and the

DISABLE bit low to power up

BK1086/88E.

To power down BK1086/88E:

1.Set the ENABLE bit high and the

DISABLE bit high to place

BK1086/88E in power down mode.

Note that all register states are

maintained as long as VIO is

supplied.

2.(Optional) Remove RCLK.

3.Remove VA and VD as needed.

To power up BK1086/88E(after power down):

1.Note that VIO is still supplied in this

scenario. If VIO is not supplied,

refer to BK1086/88E initialization

procedure above.

2.Supply VA and VD.

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3. Provide RCLK.

4. Set the ENABLE bit high and the

DISABLE bit low to power up BK1086/88E.

Figure 3 Initialization Sequence

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3 Design Specification

3.1 Recommended Operating Conditions

Table 1 Recommended Operating Conditions Parameter

Symbol Test Condition

Min Typ Max Unit Digital Supply Voltage V D 2.2 — 5.5 V Analog Supply Voltage V A 2.2 — 5.5 V Interface Supply Voltage V IO 1.6 — 3.6 V Ambient Temperature T A

–20

°C

Notes:

All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at V D = V A = 3.3 V and 25 °C unless otherwise stated. Parameters are tested in production unless otherwise stated. For SSOP20 package, VDD range is 2.2-3.6V.

3.2 Power Consumption Specification

Table 2 Power Consumption Specification Parameter

Symbol Test Condition

Min

Typ

Max

Unit

Supply Current (FM Mode) I S ENABLE = 1 DISABLE = 0 — 22 24 mA Supply Current (AM Mode) I S ENABLE = 1 DISABLE = 0 — 20 22 mA Power down Current I PD ENABLE = 0 DISABLE = 1 — 10 20 μA Interface Power down Current

Ip IO

SCLK, RCLK inactive

ENABLE = 0

— 1.9 5

μA

3.3 Receiver Characteristics

Table 3 FM Receiver Characteristics

Parameter Test Condition Min Typ Max Unit Input Frequency 64 — 108 MHz Sensitivity2,3,4,5,6(S+N)/N = 26 dB — 1.7 2.2 μV EMF LNA Input Resistance7 2.5 3 3.5 k?

Input IP38— 92 — dBμV EMF AM Suppression2, 3, 4, 5, 7m = 0.3 40 45 — dB Adjacent Channel Selectivity ±200 kHz 40 45 — dB Alternate Channel Selectivity ±400 kHz 50 60 — dB Audio Output Voltage2, 3, 4, 7 —110 — mV RMS Audio Stereo Separation2, 4, 5, 730 — — dB Audio S/N2, 3, 4, 5, 7, 55 — dB Audio THD2, 3, 5, 7, 10— 0.1 0.3 %

μs

75 De-emphasis Time Constant 1150

Audio Common Mode Voltage12ENABLE = 1 1.0 1.1 1.2 V Audio Output Load Resistance Single-ended — 32 — ?

Seek/Tune Time — — 60 ms/channel

–3 — 3 dB RSSI Offset Input levels of 8 and 50

dBμV at RF input

Notes:

1.Volume = maximum for all tests

2.F MOD = 1 kHz, 75 μs de-emphasis

3.MONO = 1, and L = R unless noted otherwise

4.Δf = 22.5 kHz

5.B AF = 300 Hz to 15 kHz, A-weighted

6.Sensitivity without matching network

7.Measured at V EMF = 1 mV, f RF = 64 to 108 MHz

8.|f2 – f1| > 2 MHz, f0 = 2 x f1 – f2. AGC is disabled by setting AGCD = 1

9.The channel spacing is selected with the SPACE [1:0] bits

10.Δf = 75 kHz

11.The de-emphasis time constant is selected with the DE bit

12.At LOUT and ROUT pins

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Table 4 AM Receiver Characteristics Parameter

Test Condition Min Typ Max Unit Frequency Long Wave(AM)

153 — 279 kHz

Medium Wave(AM) 520 — 1710 kHz

Short Wave(SW) 2.3 — 21.85 MHz

Sensitivity 1,2,3

(S+N)/N = 26 dB — 20 μV EMF Large Signal Voltage Handling 300 mV RMS Power Supply Rejection Ratio 40 — dB Audio Output Voltage — 100 — mV RMS

Audio S/N 1,2,3,5

55 — dB

Audio THD 1,2,3,5

— 0.1 %

Antenna Inductance

Medium Wave(AM) 180 600 uH

Long Wave(LW) 2800

Power Up Time From power down — 150 ms Notes:

1. FMOD = 1kHz , 30%modulation , A-weighted , 2 kHz channel filter

2. B AF = 300 Hz to 15 kHz, A-weighted

3. f RF = 1000kHz

4. Guaranteed by characterization

5. V IN = 5 mV RMS

Table5 Line in Characteristics Parameter

Test Condition Min Typ Max Unit

Input Frequency Range <3dB 30 — 12kHz Hz Max Input Level 1

THD<1% — 400 — mV RMS

Audio SNR 1,2,3（SNR ）

— 65 — dB Audio THD 1,2,3

（THD ）

— 0.1 — % Audio Common Mode Voltage — 1.1 — V Audio L/R Separation — 70 — dB

Linein/FM Separation 4

50 — 90 dB Notes ：

1. F Aud = 1 kHz ；

2. V IN = 330 mV RMS ;

3. Volume=Maxim ；

4. When Lin1(Rin1) is selected as input ，the maximum separation(90dB) is between Lin2(Rin2) and

FM audio; the minimum separation(50dB) is between Lin1(Rin1) and FM audio

5. When Lin2(Rin2) is selected as input ，the maximum separation(90dB) is between Lin1(Rin1) and

FM audio; the minimum separation(50dB) is between Lin2(Rin2) and FM audio

3.4 I2C Control Interface Characteristics

Table 6 I2C Control Interface Characteristics

Parameter Symbol

Test

Condition Min

Typ

Max

Unit SCLK Frequency f SCL— —

400

kHz SCLK Low Time t LOW 1.3 — —

μs SCLK High Time t HIGH0.6 μs

SCLK Input to SDIO ↓Setup (START) t SU:STA0.6 — —

SCLK Input to SDIO ↓

Hold (START)

t HD:STA0.6 — —

μs

SDIO Input to SCLK ↑

Setup

t SU:DAT100 — —

SDIO Input to SCLK ↓

Hold

t HD:DAT— — 900

SCLK Input to SDIO ↑

Setup (STOP)

t SU:STO0.6 — —

μs

STOP to START Time t BUF 1.3 — —

μs

SDIO Output Fall Time t f:OUT— — 250

ns SDIO Input, SCLK

Rise/Fall Time

t f:IN

t r:IN

—

200

SCLK, SDIO Capacitive

C b— — 60 pF

Input Filter Pulse

Suppression

t SP— — 40 ns t SU:STA t HD:STA t LOW t HIGH t r:IN t f:IN t SP t SU:STO t BUF

t r:IN t HD:DAT t SU:DAT f:IN,

t f:OUT

Figure 4 I2C Control Interface Read and Write Timing Diagram

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4 Register Definition

BIT NAME DEFAULT DESCRIPTION [15:0] DEVID[15:0] 16’h9255 Device ID

BIT NAME

DEFAULT DESCRIPTION [15:0] CHIPID[15:0]

16h’1080 Chip ID

BIT NAME

DEFAULT DESCRIPTION [15] DSMUTE 1’h0 Soft mute Disable.

0 = Soft mute enable. 1 = Soft mute disable.

[14] MUTEL 1’h0 Mute L channel.

0 = L channel normal operation. 1 = L channel mute.

[13]

MUTER

1’h0 Mute R channel.

0 = R channel normal operation. 1 = R channel mute.

[12] MONO 1’h0 Mono.

0 = Normal operation. 1 = Force mono.

[11] STEREO

1’h0 Stereo

0 = Normal operation. 1 = Force stereo.

MONO and STEREO cannot be set to 1 simultaneously.

[10] SKMODE 1’h0 Seek Mode

0 = Wrap

1 = Stop at the upper or higher band limit

[9] SEEKUP 1’h1 Seek Direction.

0 = Seek down. 1 = Seek up.

[8] SEEK

1’h0 Seek

0 = Disable 1 = Enable seek

A pos edge can start the seek process and during it SEEK should

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be 1 [7]

SKAFCRL

1’h1

Seek with AFC Rail

0 = During seeking, the channel is valid no matter whether AFCRL is high or low.

1 = During seeking, the channel is invalid if AFCRL is high. [6] DISABLE 1’h0

Power up Disable 0 = Normal operation 1= Power down

[5:1]

SNR_REF[4:0] 5’h0

Output SNR adjustment. Read SNR = SNR (calculated) – SNR_REF

[0] ENABLE

1’h0

Power up Enable

0 = Power down 1 = Normal operation

Note: Only DISABLE=0 and ENABLE=1 can power on the device

BIT NAME DEFAULT DESCRIPTION [15] TUNE

1’h0 Tune

0 = Disable

1 = enable Note: a pos edge can start the tune process and during it TUNE must be 1 and SEEK must be 0

[14:0] CHAN[14:0] 15’h0 Channel Select

The tuned Frequency = Band + CHAN * SPACE

BIT NAME DEFAULT DESCRIPTION [15]

RDSIEN

1’h0

RDS Interrupt Enable 0 = disable. 1 = enable.

When register GPIO2[1:0]=2’b01 and new RDS come, a 5ms low pulse will appear at GPIO2 [14] STCIEN 1’h0

Seek/Tune Complete Interrupt Enable 0 = disable. 1 = enable.

When register GPIO2[1:0]=2’b01 and seek or tune finish, a 5ms low pulse will appear at GPIO2 .Both RDSIEN and STCIEN can be high [13] AFCINV 1’h0 AFC Invert

0 = Normal AFC into mixer 1 = Reverse AFC into mixer [12] RDSEN

1’h1

RDS Enable 0 = Disable RDS. 1 = Enable RDS

[11] DE 1’h0

De-emphasis

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0 = 75us 1 = 50us

[10:9]

TCPILOT

2’h0

The Time Used to Cal The Strength of Pilot 00:4ms 01:8ms 10:16ms 11:32ms

[8:6] PILOTS

[2:0]

3’h3 Stereo Threshold of Pilot Strength

[5:4] GPIO3[1:0]

2’h0

General Purpose I/O 3. 00 = Low

01 = Mono/Stereo indicator (ST) 10 = Low 11 = High

[3:2] GPIO2[1:0] 2’h0

General Purpose I/O 2. 00 = Low

01 = STC/RDS interrupt. 10 = Low 11 = High [1:0] Reserved 2’h0

Reserved

BIT NAME DEFAULT DESCRIPTION [15:9] SEEKTH [6:0]

7’h1e RSSI Seek Threshold

[8:7] BAND[1:0] 2’h3 Band Select

AM: 00: LW 153~279e3 FM:00: FULL 64~108e6

01: MW 520~1710e3 01: East Europe 64~76e6 10: SW 2.3~21.85e6 10: Japan 76~91e6 11: MW 522~1710e3 11: Europe 87~108e6 (LW and SW Band are only defined at BK1088E)

[6:5] SPACE[1:0]2’h2 Channel Spacing

AM: 0: 1e3 FM: 0: 10e3 1: 5e3 1: 50e3 2: 9e3 2: 100e3 3: 10e3 3: 200e3

[4:0] VOLUME [4:0] 5’h0f Volume

0x00 is the lowest and 0x1F is highest (0dBFS). 2dB each

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BIT

NAME DEFAULT

DESCRIPTION

[15:14] SMUTER[1:0] 2’h0

Soft mute Attack/Recover Rate

00 = fastest 01 = fast 10 = slow 11= slowest [13:12] SMUTEA[1:0] 2’h0

Soft mute Attenuation. 00 = 16db. 01 = 14db 10 = 12db, 11 = 10db [11] CLKSEL 1’h1 Clock Select

0 = External clock input, 1= Internal oscillator input. [10:4] SKSNR[6:0] 7’h06 Seek SNR Threshold.

Required channel SNR for a valid seek channel [3:0]

SKCNT[3:0]

4’hf

Seek Impulse Detection Threshold

Allowable number of impulse for a valid seek channel while setting all zeros means not use Impulse number to judge the channel’s validity.

BIT NAME DEFAU LT DESCRIPTION

[15]

LINEIN_SEL

1’h0

Audio Line in Channel Select 0: Channel1; 1: Channel2;

(QFN24 only support one line in channel)

[14] LINEIN_EN 1’h0 Audio Line in Enable

0: Disable ( Receiver Mode) 1: Enable

[13] MODE 1’h0 Receiver Mode Select

0 = FM receiver 1 = AM receiver

[12] SIQ 1’h0 IF I/Q Signal switch.

0 = Normal operation 1 = Reversed I/Q signal

[11]

IMPEN

1’h0 Impulse Remove Enable

0 = Disable 1 = Enable

[10] BPDE

1’h0 De-emphasis Bypass

0 = Normal operation 1 = Bypass de-emphasis

[9:8] IMPTH[1:0]

2’h1 Threshold of Impulse Detect.

00 = toughest 11 = loosest

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[7] DACCK_SEL 1’h0

DAC Clock Select

0：2.432MHZ 1：4.864MHZ

[6] STHYS_SEL 1’h0 ST/MONO Transition Hysterisis Select

0：6dB

1：2dB [5:3] Reserved [2:0]

3’h0 Reserved

[2:0] FMGAIN [2:0] 3’h1 The gain of Frequency demodulated.

000 = 0dB … 011= +18dB

100= 0dB … 111= -18dB

BIT NAME DEFAULT DESCRIPTION [15] AFCEN 1’h1 AFC Enable

0 = Disable 1 = Enable

[14:13] TCSEL[1:0]2’h1 AFC/RSSI/SNR Calculate Rate

00 = fastest

11 = slowest. 4X times each

[12] SEL25K 1’h0 AFCRL Threshold

0 = Channel space/2 1 = 25kHz

[11] AVE 1’h1 AFC Average

0 = Use the instant AFC value 1 = Use the average AFC value

[10:9] VAR[1:0] 2’h2 Variation Threshold for average AFC calculation

00 = Disable

01 = the most strict 11 = the loosest

[8:7] RANGE [1:0] 2’h1 AFC Average Range

00 = the most strict

11 = the loosest

[6:0] AFCRSSIT H[6:0]

7’h10 RSSI Threshold for Instant AFC updating

BIT NAME DEFAULT DESCRIPTION [15:7] AFC[8:0] 9’h000 The AFC value.

unit AM 0.15k Hz, FM 0.6k Hz

[6:0]

SNR[6:0]

7’h00 The SNR Value.( in dB)

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BIT NAME

DEFAULT DESCRIPTION [15] RDSR

1’h0 RDS Ready Indicator

0 = Not Ready 1 = Ready

Keep high for 40ms after new RDS is received

[14] STC 1’h0 Seek/Tune Complete

0 = Not Complete 1 = Complete

[13] SF/BL 1’h0 Seek Fail/Band Limit

0 = Seek successful.

1 = Seek fail/Band limit reached

[12] AFCRL 1’h0 AFC Rail

0 = AFC not railed 1 = AFC railed

[11:9] Reserved 3’h0 Reserved [8]

STEN

1’h0

Stereo Signal Decoded Indicator [7] ST 1’h0

Stereo Signal Received Indicator

[6:0] RSSI[6:0] 7’h00

RSSI value

BIT NAME DEFAULT DESCRIPTION [15] Reserved 1’h0 Reserved [14:0] READCHA N[14:0] 15’h0000 Read Channel

Provides the current working channel

BIT NAME DEFAULT DESCRIPTION [15:0]

RDSA[15:0]

16’h0000 The First Register of RDS Received

BIT NAME

DEFAULT DESCRIPTION [15:0]

RDSB[15:0]

16’h0000 The second register of RDS received

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BIT NAME

DEFAULT DESCRIPTION [15:0]

RDSC[15:0]

16’h0000 The third register of RDS received

BIT NAME DEFAULT DESCRIPTION [15:0]

RDSD[15:0]

16’h0000 The fourth register of RDS received when read

BIT NAME

DEFAULT DESCRIPTION [15:0] Reserved

16’h7b11 Reserved.

BIT NAME

DEFAULT DESCRIPTION

[15:0]

IMPCNT[8:0]

9’h000

Audio Impulse Number Indicator [6:4] STSNR[2:0] 3’h4

Mono/Stereo SNR Threshold 000：The loosest ；

111：The most strict (2dB/Step)

[3:0]

BLNDADJ [3:0]

4’ha

Mono/Stereo RSSI Threshold 000：The loosest ；

111：The most strict (2dB/Step)

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BIT NAME

DEFAULT DESCRIPTION [15:0] Reserved

16’h4000 Reserved.

BIT NAME DEFAULT DESCRIPTION [15:0]

Reserved

16’h3e00 Reserved.

BIT NAME DEFAULT DESCRIPTION

[15] SKMUTE 1’h1 0: disable soft mute when seeking 1: enable soft mute when seeking

[14] AFCMUTE 1’h1 0: disable soft mute when AFCRL is high 1: enable soft mute when AFCRL is high [13:7] SNRMTH[6:0] 7’h05 The Mute Threshold Based on SNR [6:0]]

RSSIMTH[6:0]

7’h1a

The Mute Threshold Based on RSSI

BIT NAME

DEFAULT DESCRIPTION [15:0] Reserved

16’h79f8 Reserved.

BIT NAME DEFAULT DESCRIPTION [15:0] Reserved 16’h4012

Reserved.

Proprietary and Confidential Page 20 of 32

BIT NAME DEFAULT DESCRIPTION [15:0]

Reserved

16’h0040

Reserved.

BIT NAME DEFAULT DESCRIPTION [15:0]

Reserved

16’h341c

Reserved.

BIT NAME DEFAULT DESCRIPTION [15:0]

Reserved

16’h0080

Reserved.

Do not write anytime.

BIT NAME DEFAULT DESCRIPTION [15:9]

Reserved

7’h00 Reserved.

[8:4] ANT_SEL[5:0] 9’h000 Antenna Varactor Value [3:0] Reserved

4’h0

Reserved

BIT NAME

DEFAULT DESCRIPTION [15:0] Reserved

16’h4ca2

Reserved.

BK1086-88E Datasheet v1.2

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