MEMORY存储芯片TMS1020AFN中文规格书

TPC10 SERIES CMOS FIELD-PROGRAMMABLE GATE ARRAYS

SRFS001 F D3864, DECEMBER 1989 REVISED FEBRUARY 1993

． ． ．．．． Four Arrays With u p to 2000 Usable E q uivalent Gates Tl Action Logie r " System (TI-ALS) So何ware for: -

ViewLogic ? -Ment 。r ?－。rCAD/SDT Ill rM -Cadence ?/Valid ? Reliable Antifuse Interconnect Built-In Clock Distribution Network Silicon-Gate CM 。S Technology

Deskto p TI-ALS Creates Design Files fo『：-I ／。Pin Assignment -Design Validation -Place and Route -Circuit Timing Analysis -Array Antifuse P『ogra『n『ning -Test and Debug 23E G －旨Z 且Z ＠也唱E 翩W Q －I 1/0 and Perlph町a l Circuits I lnterc 。nnect Tracks TPC10 Series FPGA Die A『chitecture descri p tion

The Texas Instruments (Tl ) TPC10 Series comprises fou 「field-programmable gate arrays (FPGAs ). The TPC1010A, TPC1010B, TPC1020A, and TPC1020B FPGAs are fabricated using the Tl silicon-gate CMOS process. The process features polysilicon gate, source, drain elements, and two levels of copper-doped-aluminum metallization to 「educe internal resistance and enhance performance. Typical die architectu 「e is illustrated above.

These field-programmable devices combine gate-array flexibility with desktop programmability. This combination allows the designer to avoid fabrication cycle times and nonrecurring enginee 「ing charges associated with conventional mask-programmed gate arrays. The FPGAs are uni q ue in that the arrays are fabricated, tested, and ship p ed to the user for programming. The FPGA contains user-configurable inputs, outputs, logic modules, and minimum-skew clock driver with ha「dwired distribution network. The FPGA also includes on-chip diagnostic probe capabilities and security fuses to protect the proprietary design.

Table 1. Product Family Profile

DEVICE

TPC1010A TPC1020A TPC1010B TPC1020B Capacity

Gate array equivalent gates

1200 2000 1200 2000 TIL equivalent packages

34 53 34 53 CMOS Process

1.2μm 1.2μm 1.0μm 1.0μm Logic Modules

295 547 295 547 Flip-Fl 。ps (maximum)

130 273 130 273 Antif uses

112,000 186,000 112,000 186,000 H 。

rizontal Tracks

22 22 22 22 Vertical Tracks 13 13 13 13

TPC10 SERIES CMOS FIELD-PROGRAMMABLE GATE ARRAYS

SRFS001 F -D3864, DECEMBER 1989 -REVISED FEBRUARY 1993

FPGA array performance

logic module size

A mask-programmed gate array cell with four transistors usually implements only one logic level. The TPC 1 O Series array logic module is more complex and typically implements『nultiple logic levels within a single module. This reduces intermodule wiring and associated RC delays. In e仔ect,the TPC 1 O logic module implements the equivalent of a net compression that enhances performance.

PIN

1/0 NAME

CLK

DCLK

GND

1/0

1/0 MODE

NC

PRA 。

PRB 。SDI Vee Vpp TERMINAL FUNCTI 。NS

DESCRIPTI 。N Clock. TTL clock input for global clock distribution network. The clock input is buffered prior to cl 。c king the logic m 。d ules.This pin can also be used as an 1/0. Diagnostic clock. TTL clock input for diagnostic probe and device programming. DCLK is active when the MODE pin is high. This pin functi 。ns as an 1/0 when the MODE pin is low. Ground. Input low supply voltage. lnpuv，口utput.1/0 pin functions as an input, output, 3-state, or bidirectional buffer. Input and 。utput levels are compatible with standard TTL and CMOS specifications. Unused 1/0 pins are automatically set low by the ALS software. Mode. The MODE pin controls the use of multifunction pins (DCLK, PRA, PRB, SDI). When the MODE pin is high, the special functions are active. When the MODE pin is low, the pins function as I/Os. No c 。nnection.This pin is not connected to circuit叩within the device Probe A. The probe A pin is used to output data from any user defined design n 。de within the device. This independent diagnostic pin is used in conjunction with the probe B pin to allow real拍ne diagnostic output of any signal path within

the device. The probe A pin can be used as a user-defined 1/0 when debugging has been completed. The pin ’s probe capabilities can be permanently disabled to protect the programmed design ’s confidentiality. PRA is active when the MODE pin is high. This pin functions as an 1/0 when the MODE pin is low.

Probe B. The probe B pin is used to output data from any user-defined design node within the device. This independent diagnostic pin is used in conjunction with the probe A pin to allow real-time diagnostic output of any signal path within the device. The probe B pin can be used as a user-defined 1/0 when debugging has been completed. The pin's probe capabilities can be permanently disabled to protect the programmed design ’s confidentiality. PRB is active when the MODE pin is high. This pin functions as an 1/0 when the MODE pin is low.

Serial data input. Serial data input for diagnostic probe and device programming. SDI is active when the MODE pin is high. This pin functi 。

ns as an 1/0 when the MODE pin is low.

Supply v 。ltage.Input high supply voltage. Programming voltage. Input supply voltage used for device programming. This pin must be connected to Vee during normal operation.