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XAPP1065 - Spread-Spectrum Clock Generation in Spartan-6 FPGAs

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Summary

Consumer display applications commonly use high-speed LVDS interfaces to transfer video data. Spread-spectrum clocking can be used to address electromagnetic compatibility (EMC) issues within these consumer devices. This application note uses Spartan?-6 FPGAs to generate spread-spectrum clocks using the DCM_CLKGEN primitive.

Introduction

Using Spread-Spectrum Clocking to Reduce EMI

Manufacturers of electronic devices must ensure that their products do not interfere electrically with nearby devices. For example, the clarity of a phone call should not degrade when it is next to a video display. EMC regulates the noise that causes these disturbances, including

electromagnetic interference (EMI). EMC regulations can vary depending on where the product is used, but the typical solutions involve adding expensive shielding, ferrite beads, or chokes. These solutions could further impact the overall cost of the final product by requiring more complicated PCB routing and lengthening the product development cycle.

EMC regulations test a completed end-product to measure the field strength, which is the amount of EMI noise a product emits (T able 1). An antenna measures the field strength across a range of frequencies and distances. To pass, the end-product's emissions are measured across multiple frequencies and varying distances depending on the standards body regulating the emissions.

EMC testing on a single FPGA is not useful information to a system designer since every end-product (system) has different characteristics based on all the components used, how the PCB is designed, and the mechanical enclosures. However, measuring how a clock's energy is spread across multiple frequencies has a direct impact on the emissions of an entire https://www.sodocs.net/doc/cd4223387.html,ing a spectrum analyzer, a typical clock signal is measured as a reference point as shown in Figure 1 (1R). After switching the clock signal to a spread-spectrum clock, the energy is reduced by 13dB. In this example, the frequencies are evenly distributed around the input frequency with a 3.0% center-spread modulation, sometimes referred to as ±1.5% spread.

Application Note: Spartan-6 FPGAs

XAPP1065 (v1.0) March 22, 2010

Spread-Spectrum Clock Generation in Spartan-6 FPGAs

Author: Jim Tatsukawa

Table 1: Acceptable EMC Levels

Frequency (MHz)

FCC Field Strength (dbμV/m) at 10m

CISPR Field Strength (dbμV/m) at 10m

8829.530216333023035.630960

35.6

37

Notes:

1.FCC: Federal Communications Commission.

2.

CISPR: International Special Committee on Radio Interference.

When using center-spread modulation, the clock frequency can be higher than the input frequency. Because these higher clock frequencies are introduced, the system's maximum clock frequency should be adjusted. In the example in Figure 1, the center-spread modulation is 1.5%. Spread spectrum should not be confused with jitter or clock uncertainty. Because spread spectrum uses a relatively low modulation frequency, the only effect of using spread spectrum is the higher frequencies created by the center-spread modulation.

Note:The average frequency of the modulated clock can be different than the input frequency.Down-spread modulation (similar to the example shown in Figure 1) is used in systems that cannot tolerate frequencies higher than the input frequency. In down-spread modulation, the maximum frequency matches the input frequency. Fully synchronous designs are not affected because the maximum frequency is unchanged.

How the clock frequencies change, or modulate, can also impact how the system is affected by the introduction of the spread-spectrum clock. As long as the clock frequency is slowly changed over a large number of clock cycles, the effect of the spread-spectrum clock does not impact the system. If the clock frequencies are changed too slowly (20–30KHz), then the positive benefits of spread-spectrum clocking are diminished. When clock frequencies change too quickly (>120KHz), the spread-spectrum clock can appear as jitter or not properly lock the PLL to the spread-spectrum clock.

Figure 1:

Center-Spread Modulation as Viewed With a Spectrum Analyzer

X1065_01_020910

Clock frequencies can be tracked over time to measure the modulation (Figure 3). The

modulation frequency is the frequency at which a modulated spread-spectrum clock sweeps through all of the frequencies.

Consider both frequency deviation and modulation frequency when using spread-spectrum clocking in Spartan-6 FPGA designs.

Figure 2:Down-Spread Modulation as Viewed With a Spectrum Analyzer

Figure 3:

Triangular Spread-Spectrum Clocking

X1065_02_020910

Spread- Spectrum Generation

Spread-Spectrum Generation

Spartan-6 FPGAs can generate a spread-spectrum clock source from a standard

fixed-frequency oscillator. A Spartan-6 FPGA spread-spectrum clock source is generated by using the DCM_CLKGEN primitive. The DCM_CLKGEN primitive can either use a fixed spread-spectrum solution, providing the simplest implementation, or a soft spread-spectrum solution that adds flexibility but requires additional control logic to generate the spread-spectrum clock.

As detailed in T able 2, the fixed spread-spectrum solution is for typical spread-spectrum clock requirements. It only requires setting the SPREAD_SPECTRUM attribute. The soft spread-spectrum solution provides additional flexibility, but requires an additional state

machine to control the DCM_CLKGEN primitive and is focused on video applications (M =7, D =2).The attributes used in conjunction with the soft spread-spectrum solution are VIDEO_LINK_M0, VIDEO_LINK_M1, or VIDEO_LINK_M2.

Table 2: Summary of DCM_CLKGEN Spread-Spectrum Modes

Fixed Spread-Spectrum Clock Soft Spread-Spectrum Clock SPREAD_SPECTRUM Values

CENTER_LOW_SPREAD

VIDEO_LINK_M0CENTER_HIGH_SPREAD

VIDEO_LINK_M1VIDEO_LINK_M2Additional Logic None Use sstop.v Modulation Profile Triangular T riangular Spread Direction

Center Down F MOD (Modulation Frequency)

F IN /1024

See Figure 8

Spread of CLKFX Clock Periods (Frequency Deviation)

CENTER_LOW_SPREAD:100ps/CLKFX_DIVIDE CENTER_HIGH_SPREAD:240ps/CLKFX_DIVIDE

See Figure 11

CLKFX_MULTIPL Y 2–327CLKFX_DIVIDE

1–42, 4

DCM_CLKGEN Programming Ports

N/A

PROGCLK, PROGEN, PROGDAT A, PROGDONE

Fixed Spread Spectrum The simplest way to implement spread-spectrum clocking is to use one of the fixed modes of the DCM_CLKGEN primitive. When SPREAD_SPECTRUM is set to either

CENTER_LOW_SPREAD or CENTER_HIGH_SPREAD, DCM_CLKGEN automatically creates a spread-spectrum clock. Using the fixed mode, the DCM_CLKGEN primitive internally contains all of the circuitry to create a triangular center-spread modulation. Figure4 shows a typical video implementation using the fixed mode. An additional PLL is required to multiply the clock frequency to the full SDR clock rates required for OSERDES2.

Figure 4:Example of Center-Spread Modulation using Fixed DCM_CLKGEN Spread-Spectrum Clocking

The amount of spread is dependent on the final configuration of the design. Figure 5 shows the spread for a typical video application where the DCM_CLKGEN multiplies the clock frequency by 3.5x (CLKFX_MULTIPL Y =7, CLKFX_DIVIDE =2). Depending on the amount of spread required for the application, the designer can select either CENTER_LOW_SPREAD or CENTER_HIGH_SPREAD.

When using the fixed modes, the modulation frequency is the same for both CENTER_LOW_SPREAD and CENTER_HIGH_SPREAD as shown in Figure 6.

As shown in Equation 1, the modulation frequency depends on the input frequency.

Equation 1Because center-spread modulation increases the highest frequency of the clock, adjust the

timing constraints to match. As an example, to constrain a design using a 100MHz input clock with a 4% center-spread modulation (±2%) by setting the input frequency to 102MHz.

Figure 5:Example Spread for Fixed Spread-Spectrum Clocking in Video Applications

Figure 6:

Modulation Frequency For Fixed Spread Spectrum

F MOD F IN

1024------------=

Using the DCM_CLKGEN primitive, the designer can specify the maximum amount of spread using CLKFX_MD_MAX. CLKFX_MD_MAX takes an integer value.

Equation2

Where:

M=CLKFX_MULTIPL Y

D=CLKFX_DIVIDE

SPREAD=Spread using CENTER_LOW_SPREAD/ CENTER_HIGH_SPREAD [%] Using the same example of a 4% center-spread (±2% spread) and Equation2, and assuming that CLKFX_MULTIPL Y=7 and CLKFX_DIVIDE =2, then:

CLKFX_MD_MAX=(1.02x7) / 2=3.57

Soft Spread Spectrum Soft spread-spectrum clocking uses a different mode of the DCM_CLKGEN primitive. Soft spread-spectrum clocking generates a triangular down-spread modulation by a continual process of reprogramming DCM_CLKGEN. The DCM_CLKGEN primitive must be set to:

SPREAD_SPECTRUM=

Soft spread-spectrum clocking only works when using the programming interface. As a result, not using PROGCLK and PROGDATA will generate an error.

Note:In Spartan-6 devices, only the top eight BUFGMUX clock buffers can drive PROGCLK.

By focusing on down-spread modulation, the soft spread-spectrum solution does not affect overall timing analysis for the system. Because down-spread modulation slows down the average frequency, the design must ensure data is not lost when switching between the input clock domain and the spread-spectrum clock domain.

Reference Design For Soft Spread-Spectrum Clocking

The Reference Design file contains the following files:

xapp_ss.v

Reference design combining PLL to generate OSERDES outputs targeting M/D=7/2 dcm_clkgen_softspread.v

Wrapper to be used in place of DCM_CLKGEN instance targeting M/D = 7/2 dcm_clkgen

DCM_CLKGEN instantiation

sstop.v

State machine used to control spread

sscontrol

Programming state machine

xapp_ss_m7d4.v

Reference design combining PLL to generate OSERDES outputs targeting M/D = 7/4 dcm_clkgen_softspread_m7d4.v

Wrapper to be used in place of DCM_CLKGEN instance M/D = 7/4

The reference design also contains a typical video application using soft spread-spectrum clocking to generate the clock frequencies for OSERDES2. As shown in Figure7,

DCM_CLKGEN_SOFTSPREAD replaces the DCM_CLKGEN primitive. Within

DCM_CLKGEN_SOFTSPREAD, DCM_CLKGEN is connected to the state machine used for controlling the generation of spread spectrum (SSTOP).

CLKFX MAX_SPREAD_SPECTRUM1SPREAD

2

-------------------------

+

??

??M

D

----

×

=

Figure 7:Reference Design Clock Structure

To create the modulation, the reference design programs different CLKFX frequencies using a small state machine contained within SSTOP. When the modulation is at the lowest frequency within the expected modulation, CLKFX is increased. Similarly, when the modulation is at the peak of the modulation range, CLKFX is decreased.

As an example, if the input frequency is 85MHz with the DCM_CLKGEN primitive programmed using CLKFX_MULTIPL Y=7 and CLKFX_DIVIDE=2, then CLKFX is set to 297.5MHz. To speed up, CLKFX is reprogrammed to CLKFX_MULTIPL Y=7 and CLKFX_DIVIDE=1. An 85MHz input clock implies a CLKFX frequency of 595MHz. However, this frequency can never actually be reached. Because the frequencies are slowly changed, SSTOP is able to monitor the frequencies. As the modulation reaches the fastest frequency within the expected range, SSTOP sets the direction of the modulation by programming a slower CLKFX frequency. To slow down the modulated frequency, the DCM_CLKGEN primitive is reprogrammed to CLKFX_MULTIPL Y=7 and CLKFX_DIVIDE=3. Again, SSTOP reprograms CLKFX when the frequency has slowed down to the frequency defined by SSTOP. Because the reference design is targeting video applications, both M and D must be taken into consideration. The reference design uses M=7 and D=2.

To control how quickly the DCM_CLKGEN primitive frequencies change after being programmed, place the SPREAD_SPECTRUM attribute into one of three modes for soft spread-spectrum clocking: VIDEO_LINK_M0, VIDEO_LINK_M1, or VIDEO_LINK_M2. When the SPREAD_SPECTRUM attribute is set to VIDEO_LINK_M0, CLKFX changes the frequencies at the fastest rate. Modulation frequencies are the fastest when using

VIDEO_LINK_M0 as shown in Figure8.

Example: LVDS for Video Clock Frequencies of 30 To 105MHz

Focusing on a typical LVDS implementation commonly found in video designs, the SOFT_SS state machine is contained in the reference design. The reference design supports typical video applications requiring 7:1 serialization using the DCM_CLKGEN primitive with a cascaded PLL (Figure 9). The DCM_CLKGEN primitive generates the spread-spectrum

modulation. The cascaded PLL provides the high-speed clock required for the BUFPLL as well as providing additional filtering to reduce the cycle-to-cycle jitter.

Figure 8:

SPREAD_SPECTRUM Effect on Modulation Frequency

Figure 9:

Soft Spread-Spectrum Clocking Video Implementation (30

Example: LVDS for Video Clock Frequencies Beyond 105MHz

As long as the pixel clock frequencies can be supported, the solution shown in Figure9 works.

However, it is limited by the maximum frequency for CLKFX and CLKOUT_FREQ_FX. As the

pixel clock frequencies increase beyond 105MHz, a higher divide setting must be used (shown

in Figure10). T o compensate for the higher divide settings, the following changes are made in

xapp_ss_m7d4.v and dcm_clkgen_softspread_m7d4.v.

?Set .CLKFX_DIVIDE(4) for DCM_CLKGEN in dcm_clkgen_softspread_m7d4.v

?Set .SPREADSPECTRUM VIDEO_LINK_M1 for DCM_CLKGEN in

dcm_clkgen_softspread_m7d4.v

?Set .CLKFX_DIVIDE_IN(4) for SSTOP in dcm_clkgen_softspread_m7d4.v

?Set .CLKFBOUT_MULT(4) for PLL_BASE in xapp_ss_m7d4.v

Figure 10:Soft Spread-Spectrum Clocking Video Implementation (F IN>105 MHz) Support of OSERDES2 Within dcm_clkgen_softspread_m7d4.v, after changing CLKFX_DIVIDE to four for

DCM_CLKGEN, the modulation rates slow down. T o compensate, the SPREAD_SPECTRUM

attribute must be set to VIDEO_LINK_M1 to speed up the modulation rate back into an

acceptable range.

Another change to dcm_clkgen_softspread_m7d4.v requires a change to the state

machine. It can be adjusted by changing the parameter CLKFX_DIVIDE_IN=4 within the

instantiation for SSTOP. By setting CLKFX_DIVIDE_IN in the instantiation, the state machines

within sstop.v and sscontrol.v adjust to target the new target frequencies. The reference

design uses CLKFX_MULTIPL Y= 7 and CLKFX_DIVIDE=5 when speeding up the

modulation, and CLKFX_MULTIPL Y=7 and CLKFX_DIVIDE=3 when slowing it down.

In xapp_ss_m7d4.v, because DCM_CLKGEN is sending a 183.75MHz clock frequency, the

original PLL_BASE settings for DIVCLK_DIVIDE and CLKFBOUT_MULT must be increased to

meet the minimum acceptable VCO range, F VCOMIN. Set CLKFBOUT_MULT to 4 while

DIVCLK_DIVIDE remains unchanged.

Spread for Soft Spread-Spectrum Clocking

The soft spread-spectrum state machine controls the range to be used based on a set of

registers. The reference design is setup to create a down-spread spread-spectrum modulation. sstop.v controls the size of the modulation through a series of counters. The size of the modulation is controlled by the variables, SLOW and FAST. The reference design sets FAST =7 and SLOW =5 to create the down-spread modulation. To further increase the spread, SLOW can be decreased (down to 0). As the spread increases, the modulation frequency reduces. Check the spread and modulation frequency for values other than FAST =7 and SLOW =5.

Figure 11 shows the reference design's spread as the input frequencies are varied. However, by ignoring modulation frequencies, Figure 9 shows how spread varies across pixel clock frequencies.

Modulation Frequencies for the SOFT_SS State Machine

When working with a spread-spectrum clock source, the modulation frequency also influences

how the system responds to the modulation of the spread-spectrum clock.

To effectively reduce the emitted noise using a spread-spectrum solution, keep the modulation frequency higher than 20KHz. If the modulation frequency is too low, the spread-spectrum modulation is too slow to efficiently reduce EMI.

When the modulation is too high and with a large spread, spread spectrum modulation could appear as system noise or could start affecting the ability of other PLL components to follow the modulation. The modulation frequency should be less than 120kHz.

When using the SOFT_SS state machine for video applications, a number of factors affect the modulation frequency. The SPREAD_SPECTRUM modulation is not proportional to the input frequencies and requires more analysis to estimate the modulation frequencies. When using the SOFT_SS state machine, modulation frequency becomes dependent on input frequency, CLKFX_MULTIPL Y , CLKFX_DIVIDE, and the SPREAD_SPECTRUM settings

(VIDEO_LINK_M0, VIDEO_LINK_M1, VIDEO_LINK_M2). T o simplify the potential variables,

Figure 11:

Reference Design Spread Across Video Frequencies

use Equation3 to approximate the modulation frequency (F MOD) when using the reference designs.

Equation3 The modulation settings are defined using the equations from T able3 and bounding the modulation frequencies between 20 to 120KHz. For low frequencies, the VIDEO_LINK_M0 speeds up the modulation to keep the modulation frequency above the audio range frequencies. As the input frequency increases, VIDEO_LINK_M1 and VIDEO_LINK_M2 are used to slow down the modulation rates down below 120KHz.

As the input frequency continues to increase to 105MHz, DCM_CLKGEN can no longer support M=7 and D=2. As described in the Example: LVDS for Video Clock Frequencies Beyond 105MHz section, the reference design can be adjusted to support

CLKFX_MULTIPL Y(7) and CLKFX_DIVIDE(4). The increase in CLKFX_DIVIDE causes the modulation frequency to slow down. To compensate, use VIDEO_LINK_M1. The result is the M1_74F MOD in Figure12.

Spread Spectrum Receiving The PLL_BASE or DCM_SP primitives can be used for designs where a spread-spectrum clock is externally created.

Because the DCM_CLKGEN primitive is designed to filter out input clock noise and will distort received spread spectrum clocks, do not use the DCM_CLKGEN primitive with

SPREAD_SPECTRUM=NONE for spread-spectrum clock receiving.

When using the DCM_SP primitive to receive spread-spectrum clocks, it is important to understand how DCM_SP will follow the modulation. To maintain phase and frequency Table 3: Modulation Frequency Calculation

CLKFX_MULTIPLY CLKFX_DIVIDE CONST VIDEO_LINK_M07240.0x10–12 VIDEO_LINK_M17215.0x10–12 VIDEO_LINK_M272 5.0x10–12 VIDEO_LINK_M374 2.5x10

–12

Figure 12:Modulation Frequency vs F IN

F MOD F IN2CONST

×

=

alignment, the DCM must follow the spread-spectrum clock source as shown in Figure 3. To stop distortion on the original spread-spectrum source, DCM_SP must be able to update the deskewing and phase shifting often.

A rough approximation can be made to estimate the limits of the modulation frequency for a given frequency deviation. Beyond these limits, the DCM_SP phase and frequency alignment deteriorates, reducing the receiver's skew margin.

Video display receiver designs require both the DCM's delay-locked loop (DLL) and digital frequency synthesizer (DFS) to be used together. The DLL provides a digital deskew circuit. Equation 4 estimates the maximum modulation frequency (F MDLL expressed in Hz) for a spread-spectrum clock source at any given speed:

Equation 4Where:

F MDLL =Maximum modulation frequency in Hz that the DLL can follow DCM_DELAY_STEP =Finest delay resolution for the DCM(s)S =Maximum spread or frequency deviation T IN =Highest effective input clock period(s)

24=Constant related to the update rate of the DLL frequency and phase adjustments The DFS provides a flexible range of output frequencies based on the ratio of two user-defined integers, a multiplier (CLKFX_MULTIPL Y) and a divisor (CLKFX_DIVIDE). Equation 5 estimates the maximum modulation frequency (F MDFS ) for the DFS portion:

Equation 5

Where:

F MDFS =Maximum Modulation Frequency (Hz) DFS can follow DCM_DELAY_STEP =Finest delay resolution for the DCM(s)M =CLKFX_MULTIPL Y D =CLKFX_DIVIDE

S =Maximum spread or frequency deviation T IN =Highest effective input clock period (s)

2=Constant related to the update rate of DFS frequency and phase adjustments In video applications that use both DFS and DLL, the maximum modulation frequency is determined by Equation 5.

The DCM settings in this section were used during reference design testing. The parameters best represent the 7:1 LVDS designs commonly found in displays: CLKFX_MULTIPL Y =7 and CLKFX_DIVIDE =2. The DCM multiplies the clock to 3.5 times the original frequency. Using the DDR registers provides the full 7x data rate multiplication.

When using spread spectrum clocks, use the fixed phase-shift mode. The variable phase-shift mode disables the internal phase shift controls that update the phase shift with the frequency changes. As a result, variable phase shifting should not be used with spread-spectrum input clocks.

F MDLL DCM_DELAY_STEP

24S ×T IN

2

×-------------------------------------------------------

2M D S ×××T IN

2

×-------------------------------------------------------<

Other Methods of Reducing EMI

Applying the DCM settings from the 7:1 LVDS applications and using Equation4 and

Equation5, limits for a 75MHz spread-spectrum clock can be estimated with a 5% frequency

deviation.

Similarly, other display functions such as PPDS (10:1) or MINI-LVDS (8:1) use other

serialization. The ability of the DCM to track the spread-spectrum signal when multiplying is a

function of the multiply and divide values shown in Equation5. For other display functions, such

as PPDS (M=5, D=1) or MINI-LVDS (M=4, D=1), the modulation frequency threshold is

higher than this 7x example.

Other Methods of Reducing EMI In addition to supporting spread-spectrum clocks, Spartan-6 devices further reduce EMI by controlling the I/O type by selecting a specific SelectIO? interface.

Spartan-6 devices use LVCMOS and LVTTL I/Os with separate slew rate and drive strength attributes. The drive strength can be reduced by lowering DRIVE. The slew rate can be reduced by changed SLEW to SLOW or QUIETIO, which further reduces the ringing.

LCD modules are replacing the noisy LVTTL interfaces with differential interfaces like reduced-swing differential signaling (RSDS), MINI-LVDS, and even point-to-point differential signaling (PPDS). For the lowest EMI, Spartan-6 devices directly drive these differential interfaces.

Reference Design General information about the reference design is shown in Table4. The device utilization is shown in Table5 for both the fixed spread-spectrum and soft spread-spectrum designs.

The reference design files can be downloaded at:

https://https://www.sodocs.net/doc/cd4223387.html,/webreg/clickthrough.do?cid=143697

F MDLL

2310

×12

240.05

×13.3109–

×

()

2

×

--------------------------------------------------------------------108 KHz

=

<

F MDFS

2310

×12

2720.05

·

×

×

×13.3109–

×

()

2

×

------------------------------------------------------------------------------------92.9 KHz

=

=

Table 4: Reference Design Checklist

Developer Name Xilinx

Target devices Spartan-6 FPGAs

Source code provided Y es

Source code format Verilog

Design uses code/IP from an existing reference design,

application note, 3rd party, Core Generator

No

Simulation

Functional simulation performed Requires ISE software

v12.1 or later

Timing simulation performed Requires ISE software

v12.1 or later

Testbench used for functional and timing simulations provided Not applicable

Testbench format Not applicable

Simulator software used MXE

SPICE/IBIS simulations No

Implementation

Conclusion

Conclusion This application note gives examples of a typical spread-spectrum clock for video applications using the Spartan-6 FPGA DCM_CLKGEN primitive. DCM_CLKGEN can be used for fixed

spread-spectrum generation without any logic or in a soft spread-spectrum solution using a

state machine. While the focus is specifically on LVDS display applications, applications with

similar DCM usage can use similar spread-spectrum clocks.

Reference This document references the following Xilinx documentation:

1.DS162, Spartan-6 FPGA Data Sheet

2.UG382, Spartan-6 FPGA Clocking Resources User Guide

3.XAPP469, Spread-Spectrum Clocking Reception for Displays

This application note only applies to Spartan-3E and Extended Spartan-3A family devices.

Additional Resources

The following resources provided additional information useful for working with this application

note and reference design:

4.https://www.sodocs.net/doc/cd4223387.html,, Federal Communications Commission

5.https://www.sodocs.net/doc/cd4223387.html,, American National Standards Institute

6.https://www.sodocs.net/doc/cd4223387.html,/osmhome/international/cispr.html, International Special

Committee on Radio Interference, National Telecommunications and Information

Administration

7.https://www.sodocs.net/doc/cd4223387.html,/appinfo/fpd/, Flat Panel Displays, National Semiconductor

8.https://www.sodocs.net/doc/cd4223387.html,/engnotes/eng290.htm, Engineering Note 290: Comparison of FCC

Limits with CISPR Limits, Communication Certification Laboratory

Revision History The following table shows the revision history for this document.

Synthesis software tools used XST 11.4 Implementation software tools used ISE v11.4 software

Static timing analysis performed Y es

Hardware verified Y es

Hardware platform used for verification SP601

Table 5: Device Utilization

Fixed Spread-Spectrum

Design

Soft Spread-Spectrum

Design

DCM_CLKGENs used11

BUFGs used02

Slice LUT Flip-Flop pairs used099

Table 4: Reference Design Checklist (Cont’d)

Date Version Description of Revisions

03/22/10 1.0Initial Xilinx release.

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