NTE3094中文资料

NTE3094

Optoisolator

Dual, High Speed, Open Collector NAND Gate

Description:

The NTE3094 consists of a pair of inverting optically coupled gates each with a GaAsP emitting diode and a unique integrated detector. The photons are collected in the detector by a photodiode and then amplified by a high gain linear amplifier that drives a Schottky clamped open collector output transis-tor. each circuit is temperature, current and voltage compensated.

This unique isolator design provides maximum DC and AC circuit isolation between input and output while achieving LSTTL/TTL circuit compatibility. The isolator operational parameters are guaranteed from 0° to +70°C, such that a minimum input current of 5mA will sink an eight gate fan–out (13mA) at the output with 5 volt V CC applied to the detector. This isolation and coupling is achieved with a typical propagation delay of 57ns.

Features:

D LSTTL/TTL Compatible: 5V Supply

D Ultra High Speed

D Low Input Current Required

D High Common Mode Rejection

D3000V DC Withstand Test Voltage

D Typical Data Rate 10M/Bit(s)

Absolute Maximum Ratings: (T A = +25°C unless otherwise specified)

Input Diode (Each Channel)

Reverse Voltage, V R5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Forward Current, I F

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Average15mA

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Peak (≤ 1ms Duration)30mA Output Transistor (Each Channel)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Voltage (1 Minute Maximum), V CC7V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Voltage, V O7V Output Current, I O16mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Collector Power Dissipation, P D60mW

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Total Device

Operating Temperature Range, T opr0° to +70°C

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Storage Temperature Range, T stg–55° to +125°C Lead Temperature (During Soldering, 1.6mm below seating plane, 10sec Max), T L+260°C

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Recommended Operating Conditions:

Note 1.6.3mA condition permits at least 20% CTR degradation guardband. Initial switching threshold is 5mA or less.

Electrical Characteristics: (T = 0° to +70°C, Note 2 unless otherwise specified)

Note 2.All typicals at T A = +25°C, V CC = 5V unless otherwise specified.

Note 3.Each channel.

Note 4.Measured between Pin1, Pin2, Pin3 and Pin4 shorted together and Pin5, Pin6, Pin7 and Pin8 shorted together.

Note 5.At 10mA, V F decreases with increasing temperature at the rate of 1.6mV/°C.

Note 6.DC Current Transfer Ratio is defined as the ratio of the output collector current to the forward bias input current times 100%.

Note7.Measured between Pin1 and Pin2 shorted together and Pin3 and Pin4 shorted together.

Switching Characteristics: (T

= +25°C, V = 5V unless otherwise specified)

Note 3.Each channel.

Note 8.The t PLH propagation delay is measured from the 3.75mA point on the trailing edge of the

input pulse to the 1.5V point on the trailing edge of the output pulse.

Note 9.The t PHL propagation delay is measured from the 3.75mA point on the leading edge of the

input pulse to the 1.5V point on the leading edge of the output pulse.

https://www.sodocs.net/doc/c717370840.html,mon mode transient immunity in Logic High level is the maximum tolerable (positive)

dv cm/dt on the leading edge of the common mode pulse (V CM ) to assure that the output will remain in a Logic High state (i.e. V O 2.0V). Common mode transient immunity in Logic Low level is the maximum tolerable (negative) dc cm/dt on the trailing edge of the common mode pulse signal (V CM ) to assure that the output will remain in a Logic Low state (i.e. V O 0.8V).