FT245R中文资料
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Future Technology Devices International Ltd.
FT245R USB FIFO I.C.
Incorporating FTDIChip-ID? Security Dongle
The FT245R is the latest device to be added to FTDI’s range of USB FIFO interface Integrated Circuit Devices.
The FT245R is a USB to parallel FIFO interface, with the new FTDIChip-ID? security dongle feature. In addition, asynchronous and synchronous bit bang interface modes are available. USB to parallel designs using the FT245R have been further simpli?ed by fully integrating the external EEPROM, clock circuit and USB resistors onto the device.
The FT245R adds a new function compared with its predecessors, effectively making it a “2-in-1” chip for some application areas. A unique number (the FTDIChip-ID?) is burnt into the device during manufacture and is readable over USB, thus forming the basis of a security dongle which can be used to protect customer application software from being copied.
The FT245R is available in Pb-free (RoHS compliant) compact 28-Lead SSOP and QFN-32 packages.
Copyright ? Future Technology Devices International Ltd. 2005
? Single chip USB to parallel FIFO bidirectional data transfer interface.
? Entire USB protocol handled on the chip - No USB-speci?c ?rmware programming required.
? Simple interface to MCU / PLD / FPGA logic with simple 4-wire handshake interface.
? Data transfer rate to 1 Megabyte / second - D2XX Direct Drivers.
? Data transfer rate to 300 kilobyte / second - VCP Drivers.
? 256 byte receive buffer and 128 byte transmit buffer utilising buffer smoothing technology to allow
for high data throughput.
? FTDI’s royalty-free VCP and D2XX drivers
eliminate the requirement for USB driver
development in most cases.
? New USB FTDIChip-ID? feature.
? FIFO receive and transmit buffers for high data throughput.
? Adjustable receive buffer timeout.
? Synchronous and asynchronous bit bang mode interface options with RD# and WR# strobes allow
the data bus to be used as a general purpose I/O
port.
? Integrated 1024 Bit internal EEPROM for storing USB VID, PID, serial number and product
description strings.
? Device supplied preprogrammed with unique USB serial number.? Support for USB suspend / resume through PWREN# pin and Wake Up pin function.
? In-built support for event characters.
? Support for bus powered, self powered, and high-power bus powered USB con?gurations.
? Integrated 3.3V level converter for USB I/O .
? Integrated level converter on FIFO interface and control pins for interfacing to 5V - 1.8V Logic.
? True 5V / 3.3V / 2.8V / 1.8V CMOS drive output and TTL input.
? High I/O pin output drive option.
? Integrated USB resistors.
? Integrated power-on-reset circuit.
? Fully integrated clock - no external crystal,
oscillator, or resonator required.
? Fully integrated AVCC supply ?ltering - No separate AVCC pin and no external R-C ?lter required.
? USB bulk transfer mode.
? 3.3V to 5.25V Single Supply Operation.
? Low operating and USB suspend current.
? Low USB bandwidth consumption.
? UHCI / OHCI / EHCI host controller compatible
? USB 2.0 Full Speed compatible.
? -40°C to 85°C extended operating temperature range.
? Available in compact Pb-free 28 Pin SSOP and QFN-32 packages (both RoHS compliant).
1. Features
1.1 Hardware Features
Royalty-Free VIRTUAL COM PORT
(VCP) DRIVERS for...
?Windows 98, 98SE, ME, 2000, Server 2003, XP.?Windows Vista / Longhorn*
?Windows XP 64-bit.*
?Windows XP Embedded.
?Windows https://www.sodocs.net/doc/c018778734.html, 4.2 & 5.0
?MAC OS 8 / 9, OS-X
?Linux 2.4 and greater Royalty-Free D2XX Direct Drivers
(USB Drivers + DLL S/W Interface)
?Windows 98, 98SE, ME, 2000, Server 2003, XP.?Windows Vista / Longhorn*
?Windows XP 64-bit.*
?Windows XP Embedded.
?Windows https://www.sodocs.net/doc/c018778734.html, 4.2 & 5.0
?Linux 2.4 and greater
1.2 Driver Support
The drivers listed above are all available to download for free from the FTDI website. Various 3rd Party Drivers are also available for various other operating systems - see the FTDI website for details.
* Currently Under Development. Contact FTDI for availability.
?Upgrading Legacy Peripherals to USB
?Cellular and Cordless Phone USB data transfer cables and interfaces
?Interfacing MCU / PLD / FPGA based designs to USB
?USB Audio and Low Bandwidth Video data transfer ?PDA to USB data transfer
?USB Smart Card Readers
?USB Instrumentation
?USB Industrial Control ?USB MP3 Player Interface
?USB FLASH Card Reader / Writers
?Set Top Box PC - USB interface
?USB Digital Camera Interface
?USB Hardware Modems
?USB Wireless Modems
?USB Bar Code Readers
?USB Software / Hardware Encryption Dongles
1.3 Typical Applications
2. Enhancements
2.1 Device Enhancements and Key Features
This section summarises the enhancements and the key features of the FT245R device. For further details, consult the device pin-out description and functional description sections.
Integrated Clock Circuit - Previous generations of FTDI’s USB to parallel FIFO interface devices required an external crystal or ceramic resonator. The clock circuit has now been integrated onto the device meaning that no crystal or ceramic resonator is required. However, if required, an external 12MHz crystal can be used as the clock source.
Integrated EEPROM - Previous generations of FTDI’s USB to parallel FIFO interface devices required an external EEPROM if the device were to use USB Vendor ID (VID), Product ID (PID), serial number and product description strings other than the default values in the device itself. This external EEPROM has now been integrated onto the
FT245R chip meaning that all designs have the option to change the product description strings. A user area of the internal EEPROM is available for storing additional data. The internal EEPROM is programmable in circuit, over USB without any additional voltage requirement.
Preprogrammed EEPROM - The FT245R is supplied with its internal EEPROM preprogrammed with a serial number which is unique to each individual device. This, in most cases, will remove the need to program the device EEPROM. Integrated USB Resistors - Previous generations of FTDI’s USB to parallel FIFO interface devices required two external series resistors on the USBDP and USBDM lines, and a 1.5 kΩ pull up resistor on USBDP. These three resistors have now been integrated onto the device.
Integrated AVCC Filtering - Previous generations of FTDI’s USB to parallel FIFO interface devices had a separate AVCC pin - the supply to the internal PLL. This pin required an external R-C ?lter. The separate AVCC pin is now connected internally to VCC, and the ?lter has now been integrated onto the chip.
Less External Components - Integration of the crystal, EEPROM, USB resistors, and AVCC ?lter will substantially reduce the bill of materials cost for USB interface designs using the FT245R compared to its FT245BM predecessor. Transmit and Receive Buffer Smoothing - The FT245R’s 256 byte receive buffer and 128 byte transmit buffer utilise new buffer smoothing technology to allow for high data throughput.
Enhanced Asynchronous Bit Bang Mode with RD# and WR# Strobes - The FT245R supports FTDI’s BM chip bit bang mode. In bit bang mode, the eight parallel FIFO data bus lines can be switched from the regular interface mode to an 8-bit general purpose I/O port. Data packets can be sent to the device and they will be sequentially sent to the interface at a rate controlled by an internal timer (equivalent to the baud rate prescaler). With the FT245R device this mode has been enhanced so that the internal RD# and WR# strobes are now brought out of the device which can be used to allow external logic to be clocked by accesses to the bit bang I/O bus. This option will be described more fully in a separate application note
Synchronous Bit Bang Mode - Synchronous bit bang mode differs from asynchronous bit bang mode in that the interface pins are only read when the device is written to. Thus making it easier for the controlling program to measure the response to an output stimulus as the data returned is synchronous to the output data. The feature was previously seen in FTDI’s FT2232C device. This option will be described more fully in a separate application note.
Lower Supply Voltage - Previous generations of the chip required 5V supply on the VCC pin. The FT245R will work with a Vcc supply in the range 3.3V - 5V. Bus powered designs would still take their supply from the 5V on the USB bus, but for self powered designs where only 3.3V is available, and there is no 5V supply, there is no longer any need for an additional external regulator.
Integrated Level Converter on FIFO Interface and Control Signals - VCCIO pin supply can be from 1.8V to 5V. Connecting the VCCIO pin to 1.8V, 2.8V, or 3.3V allows the device to directly interface to 1.8V, 2.8V or 3.3V and other logic families without the need for external level converter I.C.s
5V / 3.3V / 2.8V / 1.8V Logic Interface - The FT245R provides true CMOS Drive Outputs and TTL level Inputs.
Integrated Power-On-Reset (POR) Circuit- The device incorporates an internal POR function. A RESET# pin is available in order to allow external logic to reset the FT245R where required. However, for many applications the RESET# pin can be left unconnected, or pulled up to VCCIO.
Wake Up Function - If USB is in suspend mode, and remote wake up has been enabled in the internal EEPROM (it is enabled by default), the RXF# pin becomes an input. Strobing this pin low will cause the FT245R to request a resume from suspend on the USB bus. Normally this can be used to wake up the host PC from suspend
Lower Operating and Suspend Current - The device operating supply current has been further reduced to 15mA, and the suspend current has been reduced to around 70μA. This allows a greater margin for peripherals to meet the USB suspend current limit of 500μA.
Low USB Bandwidth Consumption - The operation of the USB interface to the FT245R has been designed to use as little as possible of the total USB bandwidth available from the USB host controller.
High Output Drive Option - The parallel FIFO interface and the four FIFO handshake pins can be made to drive
out at three times the standard signal drive level thus allowing multiple devices to be driven, or devices that require a greater signal drive strength to be interfaced to the FT245R. This option is con?gured in the internal EEPROM. Power Management Control for USB Bus Powered, High Current Designs- The PWREN# signal can be used to directly drive a transistor or P-Channel MOSFET in applications where power switching of external circuitry is required. An option in the internal EEPROM makes the device gently pull down on its FIFO interface lines when the power
is shut off (PWREN# is high). In this mode any residual voltage on external circuitry is bled to GND when power is removed, thus ensuring that external circuitry controlled by PWREN# resets reliably when power is restored. FTDIChip-ID? - Each FT245R is assigned a unique number which is burnt into the device at manufacture. This ID number cannot be reprogrammed by product manufacturers or end-users. This allows the possibility of using FT245R based dongles for software licensing. Further to this, a renewable license scheme can be implemented based on the FTDIChip-ID? number when encrypted with other information. This encrypted number can be stored in the user area of the FT245R internal EEPROM, and can be decrypted, then compared with the protected FTDIChip-ID? to verify that a license is valid. Web based applications can be used to maintain product licensing this way. An application note describing this feature is available separately from the FTDI website.
Improved EMI Performance - The reduced operating current and improved on-chip VCC decoupling signi?cantly improves the ease of PCB design requirements in order to meet FCC, CE and other EMI related speci?cations. Programmable FIFO TX Buffer Timeout - The FIFO TX buffer timeout is used to ?ush remaining data from the receive buffer. This timeout defaults to 16ms, but is programmable over USB in 1ms increments from 1ms to 255ms, thus allowing the device to be optimised for protocols that require fast response times from short data packets. Extended Operating Temperature Range - The FT232R operates over an extended temperature range of -40o to
+85o C thus allowing the device to be used in automotive and industrial applications.
New Package Options - The FT245R is available in two packages - a compact 28 pin SSOP ( FT245RL) and an ultra-compact 5mm x 5mm pinless QFN-32 package ( FT245RQ). Both packages are lead ( Pb ) free, and use a
‘green’ compound. Both packages are fully compliant with European Union directive 2002/95/EC.
3. Block Diagram
3.1 Block Diagram (Simpli?ed)
Figure 1 - FT245R Block Diagram
3.2 Functional Block Descriptions
3.3V LDO Regulator - The 3.3V LDO Regulator generates the 3.3V reference voltage for driving the USB transceiver cell output buffers. It requires an external decoupling capacitor to be attached to the 3V3OUT regulator output pin. It also provides 3.3V power to the 1.5kΩ internal pull up resistor on USBDP . The main function of this block is to power the USB Transceiver and the Reset Generator Cells, rather than to power external logic. However, external circuitry requiring 3.3V nominal at a current of around 50mA could also draw its power from the 3V3OUT pin if https://www.sodocs.net/doc/c018778734.html,B Transceiver - The USB Transceiver Cell provides the USB 1.1 / USB 2.0 full-speed physical interface to the USB cable. The output drivers provide 3.3V level slew rate control signalling, whilst a differential receiver and two single ended receivers provide USB data in, SEO and USB Reset condition detection. This Cell also incorporates internal USB series resistors on the USB data lines, and a 1.5kΩ pull up resistor on USBDP .
USB DPLL - The USB DPLL cell locks on to the incoming NRZI USB data and provides separate recovered clock and data signals to the SIE block.
Internal 12MHz Oscillator - The Internal 12MHz Oscillator cell generates a 12MHz reference clock input to the x4 Clock multiplier. The 12MHz Oscillator is also used as the reference clock for the SIE, USB Protocol Engine and FIFO controller blocks
Clock Multiplier - The Clock Multiplier takes the 12MHz input from the Oscillator Cell and generates the 48MHz clock reference used for the USB DPLL block.
Serial Interface Engine (SIE) - The Serial Interface Engine (SIE) block performs the Parallel to Serial and Serial to Parallel conversion of the USB data. In accordance to the USB 2.0 speci?cation, it performs bit stuf?ng / un-stuf?ng and CRC5 / CRC16 generation / checking on the USB data stream.
OCSI VCC
D0D1D2D3D4D5D6D7RD#RXF#TXE#
TEST GND
WR
USB Protocol Engine - The USB Protocol Engine manages the data stream from the device USB control endpoint. It handles the low level USB protocol (Chapter 9) requests generated by the USB host controller and the commands for controlling the functional parameters of the FIFO.
FIFO TX Buffer (128 byte) - Data written into the FIFO using the WR pin is stored in the FIFO TX (transmit) Buffer. The USB host controller removes data from the FIFO TX Buffer by sending a USB request for data from the device data In endpoint.
FIFO RX Buffer (256 byte) - Data sent from the USB host controller to the FIFO via the USB data Out endpoint is stored in the FIFO RX (receive) buffer and is removed from the buffer by reading the contents of the FIFO using the RD# pin.
FIFO Controller - The FIFO controller handles the transfer of data between the external FIFO interface pins (D0 - D7) and the FIFO transmit and receive buffers. A new feature, which is enabled in the internal EEPROM allows high signal drive strength on the FIFO parallel data bus and handshake control pins.
RESET Generator - The integrated Reset Generator Cell provides a reliable power-on reset to the device internal circuitry on power up. A RESET# input is provided to allow other devices to reset the FT245R. RESET# can be tied
to VCCIO or left unconnected, unless there is a requirement to reset the FT245R device from external logic or an external reset generator I.C.
Internal EEPROM - The internal EEPROM in the FT245R can be used to store USB Vendor ID (VID), Product ID (PID), device serial number, product description string, and various other USB con?guration descriptors. The device is supplied with the internal EEPROM settings preprogrammed as described in Section 10.
4. Device Pin Out and Signal Descriptions
4.128-LD SSOP Package
Figure 2 - 28 Pin SSOP Package Pin Out
Figure 3 - 28 Pin SSOP Package Pin Out (Schematic Symbol)
4.2 SSOP-28 Package Signal Descriptions
*Contact FTDI Support for details of how to use an external crystal, ceramic resonator, or oscillator with the FT245R.
** When used in Input Mode, these pins are pulled to VCCIO via internal 200k? resistors. These can be programmed to gently pull low during USB suspend ( PWREN# = “1” ) by setting this option in the internal EEPROM.
4.3 QFN-32 Package
Figure 4 - QFN-32 Package Pin Out
Figure 5 - QFN-32 Package Pin Out (Schematic Symbol)
24
17
16
9
8
1
USBDP
USBDM
3V3OUT
RESET#
VCC NC AGND
TEST
OSCI
OSCO
TXE#RXF#D0
D2
D1D4
VCCIO D7GND NC D5D6D3
PWREN#
RD#
WR
GND
GND NC
NC
NC
NC
TOP
BOTTOM
4.4 QFN-32 Package Signal Descriptions
*Contact FTDI Support for details of how to use an external crystal, ceramic resonator, or oscillator with the FT245R. ** When used in Input Mode, these pins are pulled to VCCIO via internal 200k? resistors. These can be programmed to gently pull low during USB suspend ( PWREN# = “1” ) by setting this option in the internal EEPROM.
4.5 FT245R FIFO Timing Diagrams Figure 6 - FIFO Read Cycle
RD#
D[7...0]
* Load = 30pF
Figure 7 - FIFO Write Cycle
TXE#
WR
5. Package Parameters
The FT245R is supplied in two different packages. The FT245RL is the SSOP-28 option and the FT245RQ is the QFN-32 package option. The solder re?ow pro?le for both packages is described in Section 5.3.
5.1 SSOP-28 Package Dimensions
Figure 8 - SSOP-28 Package Dimensions
The FT245RL is supplied in a RoHS compliant 28 pin SSOP package. The package is lead ( Pb ) free and uses a
‘green’ compound. The package is fully compliant with European Union directive 2002/95/EC.
This package has a 5.30mm x 10.20mm body ( 7.80mm x 10.20mm including pins ). The pins are on a 0.65 mm pitch. The above mechanical drawing shows the SSOP-28 package – all dimensions are in millimetres.
The date code format is YYXX where XX = 2 digit week number, YY = 2 digit year number.
5.2QFN-32 Package Dimensions
Figure 9 - QFN-32 Package Dimensions
The FT245RQ is supplied in a RoHS compliant leadless QFN-32 package. The package is lead ( Pb ) free, and uses a ‘green’ compound. The package is fully compliant with European Union directive 2002/95/EC.
This package has a compact 5.00mm x 5.00mm body. The solder pads are on a 0.50mm pitch. The above mechanical drawing shows the QFN-32 package – all dimensions are in millimetres.
The centre pad on the base of the FT245RQ is not internally connected, and can be left unconnected, or connected to ground (recommended).
The date code format is YYXX where XX = 2 digit week number, YY = 2 digit year number.
5.3 QFN-32 Package Typical Pad Layout
Figure 10 - Typical Pad Layout for QFN-32 Package
5.4 QFN-32 Package Typical Solder Paste Diagram
Top View
Figure 11 - Typical Solder Paste Diagram for QFN-32 Package
+/-0.050
+/-0.050
5.5 Solder Re?ow Pro?le
T e m p e r a t u r e , T (D e g r e e s C )
p The recommended values for the solder re?ow pro?le are detailed in Table 5. Values are shown for both a completely Pb free solder process (i.e. the FT245R is used with Pb free solder), and for a non-Pb free solder process (i.e. the FT245R is used with non-Pb free solder).The FT245R is supplied in Pb free 28 LD SSOP and QFN-32 packages. The recommended solder re?ow pro?le for both package options is shown in Figure 12.
6. Device Characteristics and Ratings
6.1 Absolute Maximum Ratings
The absolute maximum ratings for the FT245R devices are as follows. These are in accordance with the Absolute Maximum Rating System (IEC 60134). Exceeding these may cause permanent damage to the device.
* If devices are stored out of the packaging beyond this time limit the devices should be baked before use. The devices should be ramped up to a temperature of 125°C and baked for up to 17 hours.
6.2 DC Characteristics
DC Characteristics ( Ambient Temperature = -40o C to +85o C )
**Inputs have an internal 200k? pull-up resistor to VCCIO.
***Driver Output Impedance includes the internal USB series resistors on USBDP and USBDM pins.
6.3 EEPROM Reliability Characteristics
The internal 1024 Bit EEPROM has the following reliability characteristics-
6.4 Internal Clock Characteristics
The internal Clock Oscillator has the following characteristics.
***Equivalent to +/-1667ppm.
****When supplied the device is con?gured to use its internal clock oscillator. Users who wish to use an external oscillator or crystal should contact FTDI technical support.
7. Device Con?gurations
Please note that pin numbers on the FT245R chip in this section have deliberately been left out as they vary between the FT245RL and FT245RQ versions of the device. All of these con?gurations apply to both package options for the FT245R device. Please refer to Section 4 for the package option pin-out and signal descriptions.
7.1 Bus Powered Con?guration
Figure 13 illustrates the FT245R in a typical USB bus powered design con?guration. A USB Bus Powered device gets its power from the USB bus. Basic rules for USB Bus power devices are as follows –
i) On plug-in to USB, the device must draw no more than 100mA.
ii) On USB Suspend the device must draw no more than 500μA.
iii) A Bus Powered High Power USB Device (one that draws more than 100mA) should use the PWREN# pin to keep the current below 100mA on plug-in and 500μA on USB suspend.
iv) A device that consumes more than 100mA can not be plugged into a USB Bus Powered Hub
v) No device can draw more that 500mA from the USB Bus.
The power descriptor in the internal EEPROM should be programmed to match the current draw of the device.
A Ferrite Bead is connected in series with US
B power to prevent noise from the device and associated circuitry (EMI) being radiated down the USB cable to the Host. The value of the Ferrite Bead depends on the total current required by the circuit – a suitable range of Ferrite Beads is available from Steward (https://www.sodocs.net/doc/c018778734.html,) for example Steward Part # MI0805K400R-00.
7.2 Self Powered Con?guration
Figure 14 illustrates the FT245R in a typical USB self powered con?guration. A USB Self Powered device gets its power from its own power supply and does not draw current from the USB bus. The basic rules for USB Self power devices are as follows –
i) A Self Powered device should not force current down the USB bus when the USB Host or Hub Controller is
powered down.
ii) A Self Powered Device can use as much current as it likes during normal operation and USB suspend as it has its own power supply.
iii) A Self Powered Device can be used with any USB Host and both Bus and Self Powered USB Hubs
The power descriptor in the internal EEPROM should be programmed to a value of zero (self powered).
In order to meet requirement (i) the USB Bus Power is used to control the RESET# Pin of the FT245R device. When the USB Host or Hub is powered up the internal 1.5kΩ resistor on USBDP is pulled up to 3.3V, thus identifying the device as a full speed device to USB. When the USB Host or Hub power is off, RESET# will go low and the device will be held in reset. As RESET# is low, the internal 1.5kΩ resistor will not be pulled up to 3.3V, so no current will be forced down USBDP via the 1.5kΩ pull-up resistor when the host or hub is powered down. Failure to do this may cause some USB host or hub controllers to power up erratically.
Figure 10 illustrates a self powered design which has a 3.3V - 5V supply. A design which is interfacing to 2.8V - 1.8V logic would have a 2.8V - 1.8V supply to VCCIO, and a 3.3V - 5V supply to VCC
Note : When the FT245R is in reset, the FIFO interface and control pins all go tri-state. These pins have internal
200kΩ pull-up resistors to VCCIO, so they will gently pull high unless driven by some external logic.