GL85X Design Guide(E)_201
Genesys Logic, Inc.
USB 2.0 High-Speed HUB Controller Design Guide
Revision 2.01 Oct. 14, 2010
USB 2.0 Hub Design Guide
Copyright
Copyright ? 2010 Genesys Logic, Inc. All rights reserved. No part of the materials shall be reproduced in any form or by any means without prior written consent of Genesys Logic, Inc.
Ownership and Title
Genesys Logic, Inc. owns and retains of its right, title and interest in and to all materials provided herein. Genesys Logic, Inc. reserves all rights, including, but not limited to, all patent rights, trademarks, copyrights and any other propriety rights. No license is granted hereunder.
Disclaimer
All Materials are provided “as is”. Genesys Logic, Inc. makes no warranties, express, implied or otherwise, regarding their accuracy, merchantability, fitness for any particular purpose, and non-infringement of intellectual property. In no event shall Genesys Logic, Inc. be liable for any damages, including, without limitation, any direct, indirect, consequential, or incidental damages. The materials may contain errors or omissions. Genesys Logic, Inc. may make changes to the materials or to the products described herein at anytime without notice.
Genesys Logic, Inc.
12F, No. 205, Sec. 3, Beishin Rd., Shindian City, Taipei, Taiwan Tel : (886-2) 8913-1888 Fax : (886-2) 6629-6168 http ://https://www.sodocs.net/doc/da1584458.html,
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USB 2.0 Hub Design Guide
Revision History
Revision 1.00 1.10 1.11 1.12 1.50 1.60 1.70 1.80 Date 07/03/2003 10/29/2003 03/23/2004 02/22/2005 07/13/2005 11/13/2006 11/29/2006 08/31/2009 First formal release Change large contents in Ch1 ~ Ch6 Add notice item 7 in Ch6 Add GL850A Add GL852, remove GL850 Modify X’tal. Modify Figure3 Modify 2.1, 2.3, p.6-7 Add 2.4, 2.5, p.7-8 Modify Ch4, Ch5, p.11-12 Modify 2.1, p.6 Add 2.6, p.9 Modify Ch5, p.13 Add 5.6, p.13 Modify 5.6, p.13 Description
1.90 2.00 2.01
12/17/2009 01/26/2010 10/14/2010
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USB 2.0 Hub Design Guide
Table of Contents
1. PREFACE ............................................................................................................................. 5 2. GENERAL OF THE USB2.0 HIGH SPEED SIGNAL ALLOCATION........................ 6 2.1 Circuitry Routing and Component Placement of the 4-Layer PCB......................... 6 2.2 Routing and Placing of Components on 2-Layer PCB............................................... 7 2.3 Layout of D+, D- ............................................................................................................ 7 2.4 The Completeness of GND............................................................................................ 8 2.5 Power Trace ................................................................................................................... 8 2.6 Crystal Routing and Placement ................................................................................... 9 3. LAYOUT DIAGRAM........................................................................................................ 10 3.1 Single Side Placement.................................................................................................. 10 3.2 Placement on the Both Sides....................................................................................... 11 3.3 Differential Signal Source Traces (D+, D-) ............................................................... 11 4. GROUNDING AND POWER LAYOUT......................................................................... 12 5. SPECIAL NOTES .............................................................................................................. 13
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USB 2.0 Hub Design Guide
1. PREFACE
The purpose of this document is to provide suggestions and descriptions for the design of PCB layout about USB 2.0 High-Speed Hub Controller of Genesys Logic Inc., so that the client can verify in the shortest time and start mass production.
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USB 2.0 Hub Design Guide
2. GENERAL OF THE USB2.0 HIGH SPEED SIGNAL ALLOCATION
2.1 Circuitry Routing and Component Placement of the 4-Layer PCB
1. Use 4-layer PCB: 1st Layer for component placement and signal layout, 2nd Layer: GND, 3rd Layer: Power, and 4th Layer: layout of signal lines. Layer Layer 1 Layer 2 Layer 3 Layer 4 Description Signal Layer 1 Ground Power Signal Layer 2
Routing of USB2.0 D+/D- data signal shall be on Signal layer 1 2. Firstly place X’tal and D+ & D- write; they must be of equal length, parallel and equal spacing. 3. No wire is allowed underneath the X’tal. X’tal is to be as near the IC as possible. The maximum suggested distance between X’tal trace and the IC is 1cm. 4. Both sides of X’tal IN/OUT leads shall be enveloped by GND to avoid noise interference. (Fig. 3.2) 5. Enlarge the Power Trace of upstream port and downstream port to at least 50 mil. If punch-through hole is required to connect the pack face, use multiple holes to avoid voltage drop. Take special attention on this, for voltage drop is verified at USB-IF Logo certification. Unsteady voltage causes signal to jitter severely and thus failure of compatibility test. 6. All wires shall not have 90-degree turns. If such turns are inevitable, make an arc or double 45° to replace them, see Fig. 2.1. It will help to minimize the EMI problems.
Figure 2.1
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USB 2.0 Hub Design Guide
7. Forbid any Power Trace or Clock Line to pass underneath a Chip. 8. All Beads are to be placed as near to the USB connector as possible. 9. All bypass and electrolytic capacitors are to be placed as near the IC as possible. 10. All coupling capacitors of D+/D- shall be placed as near the IC as possible. 11. Avoid punch-through holes at: D+, D-, X1 and X2. A punch-through hole may cause variation of signal line impedance, and distortion of signal in severe case. If it is inevitable to make such holes, the waveform will be inferior to that without the holes. The client shall make their own decision.
2.2 Routing and Placing of Components on 2-Layer PCB
1. Using 2-layer PCB: GL provides 2-layer Demo Boards presently, of which the layout principle is similar to 4-layer boards as described above. 2. When using a 2-layer board, GND shall be paved on the back of D+/D- signal lines so as to lower trace impedance of the D+/D- signal line and stabilize the signal.
2.3 Layout of D+, D1. Keep away from the X’tal, keep in the same layer as possibly can, make minimum turns and take shorted length to the USB connector. 2. Wires for D+, D- shall be parallel and guarded by GND. 3. Beware of stubs on HS signals. (Resister and capacitors shall be mounted directly on the wires.) 4. Wiring diagram of D+, D- (90 Ohm impedance) is as Fig. 2.2: This is a reference diagram of 4-layer PCB with a 1.6 mm thick; trace for the 2-layer PCB shall have the same values. Mind the width of D+/D- Tracing and the spacing between them; get PCB thickness from the manufacturer so as to verify the PCB Impedance if it meets with 90 ±10% . If the PCB manufacturer provides TDR measurement, it helps control the PCB Impedance. The GND of the signal lines shall have spacing of at least 20mil with the signal lines. The width and spacing of the D+/D- tracing shall be the same and approximate the spacing (W approximate S). (Fig. 2.2)
Figure 2.2
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USB 2.0 Hub Design Guide 2.4 The Completeness of GND
Keep GND plane with no interruptions when routing power traces.
Power (Bottom) GND Plane (Bottom) DP/DM (Top)
X
Figure 2.3
2.5 Power Trace
Keep the PCB power trace connected to the internal 5 to 3.3V regulator as short as possible in order to prevent the interference between other signal lines and power trace. It will help to minimize EMI problem.
3.3Vout 5Vin
Figure 2.4
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USB 2.0 Hub Design Guide 2.6 Crystal Routing and Placement
1. Keep the distance between X’tal and the IC less then 1cm to avoid triggering high frequency oscillation on PCB. 2. If over 1cm is unavoidable in the design, place the capacitors and the resistor as close as possible to the IC. Recommend less than 1cm if possible. And the resistor need be between the IC and the capacitor. See Figure2.5.
Figure 2.5
3. Do not route X1 and X2 underneath the IC. In this case, it may cause noise on PCB and will trigger high frequency oscillation.
Figure 2.6
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USB 2.0 Hub Design Guide
3. LAYOUT DIAGRAM
3.1 Single Side Placement
Figure 3.1
1. In single sided placement, layout the 0.1μF bypass capacitor nearest to the chip. 2. Trace the D+, D- in priority, with the resister nearest to the chip (Fig. 3.1). 3. Better EMI effect can be attained by a one-piece GND underneath the IC furnished with PTH holes to enlarge the GND area (as shown in Fig. 3.1). 4. The X’tal (oscillator) traces shall be surrounded by GND to prevent interference to other signal wires (as shown in Fig. 3.1). The X’tal traces shall be symmetrical and parallel in order to get better oscillation wave form and better EMI protection (as shown in Fig. 3.2).
Figure 3.2
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USB 2.0 Hub Design Guide 3.2 Placement on the Both Sides
For placement on the both sides, place the 0.1μF bypass capacitor to the opposite side of the IC as shown in Fig. 3.3.
Figure 3.3
3.3 Differential Signal Source Traces (D+, D-)
USB signal traces shall be placed parallel as in Fig. 3.4, not as in Fig. 3.5.
Figure 3.4
Figure 3.5
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USB 2.0 Hub Design Guide
4. GROUNDING AND POWER LAYOUT
Proper design of grounding cleans up signal by effectively draining the noises, it also saves testing time and lowers production cost, and, it does not affect the product’s function. 1. Distribute Power and GND in grids. 2. Make power plane smaller than ground area. 3. Use multi-place GND (as in Fig. 4.1), fill empty space with GND. Make ground area as large and as large and integrated as possible.
Figure 4.1
4. Reserve Ferrite Beads for the Shielding GND of USB connectors. 5. Beads shall be added before connecting the Power and GND to an IC. 6. A shielding band, 1/2” on the peripheral of the upper and lower layers, shall be provided and connected to the Shielding GND. 7. Digital GND and Analog GND can be placed together in one-piece so as to enlarge the GND, and thus helping dissipation of noises. 8. Digital Power and Analog Power shall be handled separately with different blocks to supply power to IC chip and peripheral components; a bead shall be connected in-between to isolate the noise source.
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USB 2.0 Hub Design Guide
5. SPECIAL NOTES
1. GL85X is relatively sensitive to Power Noise interference, and therefore an extra 1μF needs to be added on the PLL AVDD power source (Refer to the reference schematic). And remember to place it as near to the IC outlet as possible. 2. For Analog Power to work in a clean environment, add a large bypass capacitor 0.1μF and electrolytic capacitor 10μF in parallel on Input and Output of the 5V->3.3V regulator to ensure the stability. 3. 50ppm precision class is recommended for the X’tal. 4. When using internal regulator, suggest enlarging the GND area underneath the IC as big as possible to prevent thermal problem. 5. The suggested resistance value of Rreff is 680 ohm ±1%. Caution: a wrong value for the Rreff resister will directly affect signal quality. 6. To prevent EMI problems, for GL850G/GL852G, suggest adding one BEAD on pin34/pin38/pin39 of LQFP48, pin16/pin18 of SSOP28, pin21/pin23 of QFN28. For GL854G, suggest adding one BEAD on pin47/pin53/pin54. Besides, reserve commmon choke on every D+/D- path can aslo help prevent EMI problems. Remember to place the BEAD or common choke as near to the IC outlet as possible.
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