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【Maydell】【20th EUPVSEC 2005】BASIC ELECTRONIC PROPERTIES AND TECHNOLOGY OF TCO_a-SiH(n)_c-Si(p)

BASIC ELECTRONIC PROPERTIES AND TECHNOLOGY OF TCO/a-Si:H(n)/c-Si(p)

HETEROSTRUCTURE SOLAR CELLS: A GERMAN NETWORK PROJECT

K. v. Maydell1, H. Windgassen2, W.A. Nositschka2, U. Rau3, P. J. Rostan3, J. Henze4, J. Schmidt4, M. Scherff 5,W. Fahrner5,

D. Borchert6, S. Tardon7, R. Brüggemann7, H. Stiebig8, and M. Schmidt1

1 Hahn-Meitner Institute Berlin, Kekuléstr.5, D-12489 Berlin, Germany, email: maydell@hmi.de

2 Aachen University, Institute of Semiconductor Electronics, Sommerfeldstr. 24, D-52074 Aachen, Germany

3 University Stuttgart, Institute of Physical Electronics, Pfaffenwaldring 57, D-70569 Stuttgart, Germany

4 Institute for Solar Energy Research Hameln/Emmerthal, Am Ohrberg 1, D-31860 Emmerthal, Germany

5 FernUniversit?t Hagen, Dept. of Electrical Engineering, Haldener Strasse 182, D-58084 Hagen, Germany

6 Fraunhofer Institute for Solar Energy Systems, Auf der Reihe 2, D-45884 Gelsenkirchen, Germany

7 Institute of Physics, Carl von Ossietzky University Oldenburg, D-26122 Oldenburg, Germany

8 Institute of Photovoltaics, Research Center Jülich, D-52425 Jülich, Germany

ABSTRACT: We report on a German network project in which the technology and the basic electronic properties of amorphous/crystalline silicon heterojunction solar cells are investigated. In contrast to the approach of Sanyo our focus is on hetero solar cells fabricated on p-type substrates without an a-Si:H(i) buffer-layer. One goal of the project is to transfer the results obtained on single crystalline wafers to inexpensive substrates, such as block-cast multicrystalline silicon or edge-defined film-fed grown silicon. All solar cells investigated here are completely processed at low temperatures (<250°C). Simulation studies show that a critical parameter is the defect density at the interface between the amorphous and the crystalline semiconductor both at the front and rear side. The interface state density has to be minimized to obtain maximum open circuit voltages. Using optimised deposition conditions of the amorphous silicon efficiencies larger 17% are obtaind on p-type c-Si wafers and larger 18% on n-type c-Si. For large area cells a low temperature screen printing process was developed. On a cell area of 10×10 cm2 an efficiency of

12.9% on block-cast multicrystalline silicon is achieved.

Keywords: Heterojunction, Solar cell

1 INTRODUCTION

Heterojunction solar cells composed of hydrogenated amorphous silicon (a-Si:H) deposited on single crystalline silicon wafers (c-Si) gain more and more interest for high efficiency solar cells. Sanyo reported an efficiency larger 21% of for an a-Si:H(p, i)/c-Si(n)/a-Si:H(i, p) solar cell [1]. The high efficiencies were obtained by implementing an intrinsic a-Si:H layer between the doped a-Si:H layer and the c-Si wafer both at the front and at the rear surface. However, the efficiencies for heterojunction solar cells based on p-type substrates are still significantly lower than for solar cells based on n-type substrates.

Two main advantages arise from the a-Si:H/c-Si solar cell structure: i) The a-Si:H layer can be deposited at low temperatures (< 230°C). Any high temperature steps such as a back surface field diffusion can be omitted. This can be very important for temperature sensitive substrates such as thin film silicon on glass ii) Hydrogenated amorphous silicon is known to passivate silicon surfaces in an excellent way [2]. Thus, the a-Si:H/c-Si concept has the potential for high open circuit voltages.

In this paper the results of a German network project are described. In this project the technological and the scientific expertise of the partners is combined to develop highly efficient a-Si:H/c-Si heterojunction solar cells. In contrast to the approach of Sanyo the focus of the project is on a-Si:H(n)/c-Si(p) structures. All process steps of the solar cell fabrication should be performed at temperatures below 250°C. The results obtained on single crystal c-Si wafers are transferred to inexpensive substrates as block-cast multicrystalline (mc-Si) and edge-defined film-fed grown silicon (EFG-Si) wafers. Additionally, low temperature passivation schemes based

evaluated to improve the bulk lifetime of these materials. Due to the low process temperatures any possible thermal lifetime degradation can be completely avoided. Industrially relevant processes like a low temperature screen-printing step are implemented and stability tests are performed. In addition to the technological approach one goal of the project is to improve the fundamental physical understanding of the a-Si:H/c-Si heterojunction.

A sketch of the band diagram of an a-Si:H(n)/c-Si(p)/a-Si:H(p) structure is shown in Fig. 1. The heterojunction is dominated by two interfaces between a-Si:H and c-Si. Both interface are characterised by an interfaces state density, D it, and band offsets, ?E, which arise due to the different band gaps of a-Si:H and c-Si. The a-Si:H layer itself exhibits a high concentration of deep bulk defects and band-tail states.

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2 EXPERIMENTAL

The silicon heterojunction solar cells were fabricated by deposition of hydrogenated amorphous silicon on c-Si wafers by plasma enhanced chemical vapour deposition (PECVD) or by electron cyclotron resonance CVD. Doping was achieved by mixing silane with phosphine and diborane for n-type and p-type doping, respectively. Prior to the a-Si:H deposition the wafers were cleaned by a RCA cleaning sequence and a HF-dip.

As transparent conductive oxide either ZnO or ITO were used. The contact grid at the front side was formed by evaporating Al or Cr/Ag. Definition of the contact grid was done by photolitography. An additional aim of the project is the development of a low temperature screen printed front contact grid for large area solar cells. On the rear side of the solar cells, Al was evaporated.

The simulations presented in this work were performed using the simulation program AFORS-HET [3].

3 RESULTS

As shown in Fig. 1, the a-Si:H/c-Si heterojunction solar cell is dominated by two interfaces between a-Si:H and c-Si. The interface is characterised by an interface states density and band offsets. Simulation results have indicated that a high interface defect density severely reduces the open circuit voltage [4]. To illustrate the effect Fig. 2 shows V OC

as a function of the interfaces states density for two different values of the conduction band offset for a Metal/a-Si:H(n)/c-Si(p)/Metal structure. For D it < 5×1010 cm-2 Voc is nearly constant at about 647meV with increasing D it for ?E C = 0.15eV. A further increase in D it results in a significant decrease of Voc. Between 5×1010cm-2< D it < 5×1012 cm-2 V OC decreaes by about 90 meV from 640 to 550meV. The open triangles in Fig. 2 show the situation when the band offset for the minority carriers is large. In this case the decrease of V OC with increasing D it starts at D it ≈3×1011cm-3. However, ?E C was determined to be about 0.15eV [5] and thus the solar cell is strongly influenced by D it even at low values.

These results show that it is a major task for density. This can be done in several ways: i) The cleaning of the c-Si wafers can be optimised in such a way that the growth of the a-Si:H results in a low D it. ii) The deposition conditions can be set that an optimal growth of the a-Si:H is achieved. iii) A passivation layer between the doped a-Si:H and the c-Si can be implemented. Sanyo reported that the insertion of an intrinisic a-Si:H layer leads to a significant enhancement of V OC due to a well passivated c-Si surface. However, this was shown for solar cells based on n-type substrates only. Fig. 3 shows IQE spectra of an a-Si:H(n, i)/c-Si(p) heterojunction solar cell with different a-Si:H(i) layer thicknesses, d a-Si:H(i). In this solar cells a boron diffused back surface field was implemented. A thin a-Si:H(i) layer (3nm) leads to an enhancement of the IQE in the short wavlength region compared to the sample which contains no intrinsic layer. A further increase in the a-Si:H(i) layer thickness leads to a reduction in the IQE. This is due to internal losses in the emitter. Previously it was published that the emitter thickness leading to maximum effieciency is at about 5 nm [6].

The inset in Fig. 3 shows the efficiency of the solar cells as a function of the a-Si:H(i) layer thickness. For d a-Si:H(i)

= 0 nm an efficiency of 16.9% was achieved. This value is slightly increased to 17.1% for d a-Si:H(i)= 3 nm and decreases for thicker a-Si:H(i) layers. This finding is supported by the results of the IQE measurements. When the a-Si:H layer becomes thicker internal losses in the defect rich layer causes a reduction in the IQE and thus in the efficiency. In contratst to results reported from Sanyo for an a-Si:H(p, i)/c-Si(n) solar cell the insertion of an a-Si:H(i) layer in an a-Si:H(n)/c-Si(p) structure only leads to marginal device improvement. This can have several reasons: i) the defect density of the a-Si:H(i) layer is still too high and thus the passivation effect is not improved compared to an a-Si:H(n) layer, ii) the band allignment becomes unfavourable by inserting the a-Si:H(i) layer. Further investigations are necessary. The interface states density can also be optimized by the a-Si:H deposition conditions. Fig. 4 shows the solar cell efficiency of an a-Si:H(n)/c-Si(p) heterojunction solar cell with a diffused back surface field as a function of the deposition temperature of the a-Si:H layer. Clearly a maximum of η = 16.9% can be observed for T S≈ 230°C.

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results which show that the photoluminescence intensity is highest around this temperature and thus the interface

recombination rate is lowest [7].

The rear side of the solar cell structure is an important part of the device. Figure 5 shows V OC values determined by simulation of an a-Si:H(n)/c-Si(p) heterojunction with varying surface recombination velocity at the rear side. For S > 10 cm/s, V OC decreaes rapidly from about 677mV to 647 mV at S = 104cm/s. In the project different kinds of low temperature processed rear sides were compared. Table I summarises V OC data obtained for an a-Si:H(n)/c-Si(p) heterojunction solar cell with different rear side concepts. Serving as a reference a boron-diffused rear side results in a V OC of 635mV. Using an a-Si:H(p) layer with a thickness of about 35nm a V OC of about 634mV was obtained. In contrast to the diffused rear side the a-Si:H(p) coated rear side is processed at temperartures below 230°C. Additionally, a COSIMA rear side was implemented which results in a comparable V OC as the former two structures. The COSIMA rear side uses the passivation effect of a-Si:H combined with local Al contacts evaporated on top of the a-Si:H layer. This structure is annealed at low temperature to form the contact of Al to the base of the cell [8]. Recently the University of Stuttgart developed a rear side consisting of a stack of a-Si:H(i), a-Si:H(p), μc-Si(p) and ZnO. Using a diffused emitter as a front electrode a V OC of 678mV was achieved resulting in a

confirmed efficiency of the device of 21% [9]. This is a promising result for low-temperature a-Si:H back contacts on p-type Si wafers. This back contact will be implemented in a complete a-Si:H/c-Si solar cell structure in the next future. Note that all developed rear contact systems are in accordance with our low temperature approach.

The quality of the passivation of the c-Si surfaces and the quality of the substrate can be investigated by luminescence measurements [10]. The quasi Fermi level splitting which is determined by quantitative photoluminescence measurements gives the maximum achievable V OC . Fig. 6 shows calibrated luminescence spectra of a c-Si wafer after different process steps in the processing of an a-Si:H/c-Si solar cell structure. The splitting of the quasi Fermi levels can be deduced from the formula of the rate of spontaneous emission fitted to the calibrated photoluminescence spectra [11]. Each step of the solar cell production increases the maximum achievable V OC up to V OC = 667mV.

As mentioned above, one goal of the network project is the transfer of the results obtained for single crystalline silicon to cheaper substrates such as mc-Si and EFG-Si. The diffusion lengths in these materials are usually

smaller than diffusion lengths meausred in float-zone and Czochralski-grown single crystalline silicon wafers. To obtain high solar cell efficiencies, the diffusion length should be well above the wafer thickness. For many multicrystalline silicon wafer materials this is not initially the case. To improve the carrier lifetime of the mc-Si or EFG-Si materials, a phosphorus gettering step is performed in the typical commercial solar cell processes. This phoshporus diffusion step at ~870°C creates the n + emitter and effectively removes metallic contaminants from the material. The diffusion is followed by a

Rear side Front side Voc(mV)

Diffused a-Si:H(n) 635 a-Si:H(p) a-Si:H(n) 634 COSIMA a-Si:H(n) 629 a-Si:H(i, p)/μc-Si(p)/TCO

Diffused 678

Tab. I: Open circuit voltages for solar cell structures with different rear contacts.

Fig. 6: Measured calibrated luminescence spectra of a-Si:H/c-Si heterostructures. The numbers gives the maximum achievable open circuit voltages.

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contact firing at high tempertures (~800°C). During the firing, hydrogen diffuses from the a-SiNx:H layer deposited at the front into the bulk where it passivated defects, leading to a further increase in lifetime. A low-temperture alternative to the latter step is the H-passivation using microwave-induced remote-plasma hydrogen treatment. In Fig. 7, the effective lifetime of several neighbouring EFG-Si wafers averaged over an area of 25 cm2 is shown for different passivation times and temperatures. Prior to the H-passivation, a P gettering step was performed.. The averaged lifetime of the as-grown EFG-Si is only 6 μs. This value is strongly enhanced by a P-gettering step up to a factor of ~10. H-passivation leads to a further pronounced increase in the lifeime. The lifetime depends strongly on the plasma-hydrogenation temperature. The highest lifetimes are obtained for a hydrogenation temperature of 400°C and a passivation time larger 1 h. The averaged lifetime of about 130 μs is comparable to the lifetime obtained using the high-temperature SiN-hydrogenation treatment. The H-passivation by microwave-induced remote-plasma hydrogenation can be easily implemented in a production line and is in accordance with the low-temperature approach of the heterojunction solar cell concept.

One goal of the project is to develop and investigate industrially relevant processes. Therefore, a low-temperature screen printed front contact was implemented. The grid is optimized for a sheet resistivity

of the TCO which is about 50 ?/sq. The commercially available silver polymer screen-printing paste is modified by some additives to obtain an optimized contact finger structure. The temperature during the screen printing is always lower than 230°C. More details can be found in Ref. 12.

Table II summarizes the efficiencies obtained so far on p-type and n-type substrates for small (1cm2) and large (8x8cm2) area solar cells. All solar cells were processed at temperatures below 230°C. The large area solar cells on mc-Si and EFG-Si were processed with the low temperature screen printed front contact. The solar cells were performed without an additional a-Si:H(i) layer.

Stability tests performed on a-Si:H/c-Si solar cells using ITO as the TCO and an Cr/Ag front grid showed no degradation of the solar cell parameters. Details can be found in Ref. 13.

CONCLUSION

In conclusion, the combined work of the network project lead to efficient a-Si:H/c-Si solar cells on single crystal and inexpensive substrates. To process the solar cells completely at low temperatures different rear sides have been tested. Promising candidate is a stack of a-Si:H and μc-Si for a good passivation as well for a good contact to the rear electrode. For the front contact a low temperature screen printing was developed. Additionally to the technological approach a detailed physical knowledge has been gained during the project. ACKNOWLEDGEMENT

This work was supported by Bundesministerium für Bildung und Forschung under contract nr.: 01SF0012-19

REFERENCES

[1] M. Taguchi, H. Sakata, Y. Yoshimine, E.

Maruyama, A. Terakawa, M. Tanaka, S. Kiyama,

Proc. of the 31st IEEE PVSC Lake Buena Vista

(2005) at press.

[2] S. Dauwe, J. Schmidt, J. Hezel, Proc. of the 29th

IEEE PVSC New Orleans (2002) 1246.

[3] R. Stangl, M. Kriegel, M. Schmidt, this conference

2DO.3.5.

[4] G.H. Bauer, R. Brüggemann, M. R?sch, S. Tardon,

T. Unold, physica status solidi C 1, 5 (2004) 1308.

[5] M. Schmidt, A. Schoepke, O. Milch, T. Lussky, W.

Fuhs, MRS Symp. Proc. 762 (2003) A19.11.1. [6] M. Scherff, A. Froitzheim, A. Ulyashin, M.

Schmidt, W. R. Fahrner, W. Fuhs, Proc. of PV in

Europe, Rome (2002) 216.

[7] A. Laades, K. Kliefoth, L. Korte, K. Brendel, R.

Stangl, M. Schmidt, W. Fuhs, Proc of the 19th

EPVSEC Paris (2004) 1170.

[8] H. Plagwitz, M. Nerding, N. Ott, H. P. Strunk, R.

Brendel, Progress in Photovoltaics 12 (2004) 47. [9] P. J. Rostan, U. Rau, T. Kirchartz, V. X. Nguyen,

M. B. Schubert, J. H. Werner, unpublished.

[10] S. Tardon, M. R?sch, R. Brüggemann, T. Unold,

G.H. Bauer, J. Non-Cryst. Solids 338 (2004) 444.

[11] P. Würfel, J. Phys C 15 (1982) 3967.

[12] H. Windgassen, M. Scherff, W. A. Nositschka, H. Kurz, W. R. Fahrner, this conference, 2CV.4.2. [13] H. Stiebig, U. Zastrow, M. Scherff, A. G. Ulyashin,

this conference, 2CV.4.31.

Structure Area

(cm2)

Eta a-Si:H(n)/c-Si(p)/a-Si:H(p) 1 17.1 a-Si:H(p)/c-Si(n)/a-Si:H(n) 1 18.2 a-Si:H(n)/c-Si(p)/BSF 10×10 15.0

a-Si:H(n)/mc-Si(p) 10×10 12.9

a-Si:H(n)/EFG-Si(p)/a-Si:H(p) 8×8 12.7

Tab.II: Efficiencies of different heterojunction solar

cell processed in the network project.

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STM8L中文参考手册(4)-

STM8L中文参考手册（4）- 20 16位通用定时器(TIM2、TIM3、tim5) 20.1简介本章介绍TIM2、TIM3和tim5是相同的定时器每个定时器包括一个由可编程分频器驱动的16位上下自动重载计数器它可以用于多种目的，包括:●定时产生●测量输入信号的脉冲长度(输入捕获) ●产生输出波形(输出比较、脉宽调制和脉冲模式)●各种中断能力事件(捕获、比较、溢出) ●与其他定时器或外部信号(外部时钟、复位、触发使能)同步定时器时钟可以来自内部时钟，也可以来自配置寄存器或外部源本章仅介绍通用定时器的主要特性。它参考了与19:16高级控制定时器(TIM1)相对应的部分中的每个功能的更详细的信息页28320.2 TIMx 主要功能通用TIMx TIM2/TIM3功能包括: ●16位向上、向下、向上/向下自动刷新计数器●3位可编程分频器允许将计数器的时钟频率分成1至128的任意2次方两个独立的低电平通道:输入捕获输出比较脉冲宽度调制产生(边沿对齐)-一个脉冲输出模式低电平中断输入，用于复位定时器输出信号，或处于已知状态●输入捕捉2可通过来自comp2比较器 :

更新的中断和DMA请求产生以下事件:当计数器溢出时，计数器初始化(软件)输入捕捉输出比较中断输入触发事件(开始、停止、内部/外部触发初始化或计数) 20.3.1时间单元定时器时基单元包括:●16位可逆计数器时钟源是内部时钟(fsysclk)它由预分频器计数器的时钟ck_cnt驱动，预分频器计数器直接连接到ck_psc时钟馈送分频器分频器的实现如下:7位计数器(在timx_pscr寄存器中)由基于低预分频器的3位寄存器控制它可以控制飞行中寄存器缓冲区的变化。它可以将计数器的时钟频率转换为1、2、4、8、16、32、64或128计数器的时钟频率计算如下: fCk _ CNT = fck _ PSC/2(PSCR[2:0)计数器操作请参考第19.3.4页:上部288，模式部分19.3.5:在第290页向下计数，模式19.3.6:中心对齐(向上/向下计数)29220.3.2时钟/触发控制器参见第296页第19.4节:TIM1时钟/触发控制器20.3.3采集/比较通道输入级参见第310页第19.5节:TIM1采集/比较通道有两个输入通道，如图122:输入级框图通道2内部连接到比较器

stm8l中文参考手册(下)

手动开关手动开关没有自动切换为直接的但它提供给用户的切换事件时间的精确控制。参照图20中的流程图。 1。写使用系统时钟开关选择目标时钟源的8位值寄存器（clk_swr）。然后swbsy位是由硬件，和目标源振荡器开始。古老的时钟源继续驱动CPU和外设。 2。该软件具有等到目标时钟源准备（稳定的）。这是在clk_swcr寄存器和快捷旗由中断如果swien位设置显示。 3。最终软件的作用是设置，在所选择的时间，在clk_swcr的赛文点寄存器来执行开关。在手动和自动切换模式，旧的系统时钟源不会自动关闭的情况下是由其他模块（LSI混凝土可用于例如独立的看门狗驱动）。时钟源可以关机使用在内部时钟寄存器的位（clk_ickcr）和外部时钟寄存器（clk_eckcr）。如果时钟开关不因任何原因的工作，软件可以通过清除swbsy 标志复位电流开关操作。这将恢复clk_swr注册到其以前的内容（旧的系统时钟）。注意：在清理swbsy标志具有复位时钟主开关的程序，应用程序必须等到后产生新的主时钟切换请求之前有一段至少两个时钟周期。

9.7周门控时钟（PCG）外周时钟门控（PCG）模式选择性地启用或禁用系统时钟（SYSCLK）连接到外围设备在运行或慢速模式的任何时间来优化功耗。设备复位后，所有的外设时钟被禁用。唯一的一点是在复位状态是默认启用pcken27因为它用于启动。软件已被正确地写入关掉ROM Bootloader执行后的时钟。您可以启用时钟的任何外围设置在clk_pckenrx周围门控时钟寄存器的相应pcken点。 ●使周围，首先使在clk_pckenr相应的pcken点寄存器然后设置使点周围的外围控制寄存器。 ●禁用适当的外围，先禁用在周边的适当位控制寄存器，然后停止相应的时钟。

stm8L051F3

This is information on a product in full production. March 2014 DocID023465 Rev 21/93 STM8L051F3 Value Line, 8-bit ultralow power MCU, 8-KB Flash, 256-byte data EEPROM, RTC, timers, USART, I2C, SPI, ADC Datasheet production data Features ?Operating conditions –Operating power supply: 1.8 V to 3.6 V Temperature range: ?40 °C to 85 °C ?Low power features – 5 low power modes: Wait, Low power run (5.1 μA), Low power wait (3 μA), Active-halt with RTC (1.3 μA), Halt (350 nA)–Ultra-low leakage per I/0: 50 nA –Fast wakeup from Halt: 5 μs ?Advanced STM8 core –Harvard architecture and 3-stage pipeline –Max freq: 16 MHz, 16 CISC MIPS peak –Up to 40 external interrupt sources ?Reset and supply management –Low power, ultra-safe BOR reset with 5 selectable thresholds –Ultra low power POR/PDR –Programmable voltage detector (PVD)?Clock management –32 kHz and 1 to 16 MHz crystal oscillators –Internal 16 MHz factory-trimmed RC –Internal 38 kHz low consumption RC –Clock security system ?Low power RTC –BCD calendar with alarm interrupt –Digital calibration with +/- 0.5 ppm accuracy –LSE security system –Auto-wakeup from Halt w/ periodic interrupt ?Memories –8 Kbytes of Flash program memory and 256 bytes of data EEPROM with ECC –Flexible write and read protection modes – 1 Kbyte of RAM ?DMA – 4 channels supporting ADC, SPI, I2C, USART, timers – 1 channel for memory-to-memory ?12-bit ADC up to 1 Msps/28 channels –Internal reference voltage ?Timers –Two 16-bit timers with 2 channels (used as IC, OC, PWM), quadrature encoder –One 8-bit timer with 7-bit prescaler – 2 watchdogs: 1 Window, 1 Independent –Beeper timer with 1, 2 or 4 kHz frequencies ?Communication interfaces –Synchronous serial interface (SPI)–Fast I 2C 400 kHz SMBus and PMBus –USART ?Up to 18 I/Os, all mappable on interrupt vectors ?Development support –Fast on-chip programming and non-intrusive debugging with SWIM –Bootloader using USART https://www.sodocs.net/doc/df9196978.html,

STM8L入门手册

STM8L单片机入门手册注：本教程以STM8L052R8和IAR开发环境为例1、IAR环境安装与注意事项：安装时按照一般软件安装即可，提示需要输入License时请使用IAR kegen PartC软件进行破解，注意Product选择STM8项，如下图示：另外：机器上本身安装过MSP430平台的IAR环境，安装STM8平台的IAR是可以兼容的

2、IAR环境创建STM8工程： 2.1、创建工程如下图示，打开IAR环境for STM8 选择project->Create New Project，选择C语言开发，点击“OK” 选择保存路径后输入工程名点击“保存”即可。

按上图示，添加文件分组，并命名“SRC”和“Lib”，类似方法在分组中添加文件。 2.2工程重要设置：右击工程名，选择“Options…” 在General Options项中，Target选项卡中按照下图设置：在C/C++ Compiler项中，Preprocessor选项卡中添加头文件路径，如下图示：

红色圈内容直接输入（不能选？？？） $PROJ_DIR$\..\Lib\inc 解释：$PROJ_DIR$->表示当前工程目录（.eww文件所在目录）； ..->表示上层目录；在Debugger项中，设置仿真调试器与入口函数，如下图示：

main 上图中，Run to：写main 这里是设置入口函数2.3设置生成HEX文件：右击工程名，选择“Options…”

该设置不会影响调试器在线仿真功能，可以一直勾选上，这点和MSP430不同。 3、IAR环境常见问题及解决方法 3.1、Couldn’t go to ‘M52Li’ 进入调试模式是会有下图警告，并且不能调试找不到入口函数，入口函数应该是main 3.2、“The debugging session could not be started.” 由于脱机烧录或者其他原因写了保护，造成连接不上目标板。解决方法：打开STVP软件，点击读取按钮，会出现以下报错：此时，进入到OPTION BYTE页面，将ROP写为OFF模式，如下图示

STM8L05X入门学习笔记

1、工程新建首先新建文件夹，在文件夹下建立四个文件（这个看个人喜好），我喜欢建立一个工程文件夹Project用于存放工程文件，Library文件用于存放库文件，App用于存放用户程序，Doc 用于存放说明文档，如图1所示。图1 二：将官方的库文件Libraries文件下STM8S_StdPeriph_Driver这个文件下的内容复制到自己新建的Library文件下，把官方Project文件下Template文件夹下main.c stm8s_conf.h stm8s_it.c 和stm8s_it.h复制到App文件夹下。如图2，图3。图2 图3 三：打开IAR 选择Project-> Create New Project –>ok,将文件保存到Project下，

这时工程已经建好，右击工程选择Add Group,然后依次添加文件App,Libraries,Doc,BSP_CFG 配置好如图所示四：给工程下APP添加App文件下的文件如图

给Libraries添加Library文件下src文件下的所有文件、五配置Options,包括如下，1选择型号这里选STM8S903K3 2C++选项卡配置路经，和型号的宏定义。

六编译工程，这事会提醒对工程的保存，进行保存即可，这时会发现很多错误，这是因为这个库包含了所有的型号，有些这个单片机没有，将它移除即可。再次编译就会发现没有错误了。 7HEX文件输出

2、系统时钟四种不同的时钟源可以用来驱动系统时钟： ●16 MHz 高速内部（HSI）工厂调整RC 时钟 ●1 到16 MHz 高速外（HSE）振荡器时钟 ●32.768 千赫低速外（LSE）振荡器时钟 ●38 千赫低速内部（LSI）低功耗时钟每个时钟源可以开启或关闭独立不使用时的功耗，优化。这四个时钟可以用一个可编程分频器（因素1 至128）驱动系统时钟（系统时钟）。该系统时钟用于时钟的核心，内存和外设。复位后，该设备重新启动与HSI 时钟除以8 的违约。该分频器分频比时钟源可以改变应用程序尽快执行代码起点。

stm8L 数据手册

October 2010Doc ID 15275 Rev 111/81 STM8L101xx 8-bit ultralow power microcontroller with up to 8 Kbytes Flash, multifunction timers, comparators, USART , SPI, I2C Features ■ Main microcontroller features –Supply voltage range 1.65 V to 3.6 V –Low power consumption (Halt: 0.3μA, Active-halt: 0.8μA, Dynamic Run: 150μA/MHz) –STM8 Core with up to 16 CISC MIPS throughput –Temp. range: -40 to 85°C and 125 °C ■ Memories –Up to 8 Kbytes of Flash program including up to 2 Kbytes of data EEPROM –Error correction code (ECC) –Flexible write and read protection modes –In-application and in-circuit programming –Data EEPROM capability – 1.5 Kbytes of static RAM ■ Clock management –Internal 16 MHz RC with fast wakeup time (typ. 4μs) –Internal low consumption 38kHz RC driving both the IWDG and the AWU ■ Reset and supply management –Ultralow power, ultrasafe power-on-reset /power down reset –Three low power modes: Wait, Active-halt, Halt ■ Interrupt management –Nested interrupt controller with software priority control –Up to 29 external interrupt sources ■ I/Os –Up to 30 I/Os, all mappable on external interrupt vectors –I/Os with prog. input pull-ups, high sink/source capability and one LED driver infrared output ■ Peripherals –Two 16-bit general purpose timers (TIM2 and TIM3) with up and down counter and 2 channels (used as IC, OC, PWM) –One 8-bit timer (TIM4) with 7-bit prescaler –Infrared remote control (IR)–Independent watchdog –Auto-wakeup unit –Beeper timer with 1, 2 or 4 kHz frequencies –SPI synchronous serial interface –Fast I2C Multimaster/slave 400 kHz –USART with fractional baud rate generator – 2 comparators with 4 inputs each ■Development support –Hardware single wire interface module (SWIM) for fast on-chip programming and non intrusive debugging –In-circuit emulation (ICE)■ 96-bit unique ID Table 1. Device summary Reference Part number STM8L101xx STM8L101F1, STM8L101F2, STM8L101F3, STM8L101G2, STM8L101G3STM8L101K3 https://www.sodocs.net/doc/df9196978.html,