IRFP23N50LPBF中文资料
IRFP23N50LPbF
02/11/04
SMPS MOSFET HEXFET ?
Power MOSFET
TO-247AC
Features and Benefits
?SuperFast body diode eliminates the need for external diodes in ZVS applications.
?Lower Gate charge results in simpler drive requirements.?Enhanced dv/dt capabilities offer improved ruggedness.?Higher Gate voltage threshold offers improved noise
immunity .
Applications ?Zero Voltage Switching SMPS
?Telecom and Server Power Supplies
?Uninterruptible Power Supplies
?Motor Control applications
?Lead-Free
= 0V f = 125°C, di/dt = 100A/μs f https://www.sodocs.net/doc/d516680480.html, 1
PD - 94999
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Repetitive rating; pulse width limited by
max. junction temperature. (See Fig. 11). Starting T J = 25°C, L = 1.5mH, R G = 25?, I AS = 23A, dv/dt = 14V/ns. (See Figure 12). I SD ≤ 23A, di/dt ≤ 430A/μs, V DD ≤ V (BR)DSS , T J ≤ 150°C.
Notes:
Pulse width ≤ 300μs; duty cycle ≤ 2%.
C oss eff. is a fixed capacitance that gives the same charging time
as C oss while V DS is rising from 0 to 80% V DSS .
C oss eff.(ER) is a fixed capacitance that stores the same energy as C oss while V DS is rising from 0 to 80% V DSS .
Static @ T
= 25°C (unless otherwise specified)
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Vs. Temperature
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics V DS , Drain-to-Source Voltage (V)
I , D r a i n -t o -S o u r c e C u r r e n t (A )
V DS , Drain-to-Source Voltage (V)
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Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
1
10
100
1000
V DS , Drain-to-Source Voltage (V)
10
100
1000
10000
100000
C , C a p a c i t a n c e (p F )
100
200
300
400
500
600
V DS, Drain-to-Source Voltage (V)
05
10
15
20
25
E n e r g y (μJ )
Fig 8. Typical Source-Drain Diode
Forward Voltage
0.0
0.5
1.0
1.5
2.0
V SD , Source-toDrain Voltage (V)
0.10
1.00
10.00
100.00
I S D , R e v e r s e D a i n C u r r e n t (A )
Gate-to-Source Voltage
Fig 6. Typ. Output Capacitance
Stored Energy vs. V DS
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Case Temperature
Fig 11a. Switching Time Test Circuit
V DD
V DS V d(on)
r
d(off)
f
Fig 11b. Switching Time Waveforms
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Fig 13. Threshold Voltage vs. Temperature
T J , Temperature ( °C )
V G S (t h ) G a t e t h r e s h o l d V o l t a g e (V )
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V DS
Current Sampling Resistors
V GS Fig 16a. Gate Charge Test Circuit Fig 16b. Basic Gate Charge Waveform
Fig 15b. Unclamped Inductive Waveforms
Fig 15a. Unclamped Inductive Test Circuit
I V DD
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Fig 17. For N-Channel HEXFET ? Power MOSFETs
* V GS = 5V for Logic Level Devices
Peak Diode Recovery dv/dt Test Circuit
V DD
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TO-247AC Package Outline
Dimensions are shown in millimeters (inches)