GD32F150xx Datasheet Rev2.1
GigaDevice Semiconductor Inc.
GD32F150xx
ARM? Cortex?-M3 32-bit MCU
Datasheet
Table of Contents
List of Figures (3)
List of Tables (4)
1 General description (5)
2 Device overview (6)
2.1 Device information (6)
2.2 Block diagram (7)
2.3 Pinouts and pin assignment (8)
2.4 Memory map (10)
2.5 Clock tree (11)
2.6 Pin definitions (12)
3 Functional description (18)
3.1 ARM? Cortex?-M3 core (18)
3.2 On-chip memory (18)
3.3 Clock, reset and supply management (19)
3.4 Boot modes (19)
3.5 Power saving modes (20)
3.6 Analog to digital converter (ADC) (20)
3.7 Digital to analog converter (DAC) (21)
3.8 DMA (21)
3.9 General-purpose inputs/outputs (GPIOs) (21)
3.10 Timers and PWM generation (22)
3.11 Real time clock (RTC) (23)
3.12 Inter-integrated circuit (I2C) (23)
3.13 Serial peripheral interface (SPI) (24)
3.14 Universal synchronous asynchronous receiver transmitter (USART) (24)
3.15 Inter-IC sound (I2S) (24)
3.16 HDMI CEC (25)
3.17 Universal serial bus full-speed (USB 2.0 FS) (25)
3.18 Touch sensing interface (TSI) (25)
3.19 Comparators (CMP) (26)
3.20 Debug mode (26)
3.21 Package and operation temperature (26)
4 Electrical characteristics (27)
4.1 Absolute maximum ratings (27)
4.2 Recommended DC characteristics (27)
4.3 Power consumption (28)
4.4 EMC characteristics (29)
4.5 Power supply supervisor characteristics (29)
4.6 Electrical sensitivity (30)
4.7 External clock characteristics (30)
4.8 Internal clock characteristics (31)
4.9 PLL characteristics (32)
4.10Memory characteristics (32)
4.11 GPIO characteristics (32)
4.12 ADC characteristics (33)
4.13 DAC characteristics (33)
4.14I2C characteristics (33)
4.15 SPI characteristics (34)
5 Package information (35)
5.1 QFN package outline dimensions (35)
5.3 LQFP package outline dimensions (37)
6 Ordering Information (39)
7 Revision History (40)
List of Figures
Figure 1. GD32F150xx block diagram (7)
Figure 2. GD32F150Rx LQFP64 pinouts (8)
Figure 3. GD32F150Cx LQFP48 pinouts (8)
Figure 4. GD32F150Kx QFN32 pinouts (9)
Figure 5. GD32F150Gx QFN28 pinouts (9)
Figure 6. GD32F150xx memory map (10)
Figure 7. GD32F150xx clock tree (11)
Figure 8. QFN package outline (35)
Figure 9. LQFP package outline (37)
List of Tables
Table 1. GD32F150xx devices features and peripheral list (6)
Table 2. GD32F150xx pin definitions (12)
Table 3. Port A alternate functions summary (16)
Table 4. Port B alternate functions summary (17)
Table 5. Absolute maximum ratings (27)
Table 6. DC operating conditions (27)
Table 7. Power consumption characteristics (28)
Table 8. EMS characteristics (29)
Table 9. EMI characteristics (29)
Table 10 Power supply supervisor characteristics (29)
Table 11. ESD characteristics (30)
Table 12. Static latch-up characteristics (30)
Table 13. High speed external clock (HSE) generated from a crystal/ceramic characteristics (30)
Table 14. Low speed external clock (LSE) generated from a crystal/ceramic characteristics (31)
Table 15. High speed internal clock (HSI) characteristics (31)
Table 16. Low speed internal clock (LSI) characteristics (31)
Table 17. PLL characteristics (32)
Table 18. Flash memory characteristics (32)
Table 19. I/O port characteristics (32)
Table 20. ADC characteristics (33)
Table 21. DAC characteristics (33)
Table 22. I2C characteristics (33)
Table 23. SPI characteristics (34)
Table 25. QFN package dimensions (36)
Table 26. LQFP package dimensions (38)
Table 27. Part ordering code for GD32F150xx devices (39)
Table 28. Revision history (40)
1 General description
The GD32F150xx device belongs to the value line of GD32 MCU family. It is a 32-bit
general-purpose microcontroller based on the high performance ARM? Cortex?-M3 RISC
core with best ratio in terms of processing power, reduced power consumption and
peripheral set. The Cortex?-M3 is a next generation processor core which is tightly coupled
with a Nested Vectored Interrupt Controller (NVIC), SysTick timer and advanced debug
support.
The GD32F150xx device incorporates the ARM?Cortex?-M3 32-bit processor core
operating at 72 MHz frequency with Flash accesses zero wait states to obtain maximum
efficiency. It provides up to 64 KB on-chip Flash memory and up to 8 KB SRAM memory. An
extensive range of enhanced I/Os and peripherals connected to two APB buses. The
devices offer one 12-bit ADC, one 12-bit DAC and two comparators, up to five
general-purpose 16-bit timers, a general-purpose 32-bit timer, a basic timer, a PWM
advanced-control timer, as well as standard and advanced communication interfaces: up to
two SPIs, two I2Cs, two USARTs, a I2S, a HDMI-CEC a TSI and an USB 2.0 FS.
The device operates from a 2.6 to 3.6 V power supply and available in –40 to +85 °C
temperature range. Several power saving modes provide the flexibility for maximum
optimization between wakeup latency and power consumption, an especially important
consideration in low power applications.
The above features make the GD32F150xx devices suitable for a wide range of applications,
especially in areas such as industrial control, motor drives, user interface, power monitor and
alarm systems, consumer and handheld equipment, gaming and GPS, E-bike and so on.
2 Device overview 2.1 Device information
2.2 Block diagram
Figure 1. GD32F150xx block diagram
2.3 Pinouts and pin assignment
Figure 2. GD32F150Rx LQFP64 pinouts
V SSA PA1PA12PA11PA10PA9PA8PC9PC8PC7PC6PB15PB14PB13PA3
PF4
PF5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
V DD V SS PB9PB8PB7PB6BOOT0
PB5PB4PB3PD2
PC12
PB10
PB11
V SS
PA13PA15
PA14
V BAT PC13
PC14-OSC32_IN PC15-OSC32_OUT
NRST PA0
PA2
PB12
V DD
PC0PC1PC2PC3V DDA PC10
PC11
PF1-OSC_OUT
PF0-OSC_IN
PA5
PA4
PF6PF7
Figure 3. GD32F150Cx LQFP48 pinouts
V SSA
PA1PA12PA11PA10PA9PA8PB15PB14PB13PA3
PA4
PA5
PA6
PA7
PB0
PB1PB2
V DD
V SS
PB9
PB8
PB7
PB6
BOOT0
PB5
PB4
PB3
PB10
PB11
V SS
PF6PA13PA15
PA14
V BAT PC13
PC14-OSC32_IN PC15-OSC32_OUT
NRST PA0PA2
PB12
V DD
V DDA PF1-OSC_OUT
PF0-OSC_IN
PF7
Figure 4. GD32F150Kx QFN32 pinouts
PA8PA3
PA4PA5
PA6PA7PB0PB1
PB7PB6
PB5
PA15PA9NRST
PA0V DDA OSC_OUT/PF1
OSC_IN/PF0V DD
PA1V DD
PA10PA11PB4PB8BOOT0
PA2
PB2
PA12PA13PA14PB3
Figure 5. GD32F150Gx QFN28 pinouts
PB1
PA2
PA3PA4
PA5PA6PA7PB0
PB5PB4
PB3PA14PA9NRST
PA0V DDA OSC_OUT/PF1
OSC_IN/PF0BOOT0PA1
V DD PA10PA13PA15
PB7PB6
PA11PA12
2.4 Memory map
Figure 6. GD32F150xx memory map
7
6
5
4
3
2
1
0x0800 0000
0x0000 0000
0x4002 20000x4002 24000x4002 30000x4002 34000x4002 40000x4002 44000x4800 00000x4800 04000x4800 08000x4800 0C000x4800 10000x4800 14000x4800 18000x5000 0000
2.5 Clock tree
Figure 7. GD32F150xx clock tree
Legend:
HSE = High speed external clock
HSI = High speed internal clock
LSE = Low speed external clock
LSI = Low speed internal clock
2.6 Pin definitions
Notes:
1. Type: I = input, O = output, P = power.
2. I/O Level: 5VT = 5 V tolerant.
3. This feature is available on GD32F150x4 devices only.
4. This feature is available on GD32F150x8 and GD32F150x6 devices only.
1. This feature is available on GD32F150x4 devices only.
2. This feature is available on GD32F150x8 and GD32F150x6 devices only.
1. This feature is available on GD32F150x4 devices only.
2. This feature is available on GD32F150x8 and GD32F150x6 devices only.
3 Functional description
3.1 ARM? Cortex?-M3 core
The Cortex?-M3 processor is the latest generation of ARM?processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
?32-bit ARM? Cortex?-M3 processor core
?Up to 72 MHz operation frequency
?Single-cycle multiplication and hardware divider
?Integrated Nested Vectored Interrupt Controller (NVIC)
?24-bit SysTick timer
The Cortex?-M3 processor is based on the ARMv7 architecture and supports both Thumb
and Thumb-2 instruction sets. Some system peripherals listed below are also provided by
Cortex?-M3:
?Internal Bus Matrix connected with ICode bus, DCode bus, system bus, Private
Peripheral Bus (PPB) and debug accesses (AHB-AP)
?Nested Vectored Interrupt Controller (NVIC)
?Flash Patch and Breakpoint (FPB)
?Data Watchpoint and Trace (DWT)
?Instrument Trace Macrocell (ITM)
?Serial Wire JTAG Debug Port (SWJ-DP)
?Trace Port Interface Unit (TPIU)
3.2 On-chip memory
?Up to 64 Kbytes of Flash memory
?Up to 8 Kbytes of SRAM with hardware parity checking
The ARM?Cortex?-M3 processor is structured in Harvard architecture which can use
separate buses to fetch instructions and load/store data. 64 Kbytes of inner Flash and 8
Kbytes of inner SRAM at most is available for storing programs and data, both accessed
(R/W) at CPU clock speed with zero wait states.The Figure 7. GD32F150xx memory map
shows the memory map of the GD32F150xx series of devices, including code, SRAM,
peripheral, and other pre-defined regions.
3.3 Clock, reset and supply management
?Internal 8 MHz factory-trimmed RC and external 4 to 32 MHz crystal oscillator
?Internal 40 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator
?Integrated system clock PLL
? 2.6 to 3.6 V application supply and I/Os
?Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage
detector (LVD)
The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These
include speed internal RC oscillator and external crystal oscillator, high speed and low speed
two types.Several prescalers allow the frequency configuration of the AHB and two APB
domains. The maximum frequency of the AHB and two APB domains is 72 MHz. See Figure
9 for details on the clock tree.
The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the
processor core and peripheral IP components. Power-on reset (POR) and power-down reset
(PDR) are always active, and ensures proper operation starting from 2.6 V and down to 1.8V.
The device remains in reset mode when V DD is below a specified threshold. The embedded
low voltage detector (LVD) monitors the power supply, compares it to the voltage threshold
and generates an interrupt as a warning message for leading the MCU into security.
Power supply schemes:
?V DD range: 2.6 to 3.6 V, external power supply for I/Os and the internal regulator.
Provided externally through V DD pins.
?V SSA, V DDA range: 2.6 to 3.6 V, external analog power supplies for ADC, reset blocks,
RCs and PLL. V DDA and V SSA must be connected to V DD and V SS, respectively.
?V BAT range: 1.8 to 3.6 V, power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when V DD is not present.
3.4 Boot modes
At startup, boot pins are used to select one of three boot options:
?Boot from main Flash memory (default)
?Boot from system memory
?Boot from on-chip SRAM
In default condition, boot from main Flash memory is selected. The boot loader is located in
the internal boot ROM memory (system memory). It is used to reprogram the Flash memory
by using USART1 in device mode.