ZA7783,功能MIPI转LVDS,MIPI转RGB888,RGB转LVDS
ZA7783 DATASHEET
ZA7783 Display Interface Converter
Datasheet
Version 0.7
Revision History
Ver.
Date
Author
Content
0.5 2013-5-14 Dai Jin 1. Initial release
0.6 2013-9-29 Jiang Bo 1. Add typical application circuit 2. Add package information 3. Add functional block diagram 0.7 2014-2-12
Jiang Bo
1. Change LVDS_ATO to DVDD18
ZA7783 DATASHEET
Table of Contents
1. OVERVIEW................................................................................3 2. TARGET APPLICATIONS.............................................................3 3. FEATURE DESCRIPTION .............................................................3 4. FUNCTIONAL BLOCK DIAGRAM..................................................5 5. PIN CONFIGURATION................................................................6 6. TYPICAL APPLICATION CIRCUIT..................................................9 7. PACKAGE INFORMATION (10)
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ZA7783 DATASHEET 1. Overview
ZA7783 is a bridge chip which supports three kinds of display interfaces:
●MIPI DSI RX Interface (1 Clock Lane + 4 Data Lanes)
●LVDS TX Interface (1 Clock Lane + 4 Data Lanes)
●MIPI DPI TX/RX Interface (PCLK + RGB888 + VSYNC + HSYNC +
DATAEN)
The chip bridges these display interfaces in three working modes:
●MODE1: MIPI DSI RX => LVDS TX
●MODE2: MIPI DSI RX => DPI TX
●MODE3: DPI RX => LVDS TX
Besides, there is also an I2C control interface (XCLK + I2C_SCL + I2C_SDA) for the host chip (AP or BB) to access ZA7783’s software registers.
Analog IPs of ZA7783 are supplied by 3.3V voltage (typical). For Digital IOs, the host interface (XCLK + I2C_SCL + I2C_SDA) is supplied by DVDD18 (PIN32), while the DPI interface (PCLK + RGB888 + VSYNC + HSYNC + DATAEN) is supplied by DVDD33 (PIN45 and PIN59). Thus, ZA7783 is able to bridge AP or BB with 1.8V IO to RGB Panel with 3.3V IO. Besides, an embedded LDO converts 3.3V to 1.2V to supply the chip’s internal digital logic. In addition, an embedded POR implements a power on reset to the whole chip.
2. Target Applications
Tablet PC
3. Feature Description
MIPI DSI RX Interface
●Compliant to MIPI DSI V1.01 and MIPI D-PHY V1.00
● 1 Clock Lane + 4 Data Lanes
●Data rate up to 600Mbps per data lane (300MHz high-speed clock on clock lane)
● 2.4Gbps bandwidth on four data lanes in total, giving a display resolution up to
1366x768 24bpp @ 60fps
●Only support MIPI DSI Video Mode (Non-Burst Mode with Sync Pulses) and all lanes
are unidirectional from the host chip to the bridge chip
●The host chip is required to provide continuous high-speed clock
ZA7783 DATASHEET ●Only support using all of the four data lanes, in other words, using part of them is not
supported
●Support multiple packets within a single high-speed transmission
●Ignore received virtual channel field
●Only the following packet data types are supported:
6'h01=Sync Event, V Sync Start (Short)
6'h11=Sync Event, V Sync End (Short)
6'h21=Sync Event, H Sync Start (Short)
6'h31=Sync Event, H Sync End (Short)
6'h08=End of Transimission packet (EoTp) (Short)
6'h09=Null Packet, no data (Long)
6'h19=Blanking Packet, no data (Long)
6'h2E=Loosely Packed Pixel Stream, 18-bit RGB, 6-6-6 Format (Long)
6'h3E=Packed Pixel Stream, 24-bit RGB, 8-8-8 Format (Long) The other packet data types cannot be handled and must not be sent to ZA7783!
●Ignore received ecc field
●Ignore received checksum field
●RGB565 Packed Pixel Stream and RGB666 Packed Pixel Stream are not supported
●For a data lane, the connection of Dp/Dn can be exchanged
●The order of the four data lanes can be configured
●Dither function for converting RGB888 to RGB666
LVDS TX Interface
●Compliant to LVDS Spec
● 1 Clock Lane + 4 Data Lanes
●Support RGB888 and RGB666
RGB888: 1 Clock Lane + 4 Data Lanes
RGB666: 1 Clock Lane + 3 Data Lanes
●Support NS Mode and JEIDA Mode
●The polarity of VSYNC/HSYNC/DATAEN can be configured
●For a data lane, the connection of Dp/Dn can be exchanged
●The order of the four data lanes can be configured
●Dither function for converting RGB888 to RGB666
DPI TX/RX Interface
●PCLK + RGB888 + VSYNC + HSYNC + DATAEN
●The edge of PCLK can be configured
●The polarity of VSYNC/HSYNC/DATAEN can be configured
I2C Interface
●An external clock XCLK should be provided (e.g. 26MHz)
●Up to 400Kbps
●I2C Slave ID is 0x37
ZA7783 DATASHEET 4. Functional Block Diagram
ZA7783 DATASHEET
5. Pin Configuration
R4R5R6R7
DVDD12AVDD33MIPI_CLKP
MIPI_CLKN MIPI_D0P MIPI_D0N
MIPI_D1P
MIPI_D1N MIPI_D2P MIPI_D2N MIPI_D3P
MIPI_D3N M I P I _A V D D 33
M I P I _R E X T
M I P I _B G V D D 33
L V D S _A V D D 33
L V D S _D 0P
L V D S _D 0N
L V D S _D 1P
L V D S _D 1N
L V D S _C L K P
L V D S _C L K N
L V D S _D 2P
L V D S _D 2N
L V D S _D 3P
L V D S _D 3N
L V D S _P L L V D D 33
D V D D 18
I2C_SDA
I2C_SCL
XCLK B0B1
B2
B3DVSS
B4B5
B6B7DVDD33
DATAEN HSYNC
VSYNC G 0
G 1
G 2
G 3
D V S S
G 4
G 5
G 6
G 7
P C L K
D V D D 33
R 0
R 1
R 2
R 3
D V S S
No. Name Description
1 R4
2 R5
3 R6
4 R7 DPI R[7:4]
5 DVDD12 LDO 1.2V Output (connected to 1uF ceramic cap) Digital Core 1.2V Power Supply
6 AVDD33 LDO 3.3V Power Supply
7 MIPI_CLKP 8
MIPI_CLKN
MIPI DSI RX Clock Lane
ZA7783 DATASHEET
9 MIPI_D0P 10 MIPI_D0N 11 MIPI_D1P 12 MIPI_D1N 13 MIPI_D2P 14 MIPI_D2N 15 MIPI_D3P 16 MIPI_D3N MIPI DSI RX Data Lane 0~3
17 MIPI_AVDD33 MIPI PHY 3.3V Power Supply
18 MIPI_REXT Tie a 24KOhm resistor (1% accuracy) to analog ground 19 MIPI_BGVDD33 MIPI PHY 3.3V BandGap Supply 20 LVDS_AVDD33 LVDS TX 3.3V Power Supply 21 LVDS_D0P 22 LVDS_D0N LVDS TX Data Lane 0 23 LVDS_D1P 24 LVDS_D1N LVDS TX Data Lane 1 25 LVDS_CLKP 26 LVDS_CLKN LVDS TX Clock Lane 27 LVDS_D2P 28 LVDS_D2N LVDS TX Data Lane 2 29 LVDS_D3P 30 LVDS_D3N LVDS TX Data Lane 3
31 LVDS_PLLVDD33
LVDS TX 3.3V PLL Supply 32 DVDD18
Digital IO 1.8V Power Supply
This power supply is for XCLK/I2C_SCL/I2C_SDA. 33 I2C_SDA I2C Serial Data Line 34 I2C_SCL I2C Serial Clock Line 35 XCLK XCLK Input (e.g. 26MHz) 36 B0 37 B1 38 B2 39 B3 DPI B[3:0] 40 DVSS Digital Ground 41 B4 42 B5 43 B6 44 B7 DPI B[7:4]
45 DVDD33 Digital IO 3.3V Power Supply
This power supply is for DPI IF, including PCLK, R7~0, G7~0, B7~0, VSYNC, HSYNC, and DATAEN. 46 DATAEN DPI Data Enable 47 HSYNC DPI HSYNC 48 VSYNC DPI VSYNC 49 G0 50 G1 51 G2 52 G3 DPI G[3:0] 53 DVSS Digital Ground 54 G4 55 G5 56
G6
DPI G[7:4]
ZA7783 DATASHEET
57 G7 58 PCLK DPI Pixel Clock
59 DVDD33 Digital IO 3.3V Power Supply
This power supply is for DPI IF, including PCLK, R7~0, G7~0, B7~0, VSYNC, HSYNC, and DATAEN. 60 R0 61 R1 62 R2 63 R3 DPI R[3:0]
64 DVSS Digital Ground
EP(65)
AVSS
Analog Ground for LDO, MIPI PHY, and LVDS TX
陈志华手机：１８１２３９０５５１６地址：深圳市宝安区互联网产业园Ａ区Ａ栋２０９Ｄ
香港众鑫微电子有限公司电话：０７５５－６１５９１８９６传真：０７５５－６１５９１８８１
ZA7783 DATASHEET
6. Typical Application Circuit
陈志华
手机：１８１２３９０５５１６地址：深圳市宝安区互联网产业园Ａ区Ａ栋２０９Ｄ
香港众鑫微电子有限公司
ZA7783 DATASHEET
7. Package Information
ZA7783 is provided in 8x8 QFN64 package, 0.4 pitch.
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