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MOSFET驱动芯片UCC27211中文资料

MOSFET驱动芯片UCC27211中文资料
MOSFET驱动芯片UCC27211中文资料

UCC27210UCC27211

https://www.sodocs.net/doc/e52073533.html, ZHCS501E –NOVEMBER 2011–REVISED AUGUST 2013

120V 升压,4A 峰值电流,高频高侧和低侧驱动器

查询样片:UCC27210,UCC27211

特性

应用范围?用独立输入驱动高侧和低侧配置中的两个N 通道金

?针对电信,数据通信和商用的电源属氧化物半导体场效应晶体管(MOSFET)

?半桥和全桥转换器?最大引导电压120V 直流

?推挽转换器?4A 吸收,4A 源输出电流

?高电压同步降压型转换器?0.9Ω上拉和下拉电阻

?两开关正激式转换器?输入引脚能够耐受-10V 至20V 的电压,并且与电

?有源箝位正激式转换器源电压范围无关

?D 类音频放大器?晶体管-晶体管逻辑电路(TTL)或伪CMOS 兼容输

入版本

说明?8V 至17V VDD 运行范围,(绝对最大值20V )

UCC27210和UCC27211驱动器基于常见的?7.2ns 上升和5.5ns 下降时间(采用1000pF 负载

UCC27200和UCC27201MOSFET 驱动器,但是对时)

性能进行了几项重大改进。峰值输出上拉和下拉电流?快速传播延迟时间(典型值18ns)

已经被增加至4A 拉电流和4A 灌电流,并且上拉和下?2ns 延迟匹配

拉电阻已经被减少至0.9Ω,因此可以在MOSFET 的?用于高侧和低侧驱动器的对称欠压闭锁功能

米勒效应平台转换期间用尽可能小的开关损耗来驱动大?可提供全部行业标准封装(小外形尺寸集成电路

功率MOSFET 。现在,输入结构能够直接处理-10(SOIC)-8封装,PowerPAD?SOIC-8,4mm x

VDC ,这增加了稳健耐用性,并且可实现与栅极驱动4mm 小外形尺寸无引线(SON)-8封装和4mm x

变压器的直接对接,而无需使用整流二极管。此输入4mm SON-10)

与电源电压无关,并且具有一个20V 的最大额定值。?

-40℃至140℃的额定温度范围典型应用图

Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

UCC27210

UCC27211

ZHCS501E–NOVEMBER2011–REVISED https://www.sodocs.net/doc/e52073533.html, 说明(续)

UCC27210/1的开关节点(HS引脚)能够处理-18V最大电压,这可保护高侧通道不受固有负电压所导致的寄生电感和离散电容的损坏。UCC27210(伪CMOS输入)和UCC27211(TTL输入)已经增加了滞后,从而使得到模拟或数字脉宽调制(PWM)控制器的接口具有增强的抗扰度。

低端和高端栅极驱动器是独立控制的,并在彼此的接通和关断之间实现了至2ns的匹配。

由于在芯片上集成了一个额定电压为120V的自举二极管,因此无需采用外部分立式二极管。为高端和低端驱动器提供了欠压闭锁功能,如果驱动电压低于额定的阀值电压,则提供对称接通/关闭运行方式,并且强制输出为低电平。

这两款器件均采用8引脚SOIC(D),PowerPad?SOIC-8(DDA),4mm x4mm SON-8(DRM)和SON-10(DPR)封装。

These devices have limited built-in ESD protection.The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION(1)

PACKAGED DEVICES(1)

INPUT

TEMPERATURE RANGE T A=T J PowerPAD?

COMPATIBILITY SOIC-8(D)(2)SON-8(DRM)(3)SON-10(DPR)(4)

SOIC-8(DDA)(2)

Pseudo CMOS UCC27210D UCC27210DDA UCC27210DRM UCC27210DPR -40°C to140°C

TTL UCC27211D UCC27211DDA UCC27211DRM UCC27211DPR (1)These products are packaged in Lead(Pb)-Free and green lead finish of PdNiAu which is compatible with MSL level1at255°C to

260°C peak reflow temperature to be compatible with either lead free or Sn/Pb soldering operations.

(2)D(SOIC-8)and DDA(Power Pad?SOIC-8)packages are available taped and reeled.Add R suffix to device type(e.g.

UCC27210ADR/UCC27211ADR)to order quantities of2,500devices per reel.

(3)DRM(SON-8)package comes either in a small reel of250pieces as part number UCC27210ADRMT/UCC27211ADRMT,or larger reels

of3000pieces as part number UCC27210ADRMR/UCC27211ADRMR.

(4)DPR(SON-10)package comes either in a small reel of250pieces as part number UCC27210ADPRT/UCC27211ADPRT,or large reels

of3000pieces as part number UCC27210ADPRR/UCC27211ADPRR.

UCC27210

UCC27211 https://www.sodocs.net/doc/e52073533.html, ZHCS501E–NOVEMBER2011–REVISED AUGUST2013 ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range(unless otherwise noted)

MIN MAX UNIT Supply voltage range,V DD(1),V HB-V HS-0.320

Input voltages on LI and HI,V LI,V HI-1020

DC-0.3V DD+0.3

Output voltage on LO,V LO

Repetitive pulse<100ns(2)-2V DD+0.3

DC V HS–0.3V HB+0.3V Output voltage on HO,V HO

Repetitive pulse<100ns(2)V HS-2V HB+0.3

DC-1115

Voltage on HS,V HS

Repetitive pulse<100ns(2)-(24V-VDD)115

Voltage on HB,V HB-0.3120

Human Body Model(HBM)2

ESD kV

Field Induced Charged Device Model

1

(FICDM)

Operating virtual junction temperature range,T J-40150

Storage temperature,T STG-65150°C

Lead temperature(soldering,10sec.)300

(1)All voltages are with respect to VSS unless otherwise noted.Currents are positive into,negative out of the specified terminal.

(2)Verified at bench characterization.VDD is the value used in an application design.

RECOMMENDED OPERATING CONDITIONS

all voltages are with respect to V SS;currents are positive into and negative out of the specified terminal.–40°C

PARAMETER MIN TYP MAX UNIT Supply voltage range,V DD,V HB-V HS81217

Voltage on HS,V HS-1105

V Voltage on HS,V HS(repetitive pulse<100ns)-(24V-VDD)110

V HS+8,V HS+17,

Voltage on HB,V HB

V DD–1115

Voltage slew rate on HS50V/ns Operating junction temperature range-40140°C

UCC27210

UCC27211

ZHCS501E–NOVEMBER2011–REVISED https://www.sodocs.net/doc/e52073533.html, THERMAL INFORMATION

UCC27210/11(1)

THERMAL METRIC D DDA UNITS

8PINS8PINS

θJA Junction-to-ambient thermal resistance(2)111.837.7

θJCtop Junction-to-case(top)thermal resistance(3)56.947.2

θJB Junction-to-board thermal resistance(4)53.09.6

°C/W

ψJT Junction-to-top characterization parameter(5)7.8 2.8

ψJB Junction-to-board characterization parameter(6)52.39.4

θJCbot Junction-to-case(bottom)thermal resistance(7)n/a 3.6

(1)For more information about traditional and new thermal metrics,see the IC Package Thermal Metrics application report,SPRA953.

(2)The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard,high-K board,as

specified in JESD51-7,in an environment described in JESD51-2a.

(3)The junction-to-case(top)thermal resistance is obtained by simulating a cold plate test on the package top.No specific JEDEC-

standard test exists,but a close description can be found in the ANSI SEMI standard G30-88.

(4)The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature,as described in JESD51-8.

(5)The junction-to-top characterization parameter,ψJT,estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtainingθJA,using a procedure described in JESD51-2a(sections6and7).

(6)The junction-to-board characterization parameter,ψJB,estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtainingθJA,using a procedure described in JESD51-2a(sections6and7).

(7)The junction-to-case(bottom)thermal resistance is obtained by simulating a cold plate test on the exposed(power)pad.No specific

JEDEC standard test exists,but a close description can be found in the ANSI SEMI standard G30-88.

THERMAL INFORMATION

UCC27210/11(1)

THERMAL METRIC DRM DPR UNITS

8PINS10PINS

θJA Junction-to-ambient thermal resistance(2)33.936.8

θJCtop Junction-to-case(top)thermal resistance(3)33.236.0

θJB Junction-to-board thermal resistance(4)11.414.0

°C/W

ψJT Junction-to-top characterization parameter(5)0.40.3

ψJB Junction-to-board characterization parameter(6)11.714.2

θJCbot Junction-to-case(bottom)thermal resistance(7) 2.3 3.4

(1)For more information about traditional and new thermal metrics,see the IC Package Thermal Metrics application report,SPRA953.

(2)The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard,high-K board,as

specified in JESD51-7,in an environment described in JESD51-2a.

(3)The junction-to-case(top)thermal resistance is obtained by simulating a cold plate test on the package top.No specific JEDEC-

standard test exists,but a close description can be found in the ANSI SEMI standard G30-88.

(4)The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature,as described in JESD51-8.

(5)The junction-to-top characterization parameter,ψJT,estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtainingθJA,using a procedure described in JESD51-2a(sections6and7).

(6)The junction-to-board characterization parameter,ψJB,estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtainingθJA,using a procedure described in JESD51-2a(sections6and7).

(7)The junction-to-case(bottom)thermal resistance is obtained by simulating a cold plate test on the exposed(power)pad.No specific

JEDEC standard test exists,but a close description can be found in the ANSI SEMI standard G30-88.

UCC27210

UCC27211 https://www.sodocs.net/doc/e52073533.html, ZHCS501E–NOVEMBER2011–REVISED AUGUST2013 ELECTRICAL CHARACTERISTICS

V DD=V HB=12V,V HS=V SS=0V,no load on LO or HO,T A=T J=-40°C to140°C,(unless otherwise noted)

PARAMETER TEST CONDITION MIN TYP MAX UNITS

Supply Currents

I DD V DD quiescent current V(LI)=V(HI)=0V0.050.0850.17

I DDO UCC27210 2.6 5.2

V DD operating current f=500kHz,C LOAD=0

UCC27211 2.5 5.2mA

I HB Boot voltage quiescent current V(LI)=V(HI)=0V0.0150.0650.1

I HBO Boot voltage operating current f=500kHz,C LOAD=0 2.5 5.0

I HBS HB to V SS quiescent current V(HS)=V(HB)=115V0.0005 1.0μA

I HBSO HB to V SS operating current f=500kHz,C LOAD=00.07 1.2mA

Input

V HIT Input voltage threshold UCC27210 4.2 5.0 5.8

UCC27210(DDA only) 4.2 5.0 5.9

V LIT Input voltage threshold UCC27210 2.4 3.2 4.0V

UCC27210(DDA only) 2.4 3.2 4.0

V IHYS Input voltage hysteresis 1.8

UCC27210

R IN Input pulldown resistance102kΩ

V HIT Input voltage threshold UCC27211 1.9 2.3 2.7

UCC27211(DDA only) 1.9 2.3 2.8

V

V LIT Input voltage threshold UCC27211 1.3 1.6 1.9

UCC27211(DDA only) 1.3 1.6 2.1

V IHYS Input voltage hysteresis700mV

UCC27211

R IN Input pulldown resistance68kΩ

Under-Voltage Lockout(UVLO)

V DDR V DD turn-on threshold 6.27.07.8

DDA only 5.87.08.1

V DDHYS Hysteresis0.5

V

V HBR V HB turn-on threshold 5.6 6.77.9

DDA only 5.3 6.78.0

V HBHYS Hysteresis 1.1

Bootstrap Diode

V F Low-current forward voltage I VDD-HB=100μA0.650.8

V

V FI High-current forward voltage I VDD-HB=100mA0.850.95

R D Dynamic resistance,ΔVF/ΔI I VDD-HB=100mA and80mA0.30.50.85Ω

LO Gate Driver

V LOL Low-level output voltage I LO=100mA0.050.090.19

V

V LOH High level output voltage I LO=-100mA,V LOH=V DD-V LO0.10.160.29

Peak pull-up current(1)V LO=0V 3.7

A Peak pull-down current(1)V LO=12V 4.5

HO GATE Driver

V HOL Low-level output voltage I HO=100mA0.050.090.19

V

V HOH High-level output voltage I HO=-100mA,V HOH=V HB-V HO0.10.160.29

Peak pull-up current(1)V HO=0V 3.7

A Peak pull-down current(1)V HO=12V 4.5

(1)Ensured by design.

UCC27210

UCC27211

ZHCS501E–NOVEMBER2011–REVISED https://www.sodocs.net/doc/e52073533.html, ELECTRICAL CHARACTERISTICS(continued)

V DD=V HB=12V,V HS=V SS=0V,no load on LO or HO,T A=T J=-40°C to140°C,(unless otherwise noted)

PARAMETER TEST CONDITION MIN TYP MAX UNITS

Switching Parameters:Propagation Delays

T DLFF V LI falling to V LO falling152137

T DHFF V HI falling to V HO falling152137

UCC27210,C LOAD=0

T DLRR V LI rising to V LO rising152446

T DHRR V HI rising to V HO rising152446

ns

T DLFF V LI falling to V LO falling101730

T DHFF V HI falling to V HO falling101730

UCC27211,C LOAD=0

T DLRR V LI rising to V LO rising101840

T DHRR V HI rising to V HO rising101840

Switching Parameters:Delay Matching

T J=25°C311

T MON From HO OFF to LO ON ns

T J=–40°C to140°C314

UCC27210

T J=25°C311

T MOFF From LO OFF to HO ON ns

T J=–40°C to140°C314

T J=25°C29.5

T MON From HO OFF to LO ON ns

T J=–40°C to140°C214

UCC27211

T J=25°C29.5

T MOFF From LO OFF to HO ON ns

T J=–40°C to140°C214

Switching Parameters:Output Rise and Fall Time

t R LO rise time7.2

C LOAD=1000pF,from10%to90%

t R HO rise time7.2

ns

t F LO fall time 5.5

C LOAD=1000pF,from90%to10%

t F HO fall time 5.5

t R LO,HO C LOAD=0.1μF,(3V to9V)0.360.6

μs

t F LO,HO C LOAD=0.1μF,(9V to3V)0.150.4

Switching Parameters:Miscellaneous

Minimum input pulse width that changes the

50 output ns

Bootstrap diode turn-off time(2)(3)I F=20mA,I REV=0.5A(4)20

(2)Ensured by design.

(3)I F:Forward current applied to bootstrap diode,I REV:Reverse current applied to bootstrap diode.

(4)Typical values for T A=25°C.

Input (HI,LI)

Output (HO,

MON MOFF

LI

HI

LO

UCC27210

UCC27211

https://www.sodocs.net/doc/e52073533.html, ZHCS501E–NOVEMBER2011–REVISED AUGUST2013

Timing Diagrams

VDD HB HO HS NC LO VSS

LI

HI

NC 10912345876

SON-10 (DPR)TOP

VIEW VDD HB HO HS VSS

Power Pad TM SOIC-8(DDA)TOP VIEW

LO LI

HI

VDD HB HO HS LO VSS LI

HI SOIC-8(D)

TOP VIEW VDD HB HO HS VSS SON-8(DRM)

TOP VIEW

LO LI HI

HI

LI V DD HB HO HS LO

V SS UCC27210UCC27211

ZHCS501E –NOVEMBER 2011–REVISED AUGUST https://www.sodocs.net/doc/e52073533.html,

DEVICE INFORMATION

Functional Block Diagram

UCC27210

UCC27211 https://www.sodocs.net/doc/e52073533.html, ZHCS501E–NOVEMBER2011–REVISED AUGUST2013

TERMINAL FUNCTIONS

PIN

PIN NAME DESCRIPTION

D/DDA/DRM DPR

Positive supply to the lower-gate driver.De-couple this pin to V SS(GND).Typical VDD11

decoupling capacitor range is0.22μF to4.7μF(See(1)).

High-side bootstrap supply.The bootstrap diode is on-chip but the external bootstrap

capacitor is required.Connect positive side of the bootstrap capacitor to this pin.

HB22Typical range of HB bypass capacitor is0.022μF to0.1μF.The capacitor value is

dependant on the gate charge of the high-side MOSFET and should also be selected

based on speed and ripple criteria

HO33High-side output.Connect to the gate of the high-side power MOSFET.

High-side source connection.Connect to source of high-side power MOSFET.

HS44

Connect the negative side of bootstrap capacitor to this pin.

HI57High-side input.(2)

LI68Low-side input.(2)

VSS79Negative supply terminal for the device which is generally grounded.

LO810Low-side output.Connect to the gate of the low-side power MOSFET.

N/C-5/6Not Connected.

Utilized on the DDA,DRM and DPR packages only.Electrically referenced to V SS PowerPAD?(3)Pad Pad(GND).Connect to a large thermal mass trace or GND plane to dramatically improve

thermal performance.

(1)For cold temperature applications we recommend the upper capacitance range.Attention should also be made to PCB layout-see

Layout Recommendations.

(2)HI or LI input is assumed to connect to a low impedance source signal.The source output impedance is assumed less than100Ω.If the

source impedance is greater than100Ω,add a bypassing capacitor,each,between HI and VSS and between LI and VSS.The added capacitor value depends on the noise levels presented on the pins,typically from1nF to10nF should be effective to eliminate the possible noise effect.When noise is present on two pins,HI or LI,the effect is to cause HO and LO malfunctions to have wrong logic outputs.

(3)The PowerPAD?is not directly connected to any leads of the package.However it is electrically and thermally connected to the

substrate which is the ground of the device.

?10

123456

V DD ? Supply Voltage (V)H I , L I ? I n p u t T h r e s h o l d V o l t a g e (V )G005 ?10123456

Temperature (°C)H I , L I ? I n p u t T h r e s h o l d V o l t a g e (V )G006 0.010.111010010

100

1000Frequency (kHz)I D D O ? O p e r a t i n g C u r r e n t (m A )G003 0.01

0.1110100101001000

Frequency (kHz)I H B O ? O p e r a t i n g C u r r e n t (m A )G004 02040

6080

100

02468101214161820V DD = V HB ? Supply Voltage (V)I D D , I H B ? Q u i e s c e n t C u r r e n t (μA )G001 0.01

0.111010010

100

1000Frequency (kHz)I D D O ? O p e r a t i n g C u r r e n t (m A )G002 UCC27210UCC27211

ZHCS501E –NOVEMBER 2011–REVISED AUGUST https://www.sodocs.net/doc/e52073533.html,

TYPICAL CHARACTERISTICS

QUIESCENT CURRENT UCC27210IDD OPERATING CURRENT vs vs Figure 1.

Figure 2.UCC27211IDD OPERATING CURRENT BOOT VOLTAGE OPERATING CURRENT vs vs FREQUENCY

FREQUENCY (HB to HS)Figure 3.

Figure 4.UCC27210/11INPUT THRESHOLD UCC27210/11INPUT THRESHOLDS vs vs SUPPLY VOLTAGE

TEMPERATURE Figure 5.Figure 6.

04

8

12

162024283236

40

Temperature (°C)P r o p a g a t i o n D e l a y (n s )G011 081624

32Temperature (°C)P r o p a g a t i o n D e l a y (n s )

G012 5.25.666.46.87.27.6

8

Temperature (°C)T h r e s h o l d (V )

G009 00.30.60.91.2

1.5Temperature (°C)H y s t e r e s i s (V )

G010

00.04

0.08

0.120.160.20.240.280.32

Temperature (°C)V O H ? L O /H O O u t p u t V o l t a g e (V )G007 00.040.080.120.16

0.2Temperature (°C)V O L ? L O /H O O u t p u t V o l t a g e (V )G008 UCC27210UCC27211

https://www.sodocs.net/doc/e52073533.html, ZHCS501E –NOVEMBER 2011–REVISED AUGUST 2013

TYPICAL CHARACTERISTICS (continued)

LO AND HO HIGH LEVEL OUTPUT VOLTAGE LO AND HO LOW LEVEL OUTPUT VOLTAGE vs vs TEMPERATURE TEMPERATURE Figure 7.

Figure 8.UNDERVOLTAGE LOCKOUT THRESHOLD UNDERVOLTAGE LOCKOUT THRESHOLD HYSTERESIS vs vs TEMPERATURE TEMPERATURE Figure 9.

Figure 10.UCC27210PROPAGATION DELAYS UCC27211PROPAGATION DELAYS vs vs TEMPERATURE

TEMPERATURE Figure 11.Figure 12.

0.0010.01

0.1

110

100500550600650700750

800850Diode Voltage (mV)D i o d e C u r r e n t (m A )G017

?20

246810

Temperature (°C)D e l a y M a t c h i n g (n s )G015 0

12345

V LO , V HO ? Output Voltage (V)I L O , I H O ? O u t p u t C u r r e n t (A )

G016 04

8

1216202428

32

V DD =V HB ? Supply Voltage (V)P r o p a g a t i o n D e l a y (n s )

G012 048121620242832V DD =V HB ? Supply Voltage (V)P r o p a g a t i o n D e l a y (n s )G014

UCC27210UCC27211

ZHCS501E –NOVEMBER 2011–REVISED AUGUST https://www.sodocs.net/doc/e52073533.html,

TYPICAL CHARACTERISTICS (continued)

UCC27210PROPAGATION DELAYS UCC27211PROPAGATION DELAYS vs vs SUPPLY VOLTAGE SUPPLY VOLTAGE Figure 13.

Figure 14.DELAY MATCHING OUTPUT CURRENT vs vs TEMPERATURE

OUTPUT VOLTAGE Figure 15.

Figure 16.DIODE CURRENT vs DIODE VOLTAGE NEGATIVE 10-V INPUT

Figure 17.Figure 18.

UCC27210UCC27211

https://www.sodocs.net/doc/e52073533.html, ZHCS501E –NOVEMBER 2011–REVISED AUGUST 2013

TYPICAL CHARACTERISTICS (continued)

STEP INPUT SYMMETRICAL UVLO

Figure 19.Figure 20.

UCC27210

UCC27211

ZHCS501E–NOVEMBER2011–REVISED https://www.sodocs.net/doc/e52073533.html,

APPLICATION INFORMATION

Functional Description

The UCC27210/11represent Texas Instruments’latest generation of high voltage gate drivers which are designed to drive both the high-side and low-side of N-Channel MOSFETs in a half-/full-bridge or synchronous buck configuration.The floating high-side driver is capable of operating with supply voltages of up to120V.This allows for N-Channel MOSFET control in half-bridge,full-bridge,push pull,two-switch forward and active clamp forward converters.

The UCC27210/11feature4-A source/sink capability,industry best-in-class switching characteristics and a host of other features listed in the table below.These features combine to ensure efficient,robust and reliable operation in high-frequency switching power circuits.

Table1.UCC27210/11Highlights

FEATURE BENEFIT

High peak current ideal for driving large power MOSFETs with

4-A source and sink current with0.9-Ωoutput resistance

minimal power loss(fast-drive capability at Miller plateau)

Increased robustness and ability to handle under/overshoot.Can Input pins(HI and LI)can directly handle-10VDC up to20VDC interface directly to gate-drive transformers without having to use

rectification diodes

120-V internal boot diode Provides voltage margin to meet telecom100-V surge requirements

Allows the high-side channel to have extra protection from inherent Switch node(HS pin)able to handle-18V maximum for100ns negative voltages caused parasitic inductance and stray

capacitance.

Robust ESD circuitry to handle voltage spikes Excellent immunity to large dV/dT conditions

Best-in-class switching characteristics and extremely low-pulse

18-ns propagation delay with7.2-ns/5.5-ns rise/fall Times

transmission distortion

2-ns(typ)delay matching between channels Avoids transformer volt-second offset in bridge

Symmetrical UVLO circuit Ensures high-side and low-side shut down at the same time

CMOS optimized threshold or TTL optimized thresholds with Complementary to analog or digital PWM controllers.Increased increased hysteresis hysteresis offers added noise immunity

In UCC27210/11,the high side and low side each have independent inputs which allow maximum flexibility of input control signals in the application.The boot diode for the high-side driver bias supply is internal to the UCC27210and UCC27211.The UCC27210is the Pseudo-CMOS compatible input version and the UCC27211 is the TTL or logic compatible version.The high-side driver is referenced to the switch node(HS)which is typically the source pin of the high-side MOSFET and drain pin of the low-side MOSFET.The low-side driver is referenced to V SS which is typically ground.The functions contained are the input stages,UVLO protection,level shift,boot diode,and output driver stages.

UCC27210

UCC27211 https://www.sodocs.net/doc/e52073533.html, ZHCS501E–NOVEMBER2011–REVISED AUGUST2013 Input Stages

The input stages provide the interface to the PWM output signals.The input impedance of the UCC27210is100 kΩnominal and input capacitance is approximately2pF.The100kΩis a pull-down resistance to V SS(ground). The UCC27210Pseudo-CMOS input structure has been designed to provide large hysteresis and at the same time to allows interfacing to a multitude of analog or digital PWM controllers.In some CMOS designs,the input thresholds are determined as a percentage of VDD.By doing so,the high-level input threshold can become unreasonably high and unusable.The UCC27210recognizes the fact that VDD levels are trending downward and it therefore provides a rising threshold with5.0V(typ)and falling threshold with3.2V(typ).The input hysteresis of the UCC27210is1.8V(typ).

The input stages of the UCC27211have impedance of70kΩnominal and input capacitance is approximately2 pF.Pull-down resistance to V SS(ground)is70kΩ.The logic level compatible input provides a rising threshold of 2.3V and a falling threshold of1.6V.

Under Voltage Lockout(UVLO)

The bias supplies for the high-side and low-side drivers have UVLO protection.V DD as well as V HB to V HS differential voltages are monitored.The V DD UVLO disables both drivers when V DD is below the specified threshold.The rising V DD threshold is7.0V with0.5-V hysteresis.The VHB UVLO disables only the high-side driver when the V HB to V HS differential voltage is below the specified threshold.The V HB UVLO rising threshold is 6.7V with1.1-V hysteresis.

Level Shift

The level shift circuit is the interface from the high-side input to the high-side driver stage which is referenced to the switch node(HS).The level shift allows control of the HO output referenced to the HS pin and provides excellent delay matching with the low-side driver.

Boot Diode

The boot diode necessary to generate the high-side bias is included in the UCC27210/11family of drivers.The diode anode is connected to V DD and cathode connected to V HB.With the V HB capacitor connected to HB and the HS pins,the V HB capacitor charge is refreshed every switching cycle when HS transitions to ground.The boot diode provides fast recovery times,low diode resistance,and voltage rating margin to allow for efficient and reliable operation.

Output Stages

The output stages are the interface to the power MOSFETs in the power train.High slew rate,low resistance and high peak current capability of both output drivers allow for efficient switching of the power MOSFETs.The low-side output stage is referenced from V DD to V SS and the high side is referenced from V HB to V HS.

UCC27210

UCC27211

ZHCS501E–NOVEMBER2011–REVISED https://www.sodocs.net/doc/e52073533.html, Layout Recommendations

To improve the switching characteristics and efficiency of a design,the following layout rules should be followed.?Locate the driver as close as possible to the MOSFETs.

?Locate the V DD-V SS and V HB-V HS(bootstrap)capacitors as close as possible to the device(see example layout below).

?Pay close attention to the GND https://www.sodocs.net/doc/e52073533.html,e the thermal pad of the DDA and DRM package as GND by connecting it to the VSS pin(GND).The GND trace from the driver goes directly to the source of the MOSFET but should not be in the high current path of the MOSFET(S)drain or source current.

?Use similar rules for the HS node as for GND for the high-side driver.

?For systems using multiple UCC27210and UCC27211devices we recommend that dedicated decoupling capacitors be located at V DD-V SS for each device.

?Care should be taken to avoid VDD traces being close to LO,HS,and HO signals.

?Use wide traces for LO and HO closely following the associated GND or HS traces.60to100-mils width is preferable where possible.

?Use as least two or more vias if the driver outputs or SW node needs to be routed from one layer to another.

For GND the number of vias needs to be a consideration of the thermal pad requirements as well as parasitic inductance.

?Avoid LI and HI(driver input)going close to the HS node or any other high dV/dT traces that can induce significant noise into the relatively high impedance leads.

Keep in mind that a poor layout can cause a significant drop in efficiency or system malfunction versus a good PCB layout and can even lead to decreased reliability of the whole system.

Example

Additional References

These references and links to additional information may be found at https://www.sodocs.net/doc/e52073533.html,

?Additional layout guidelines for PCB land patterns may be found in,QFN/SON PCB Attachment,Application Brief(Texas Instrument's Literature Number SLUA271)

?Additional thermal performance guidelines may be found in,PowerPAD?Thermally Enhanced Package Application Report,Application Report(Texas Instrument's Literature Number SLMA002A)

?Additional thermal performance guidelines may be found in,PowerPAD?Made Easy,Application Report (Texas Instrument's Literature Number SLMA004)

UCC27210

UCC27211 https://www.sodocs.net/doc/e52073533.html, ZHCS501E–NOVEMBER2011–REVISED AUGUST2013

REVISION HISTORY

Changes from Revision A(November,2011)to Revision B Page ?Changed ordering information notes to reflect corrected part number (2)

Changes from Revision B(February)to Revision C Page ?Changed V DD operating current max range of4.3to4.4in both places (5)

?Changed Boot voltage operating current max range from4.0to4.2 (5)

?Changed HB to V SS quiescent current max range from0.13to1.0 (5)

?Changed HB to V SS operating current max range from0.9to1.1 (5)

?Added Input UCC27210/11(DDA Only)values (5)

?Added Under-Voltage Lockout(UVLO)DDA only values,two places (5)

?Changed LO Gate Driver's Low-level output voltage max range from0.15to0.17 (5)

?Changed LO Gate Driver's V LOH max range from0.27to0.29 (5)

?Changed HO GATE Driver's Low-level output voltage max range from0.15to0.17 (5)

?Changed V LI falling to V LO falling min value from17to15 (6)

?Changed V HI falling to V HO falling min value from17to15 (6)

?Changed V LI rising to V LO rising min value from18to15 (6)

?Changed V HI rising to V HO rising min value from18to15 (6)

?Changed Figure17,Output Current vs.Output Voltage (12)

Changes from Revision C(March,2012)to Revision D Page ?Changed capacitor range from1.0μF to4.7μF (9)

?Added Terminal Functions Note to HI and LI pin description (9)

?Changed bullet2in the Layout Recommendations (16)

?Added Note:For systems using (16)

?Added Note:Care should be taken (16)

Changes from Revision C(November,2012)to Revision E Page ?Changed Repetitive pulse data from-18V to-(24V-VDD) (3)

?Added additional details to Note2 (3)

?Changed Voltage on HS,V HS(repetitive pulse<100ns)data from-15to-(24V-VDD) (3)

?Deleted2.4-mA operating current min range in both places (5)

?Changed operating current max range extended to5.2in both places (5)

?Deleted1.5min Boot voltage operating current range (5)

?Changed Boot voltage operating current max range from4.2to5.0 (5)

?Changed HB to V SS operating current max range from1.1to1.2 (5)

?Changed LO Gate Driver's Low-level output voltage max range from0.17to0.19 (5)

?Changed HO GATE Driver's Low-level output voltage max range from0.17to0.19 (5)

?Added Note2to the Terminal Functions Table (9)

PACKAGING INFORMATION

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

Addendum-Page 1

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check https://www.sodocs.net/doc/e52073533.html,/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

TAPE AND REEL INFORMATION

*All dimensions are nominal Device Package Type Package Drawing

Pins

SPQ Reel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant UCC27210DDAR SO

Power

PAD

DDA 82500330.012.8 6.4 5.2 2.18.012.0Q1UCC27210DPRR WSON

DPR 103000330.012.4 4.25 4.25 1.158.012.0Q2UCC27210DPRT WSON

DPR 10250180.012.4 4.25 4.25 1.158.012.0Q2UCC27210DR SOIC

D 82500330.012.4 6.4 5.2 2.18.012.0Q1UCC27210DRMR VSON

DRM 83000330.012.4 4.25 4.25 1.158.012.0Q2UCC27210DRMT VSON

DRM 8250180.012.4 4.25 4.25 1.158.012.0Q2UCC27211DDAR SO

Power

PAD

DDA 82500330.012.8 6.4 5.2 2.18.012.0Q1UCC27211DPRR WSON

DPR 103000330.012.4 4.25 4.25 1.158.012.0Q2UCC27211DPRT WSON

DPR 10250180.012.4 4.25 4.25 1.158.012.0Q2UCC27211DR SOIC

D 82500330.012.4 6.4 5.2 2.18.012.0Q1UCC27211DRMR VSON

DRM 83000330.012.4 4.25 4.25 1.158.012.0Q2UCC27211DRMT VSON DRM 8250180.012.4 4.25 4.25 1.158.012.0Q2

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